coreboot October 2011

coreboot@coreboot.org

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501 discussions

Patch merged into coreboot/master: 4fa81f7 Fix libpayload speaker driver
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit 4fa81f7cbcce03bb8679a69f073cd9317fde4412 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 14:15:57 2011 -0700 Fix libpayload speaker driver The frequency for the PC speaker has to be specified as 1193180 / frequency according to http://wiki.osdev.org/PC_Speaker Change-Id: Iaca9d45807e080efe834611e719b350680b5fb90 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Oct 27 10:49:36 2011, giving +2 See http://review.coreboot.org/337 for details. -gerrit

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Re: [coreboot] Status of SeaBIOS VGA bios.
by Kevin O'Connor 27 Oct '11

27 Oct '11

On Wed, Oct 26, 2011 at 02:06:53AM +0100, Julian Pidancet wrote: > On Wed, Oct 26, 2011 at 1:26 AM, Kevin O'Connor <kevin(a)koconnor.net> wrote: > > It should work. Ideally, someone would complete the port of the "lgpl > > vgabios". This involves translating the remaining 16bit assembler to > > C code and then doing lots of testing on the result. > > I havn't tried to run the ROM yet. Could you be more precise about > what works (or what is supposed to be working), what's not, and what > exactly remains to be translated ? I'd like to make an idea of the > amount of work required to have a ROM equivalent to vgabios. If you look at the "lgpl vgabios" source - I ported vgabios.c but did not convert vbe.c nor clext.c. As for what works - I was able to launch qemu and run guests. However, the vbe extensions weren't present, and so most guests wouldn't attempt to increase resolution or they had other features not available. Also, I was seeing the grub screen come up as black-and-white - which may be due to lack of VBE, but may also have been due to a bug somewhere in the port. -Kevin

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Porting to Adlink Express ATR?
by Holdsworth, Joel 26 Oct '11

26 Oct '11

Hi All, I'm currently doing some with with the Adlink Express ATR COM Express module, and I'm grappling with a broken American Megatrends BIOS with a misconfigured WiFi PCI whitelist. Can anyone comment on how hard it would be to get coreboot working on this hardware? CPU: Intel Atom N270 Northbridge: Intel 82945GSE (GMCH) Southbridge/Super-IO: Intel 82801GBM (ICH7M) Best Regards Joel Holdsworth ______________________________________________ Joel Holdsworth - Engineer t +44 (0)1483 816052 a Detica | Surrey Research Park | Guildford | GU2 7YP | UK ______________________________________________ www.detica.com <http://www.detica.com/> Please consider the environment before printing this email. This message should be regarded as confidential. If you have received this email in error please notify the sender and destroy it immediately. Statements of intent shall only become binding when confirmed in hard copy by an authorised signatory. The contents of this email may relate to dealings with other companies under the control of BAE Systems plc details of which can be found at http://www.baesystems.com/Businesses/index.htm. Detica Limited is a BAE Systems company trading as BAE Systems Detica. Detica Limited is registered in England and Wales under No: 1337451. Registered office: Surrey Research Park, Guildford, Surrey, GU2 7YP, England.

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Re: [coreboot] "No valid softstrap base found." hang?
by Kyösti Mälkki 26 Oct '11

26 Oct '11

On Wed, 2011-10-26 at 16:42 +0300, Alp Eren Köse wrote: > Ok I get passed the "Setting up RAM controller." now, but stuck now in > "Setting up RAM" as can be seen above I print the detected softstrap > base, and it says fffc0000. Wild guess, but where did I put that CMC binary again? KM

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New patch to review for coreboot: 0144f26 Enable easy transition away from big bootblock
by Kyösti Mälkki 26 Oct '11

26 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/339 -gerrit commit 0144f260825a50f703db8b3a6ff517e91adedbf9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Oct 26 18:29:08 2011 +0300 Enable easy transition away from big bootblock In short, mainboard Kconfig flags where inverted, resulting in a situation where a flag is removed once the mainboard no longer uses a deprecated functionality. Default behaviour for a mainboard remains unchanged, but the user is presented with a choice in menuconfig to switch to tiny bootblock. The switch is presented to both CAR and no-CAR boards without the requirement of expert mode. Complete workflow of the change starts here: http://review.coreboot.org/315 Change-Id: I96024ca4ce3032ddc6a845a0ec345dd3673aa9d4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- src/arch/x86/Kconfig | 53 ++++++++++++++++++--- src/arch/x86/Makefile.inc | 21 ++++----- src/cpu/Kconfig | 4 -- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/amd/model_gx2/Kconfig | 1 - src/cpu/amd/model_lx/Kconfig | 1 - src/cpu/amd/socket_754/Kconfig | 1 - src/cpu/amd/socket_939/Kconfig | 1 - src/cpu/amd/socket_940/Kconfig | 1 - src/cpu/amd/socket_AM2/Kconfig | 1 - src/cpu/amd/socket_AM2r2/Kconfig | 1 - src/cpu/amd/socket_AM3/Kconfig | 1 - src/cpu/amd/socket_ASB2/Kconfig | 1 - src/cpu/amd/socket_C32/Kconfig | 1 - src/cpu/amd/socket_F/Kconfig | 1 - src/cpu/amd/socket_F_1207/Kconfig | 1 - src/cpu/amd/socket_S1G1/Kconfig | 1 - src/cpu/intel/car/cache_as_ram.inc | 2 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 2 +- src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +- src/cpu/intel/model_6fx/cache_as_ram.inc | 2 +- src/cpu/intel/slot_1/Kconfig | 1 - src/cpu/intel/socket_441/Kconfig | 1 - src/cpu/intel/socket_FC_PGA370/Kconfig | 2 - src/cpu/intel/socket_PGA370/Kconfig | 1 - src/cpu/intel/socket_mFCBGA479/Kconfig | 1 - src/cpu/intel/socket_mFCPGA478/Kconfig | 1 - src/cpu/intel/socket_mPGA479M/Kconfig | 1 - src/cpu/intel/socket_mPGA604/Makefile.inc | 2 + src/cpu/via/car/cache_as_ram.inc | 2 +- src/cpu/via/model_c7/Kconfig | 1 - src/cpu/x86/mtrr/earlymtrr.c | 8 +++- src/include/cpu/x86/mtrr.h | 2 +- src/mainboard/aaeon/pfm-540i_revb/Kconfig | 1 + src/mainboard/advansus/a785e-i/Kconfig | 1 - src/mainboard/advantech/pcm-5820/Kconfig | 3 +- src/mainboard/amd/db800/Kconfig | 1 + src/mainboard/amd/inagua/Kconfig | 1 - src/mainboard/amd/norwich/Kconfig | 1 + src/mainboard/amd/persimmon/Kconfig | 1 - src/mainboard/amd/rumba/Kconfig | 1 + src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 1 - src/mainboard/amd/torpedo/Kconfig | 1 - src/mainboard/artecgroup/dbe61/Kconfig | 1 + src/mainboard/asi/mb_5blgp/Kconfig | 3 +- src/mainboard/asi/mb_5blmp/Kconfig | 3 +- src/mainboard/asrock/e350m1/Kconfig | 1 - src/mainboard/asus/a8v-e_deluxe/Kconfig | 1 + src/mainboard/asus/a8v-e_se/Kconfig | 1 + src/mainboard/asus/m2v-mx_se/Kconfig | 1 - src/mainboard/asus/m2v/Kconfig | 1 - src/mainboard/asus/mew-am/Kconfig | 1 + src/mainboard/asus/mew-vm/Kconfig | 1 + src/mainboard/avalue/eax-785e/Kconfig | 1 - src/mainboard/axus/tc320/Kconfig | 3 +- src/mainboard/bcom/winnet100/Kconfig | 3 +- src/mainboard/bcom/winnetp680/Kconfig | 1 + src/mainboard/dell/s1850/Kconfig | 3 +- src/mainboard/digitallogic/adl855pc/Kconfig | 1 - src/mainboard/digitallogic/msm586seg/Kconfig | 3 +- src/mainboard/digitallogic/msm800sev/Kconfig | 1 + src/mainboard/eaglelion/5bcm/Kconfig | 3 +- src/mainboard/ecs/p6iwp-fe/Kconfig | 1 + src/mainboard/emulation/qemu-x86/Kconfig | 4 +- src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 + src/mainboard/ibase/mb899/Kconfig | 1 - src/mainboard/iei/juki-511p/Kconfig | 3 +- src/mainboard/iei/nova4899r/Kconfig | 3 +- src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 1 + src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/intel/eagleheights/Kconfig | 1 + src/mainboard/intel/jarrell/Kconfig | 3 +- src/mainboard/intel/jarrell/power_reset_check.c | 3 + src/mainboard/intel/jarrell/watchdog.c | 6 ++ src/mainboard/intel/mtarvon/Kconfig | 1 + src/mainboard/intel/truxton/Kconfig | 3 +- src/mainboard/intel/xe7501devkit/Kconfig | 3 +- src/mainboard/jetway/j7f24/Kconfig | 1 + src/mainboard/kontron/986lcd-m/Kconfig | 1 - src/mainboard/lanner/em8510/Kconfig | 1 - src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lippert/frontrunner/Kconfig | 1 + src/mainboard/lippert/hurricane-lx/Kconfig | 1 + src/mainboard/lippert/literunner-lx/Kconfig | 1 + src/mainboard/lippert/roadrunner-lx/Kconfig | 1 + src/mainboard/lippert/spacerunner-lx/Kconfig | 1 + src/mainboard/mitac/6513wu/Kconfig | 1 + src/mainboard/msi/ms6178/Kconfig | 1 + src/mainboard/msi/ms9652_fam10/Kconfig | 1 - src/mainboard/nec/powermate2000/Kconfig | 1 + src/mainboard/pcengines/alix1c/Kconfig | 1 + src/mainboard/pcengines/alix2d/Kconfig | 1 + src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/roda/rk886ex/Kconfig | 1 + src/mainboard/supermicro/h8dmr_fam10/Kconfig | 1 - src/mainboard/supermicro/h8qgi/Kconfig | 1 - src/mainboard/supermicro/h8qme_fam10/Kconfig | 1 - src/mainboard/supermicro/x6dai_g/Kconfig | 3 +- src/mainboard/supermicro/x6dhe_g/Kconfig | 3 +- src/mainboard/supermicro/x6dhe_g2/Kconfig | 3 +- src/mainboard/supermicro/x6dhr_ig/Kconfig | 3 +- src/mainboard/supermicro/x6dhr_ig2/Kconfig | 3 +- src/mainboard/technologic/ts5300/Kconfig | 3 +- src/mainboard/televideo/tc7020/Kconfig | 3 +- src/mainboard/thomson/ip1000/Kconfig | 1 - src/mainboard/traverse/geos/Kconfig | 1 + src/mainboard/tyan/s2735/Kconfig | 2 +- src/mainboard/tyan/s2912_fam10/Kconfig | 1 - src/mainboard/via/epia-cn/Kconfig | 1 + src/mainboard/via/epia-m/Kconfig | 3 +- src/mainboard/via/epia-m700/Kconfig | 1 + src/mainboard/via/epia-n/Kconfig | 3 +- src/mainboard/via/epia/Kconfig | 3 +- src/mainboard/via/pc2500e/Kconfig | 1 + src/mainboard/via/vt8454c/Kconfig | 1 - src/mainboard/winent/pl6064/Kconfig | 1 + src/mainboard/wyse/s50/Kconfig | 1 + src/southbridge/amd/amd8111/Kconfig | 1 - src/southbridge/amd/sb600/Kconfig | 1 - src/southbridge/amd/sb700/Kconfig | 2 - src/southbridge/amd/sb800/Kconfig | 1 - src/southbridge/broadcom/bcm5785/Kconfig | 1 - src/southbridge/intel/i82371eb/Kconfig | 1 - src/southbridge/intel/i82801cx/early_smbus.c | 1 - src/southbridge/intel/sch/Kconfig | 1 - src/southbridge/nvidia/ck804/Kconfig | 1 - src/southbridge/nvidia/mcp55/Kconfig | 1 - src/southbridge/sis/sis966/Kconfig | 1 - 132 files changed, 165 insertions(+), 117 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 525d452..f823d7b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -881,7 +881,7 @@ config ENABLE_APIC_EXT_ID config WARNINGS_ARE_ERRORS bool - default y + default n config ID_SECTION_OFFSET hex diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f98cf5b..5fb7de5 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -30,22 +30,64 @@ config MAX_REBOOT_CNT int default 3 -config TINY_BOOTBLOCK +config NO_CACHE_AS_RAM bool default n +config MAYBE_CACHE_AS_RAM + bool + default n + +config USES_BIG_BOOTBLOCK + bool + default n + +config SWITCH_TO_TINY_BOOTBLOCK + bool "Switch setup to tiny bootblock (experimental)" + default n + depends on USES_BIG_BOOTBLOCK + help + Your mainboard has been converted to use Cache-As-Ram, but + for some reason it still uses big bootblock. + Make sure you have CBFS_PREFIX=fallback. While other + prefixes worked for big bootblock, they don't for tiny one. + + Beware: This may leave your system non-bootable! + +config CACHE_AS_RAM_OVERRIDE + bool "Enable Cache-As-Ram (experimental)" + default n + depends on MAYBE_CACHE_AS_RAM + help + Your mainboard has been converted to use Cache-As-Ram, but + we have not yet received any confirmation that it actually + works for this setup. + + Beware: This may leave your system non-bootable! + +config CACHE_AS_RAM + bool + default y if CACHE_AS_RAM_OVERRIDE + default n if NO_CACHE_AS_RAM + default n if MAYBE_CACHE_AS_RAM + default y + config BIG_BOOTBLOCK bool - default n if TINY_BOOTBLOCK + default n if BOARD_EMULATION_QEMU_X86 + default n if SWITCH_TO_TINY_BOOTBLOCK + default y if USES_BIG_BOOTBLOCK + default n if CACHE_AS_RAM default y +if !BIG_BOOTBLOCK + # We had to rename the choice options under arch/ because otherwise # the options would conflict between different architectures despite # the if ARCH_xxx guarding the arch/xxx/Kconfig sourcing. choice prompt "Bootblock behaviour" default X86_BOOTBLOCK_SIMPLE - depends on TINY_BOOTBLOCK config X86_BOOTBLOCK_SIMPLE bool "Always load fallback" @@ -63,16 +105,13 @@ config BOOTBLOCK_SOURCE config UPDATE_IMAGE bool "Update existing coreboot.rom image" default n - depends on TINY_BOOTBLOCK help If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified. -config ROMCC - bool - default n +endif config PC80_SYSTEM bool diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 65c2a92..64ae445 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -198,14 +198,11 @@ ifeq ($(CONFIG_SSE),y) crt0s += $(src)/cpu/x86/sse_enable.inc endif +# When some mainboards with a specific socket have been converted +# to cache-as-ram, but others haven't, cache_as_ram.inc is +# included only conditionally crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc @@ -225,11 +222,11 @@ crt0s += $(chipset_bootblock_inc) ldscripts += $(chipset_bootblock_lds) endif -ifeq ($(CONFIG_ROMCC),y) +ifeq ($(CONFIG_CACHE_AS_RAM),n) crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc endif -ifeq ($(CONFIG_ROMCC),y) +ifeq ($(CONFIG_CACHE_AS_RAM),n) ROMCCFLAGS ?= -mcpu=p2 -O2 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @@ -285,10 +282,10 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -ifeq ($(CONFIG_TINY_BOOTBLOCK),y) -include $(src)/arch/x86/Makefile.bootblock.inc -else +ifeq ($(CONFIG_BIG_BOOTBLOCK),y) include $(src)/arch/x86/Makefile.bigbootblock.inc +else +include $(src)/arch/x86/Makefile.bootblock.inc endif seabios: diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..3edc10b 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -5,10 +5,6 @@ source src/cpu/intel/Kconfig source src/cpu/via/Kconfig source src/cpu/x86/Kconfig -config CACHE_AS_RAM - bool - default !ROMCC - config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4899296..d625112 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -281,7 +281,7 @@ clear_fixed_var_mtrr_out: #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if CONFIG_TINY_BOOTBLOCK +#if !CONFIG_BIG_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE diff --git a/src/cpu/amd/model_gx2/Kconfig b/src/cpu/amd/model_gx2/Kconfig index 4515a71..deeffbb 100644 --- a/src/cpu/amd/model_gx2/Kconfig +++ b/src/cpu/amd/model_gx2/Kconfig @@ -24,7 +24,6 @@ if CPU_AMD_GX2 config CPU_SPECIFIC_OPTIONS def_bool y - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/model_lx/Kconfig index 742ef69..b2bf944 100644 --- a/src/cpu/amd/model_lx/Kconfig +++ b/src/cpu/amd/model_lx/Kconfig @@ -5,7 +5,6 @@ if CPU_AMD_LX config CPU_SPECIFIC_OPTIONS def_bool y - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index 7a353a3..4166754 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -6,7 +6,6 @@ if CPU_AMD_SOCKET_754 config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM config CPU_ADDR_BITS int diff --git a/src/cpu/amd/socket_939/Kconfig b/src/cpu/amd/socket_939/Kconfig index 4546297..ff36a84 100644 --- a/src/cpu/amd/socket_939/Kconfig +++ b/src/cpu/amd/socket_939/Kconfig @@ -1,5 +1,4 @@ config CPU_AMD_SOCKET_939 bool select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index 1dbf652..603aa03 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS def_bool y select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM config CPU_ADDR_BITS int diff --git a/src/cpu/amd/socket_AM2/Kconfig b/src/cpu/amd/socket_AM2/Kconfig index 6849154..3663061 100644 --- a/src/cpu/amd/socket_AM2/Kconfig +++ b/src/cpu/amd/socket_AM2/Kconfig @@ -4,7 +4,6 @@ config CPU_AMD_SOCKET_AM2 # Opteron K8 1G HT support select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig index c7cff14..9435a55 100644 --- a/src/cpu/amd/socket_AM2r2/Kconfig +++ b/src/cpu/amd/socket_AM2r2/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_AM2R2 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig index c718ead..2979cbe 100644 --- a/src/cpu/amd/socket_AM3/Kconfig +++ b/src/cpu/amd/socket_AM3/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_AM3 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig index 964a59f..7b8857f 100644 --- a/src/cpu/amd/socket_ASB2/Kconfig +++ b/src/cpu/amd/socket_ASB2/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_ASB2 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig index 7ffa374..70578c2 100644 --- a/src/cpu/amd/socket_C32/Kconfig +++ b/src/cpu/amd/socket_C32/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_C32 select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select PCI_IO_CFG_EXT - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig index 8514369..f32e690 100644 --- a/src/cpu/amd/socket_F/Kconfig +++ b/src/cpu/amd/socket_F/Kconfig @@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_F select K8_REV_F_SUPPORT select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig index 224059a..959fea5 100644 --- a/src/cpu/amd/socket_F_1207/Kconfig +++ b/src/cpu/amd/socket_F_1207/Kconfig @@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_F_1207 bool select CPU_AMD_MODEL_10XXX select PCI_IO_CFG_EXT - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 284c181..b96613c 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select K8_REV_F_SUPPORT select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX - select CACHE_AS_RAM config CPU_SOCKET_TYPE hex diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 2310d7d..55cb534 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -231,7 +231,7 @@ clear_fixed_var_mtrr_out: #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) -#if CONFIG_TINY_BOOTBLOCK +#if !CONFIG_BIG_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index da14db2..db658fa 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -102,7 +102,7 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK +#if !CONFIG_BIG_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 02de5ab..10ba812 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -102,7 +102,7 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK +#if !CONFIG_BIG_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 2f13d35..ce2718b 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -109,7 +109,7 @@ clear_mtrrs: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx -#if CONFIG_TINY_BOOTBLOCK +#if !CONFIG_BIG_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 45c94ac..ce43525 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -19,7 +19,6 @@ config CPU_INTEL_SLOT_1 bool - select CACHE_AS_RAM config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index f73c8a9..2269190 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_106CX select MMX select SSE - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig index 88541a8..a97d9c3 100644 --- a/src/cpu/intel/socket_FC_PGA370/Kconfig +++ b/src/cpu/intel/socket_FC_PGA370/Kconfig @@ -23,8 +23,6 @@ config CPU_INTEL_SOCKET_FC_PGA370 select CPU_INTEL_MODEL_68X select MMX select SSE - select CACHE_AS_RAM - select TINY_BOOTBLOCK config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index adfb5f3..6993e62 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -21,7 +21,6 @@ config CPU_INTEL_SOCKET_PGA370 bool select MMX select UDELAY_TSC - select CACHE_AS_RAM if CPU_INTEL_SOCKET_PGA370 diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig index d2ceabe..5576623 100644 --- a/src/cpu/intel/socket_mFCBGA479/Kconfig +++ b/src/cpu/intel/socket_mFCBGA479/Kconfig @@ -3,4 +3,3 @@ config CPU_INTEL_SOCKET_MFCBGA479 select CPU_INTEL_MODEL_6BX select MMX select SSE - select CACHE_AS_RAM diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 3f39303..566d482 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_CORE2 select MMX select SSE - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig index 4be39b5..8598eaf 100644 --- a/src/cpu/intel/socket_mPGA479M/Kconfig +++ b/src/cpu/intel/socket_mPGA479M/Kconfig @@ -6,4 +6,3 @@ config CPU_INTEL_SOCKET_MPGA479M select CPU_INTEL_MODEL_F2X select MMX select SSE - select CACHE_AS_RAM diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..80ae79f 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram.inc + diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 20b3220..04d5941 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -110,7 +110,7 @@ clear_fixed_var_mtrr_out: movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax wrmsr -#if CONFIG_TINY_BOOTBLOCK +#if !CONFIG_BIG_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig index 8e6f0e8..25aa43a 100644 --- a/src/cpu/via/model_c7/Kconfig +++ b/src/cpu/via/model_c7/Kconfig @@ -8,7 +8,6 @@ config CPU_SPECFIC_OPTIONS select UDELAY_TSC select MMX select SSE2 - select CACHE_AS_RAM config DCACHE_RAM_BASE hex diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index dcfcccd..2f31ac7 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -29,6 +29,8 @@ static void cache_lbmem(int type) enable_cache(); } +const int addr_det = 0; + /* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ @@ -52,8 +54,12 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) #if defined(CONFIG_XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. + * Determine address by calculating the XIP_ROM_SIZE sized area with + * XIP_ROM_SIZE alignment that contains the global variable defined above; */ - set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + unsigned long f = (unsigned long)&addr_det; + f = f & ~(CONFIG_XIP_ROM_SIZE - 1); + set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 44a2223..5413366 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -69,7 +69,7 @@ void x86_setup_fixed_mtrrs(void); #if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) -# if CONFIG_TINY_BOOTBLOCK +# if CONFIG_CACHE_AS_RAM extern unsigned long AUTO_XIP_ROM_BASE; # define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE # else diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig index 3b31ffb..1b5b62b 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig +++ b/src/mainboard/aaeon/pfm-540i_revb/Kconfig @@ -3,6 +3,7 @@ if BOARD_AAEON_PFM_540I_REVB config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 29c1c6b..7f1d136 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select HAVE_DEBUG_CAR select SET_FIDVID diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig index 7c87e28..715fe3b 100644 --- a/src/mainboard/advantech/pcm-5820/Kconfig +++ b/src/mainboard/advantech/pcm-5820/Kconfig @@ -21,11 +21,12 @@ if BOARD_ADVANTECH_PCM_5820 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977F - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig index 834e085..780b56e 100644 --- a/src/mainboard/amd/db800/Kconfig +++ b/src/mainboard/amd/db800/Kconfig @@ -3,6 +3,7 @@ if BOARD_AMD_DB800 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index 80bc621..4bb0d60 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -43,7 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA config AMD_AGESA diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig index b265eeb..84c2c33 100644 --- a/src/mainboard/amd/norwich/Kconfig +++ b/src/mainboard/amd/norwich/Kconfig @@ -3,6 +3,7 @@ if BOARD_AMD_NORWICH config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 72b7947..93b4554 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - select TINY_BOOTBLOCK select GFXUMA config AMD_AGESA diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index 0477f32..d87e182 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -21,6 +21,7 @@ if BOARD_AMD_RUMBA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 4c9d2a0..0fc857b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -24,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select LIFT_BSP_APIC_ID - select TINY_BOOTBLOCK select QRANK_DIMM_SUPPORT config MAINBOARD_DIR diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index 6da53a0..f368279 100755 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -43,7 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA config AMD_AGESA diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig index 846000c..8f871d0 100644 --- a/src/mainboard/artecgroup/dbe61/Kconfig +++ b/src/mainboard/artecgroup/dbe61/Kconfig @@ -3,6 +3,7 @@ if BOARD_ARTECGROUP_DBE61 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig index 5278369..b935ffe 100644 --- a/src/mainboard/asi/mb_5blgp/Kconfig +++ b/src/mainboard/asi/mb_5blgp/Kconfig @@ -21,11 +21,12 @@ if BOARD_ASI_MB_5BLGP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC87351 - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig index 5b3b5bd..6ba556a 100644 --- a/src/mainboard/asi/mb_5blmp/Kconfig +++ b/src/mainboard/asi/mb_5blmp/Kconfig @@ -21,11 +21,12 @@ if BOARD_ASI_MB_5BLMP config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC87351 - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 802b58f..8324fa4 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -41,7 +41,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - select TINY_BOOTBLOCK select GFXUMA config AMD_AGESA diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 05408ca..8ae0e89 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -3,6 +3,7 @@ if BOARD_ASUS_A8V_E_DELUXE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index 4975cfa..c0e8218 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -3,6 +3,7 @@ if BOARD_ASUS_A8V_E_SE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_SOCKET_939 select K8_HT_FREQ_1G_SUPPORT select NORTHBRIDGE_AMD_AMDK8 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 1d8f367..6434306 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select VGA - select TINY_BOOTBLOCK select HAVE_ACPI_RESUME select HAVE_MAINBOARD_RESOURCES select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 571b940..747c273 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_ITE_IT8712F select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO - select TINY_BOOTBLOCK select HAVE_ACPI_RESUME select HAVE_PIRQ_TABLE select PIRQ_ROUTE diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index 68ac160..16c708f 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -21,6 +21,7 @@ if BOARD_ASUS_MEW_AM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 4e46192..78228f7 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -21,6 +21,7 @@ if BOARD_ASUS_MEW_VM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 7aa90c8..aabd724 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select HAVE_DEBUG_CAR select SET_FIDVID diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig index dde2a36..70a67e8 100644 --- a/src/mainboard/axus/tc320/Kconfig +++ b/src/mainboard/axus/tc320/Kconfig @@ -21,11 +21,12 @@ if BOARD_AXUS_TC320 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig index dbb2cb8..597595c 100644 --- a/src/mainboard/bcom/winnet100/Kconfig +++ b/src/mainboard/bcom/winnet100/Kconfig @@ -21,11 +21,12 @@ if BOARD_BCOM_WINNET100 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/bcom/winnetp680/Kconfig b/src/mainboard/bcom/winnetp680/Kconfig index 78e014e..9ad5325 100644 --- a/src/mainboard/bcom/winnetp680/Kconfig +++ b/src/mainboard/bcom/winnetp680/Kconfig @@ -3,6 +3,7 @@ if BOARD_BCOM_WINNETP680 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig index 381c9f6..0a10f99 100644 --- a/src/mainboard/dell/s1850/Kconfig +++ b/src/mainboard/dell/s1850/Kconfig @@ -3,12 +3,13 @@ if BOARD_DELL_S1850 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC8374 - select ROMCC select HAVE_HARD_RESET select HAVE_OPTION_TABLE select BOARD_HAS_HARD_RESET diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index ec5acb1..4b2bcd2 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 - select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/digitallogic/msm586seg/Kconfig b/src/mainboard/digitallogic/msm586seg/Kconfig index d54037a..b0a61cf 100644 --- a/src/mainboard/digitallogic/msm586seg/Kconfig +++ b/src/mainboard/digitallogic/msm586seg/Kconfig @@ -3,11 +3,12 @@ if BOARD_DIGITALLOGIC_MSM586SEG config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_SC520 select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE select BOARD_ROMSIZE_KB_512 - select ROMCC config MAINBOARD_DIR string diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig index 444023b..4aa0807 100644 --- a/src/mainboard/digitallogic/msm800sev/Kconfig +++ b/src/mainboard/digitallogic/msm800sev/Kconfig @@ -3,6 +3,7 @@ if BOARD_DIGITALLOGIC_MSM800SEV config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/eaglelion/5bcm/Kconfig b/src/mainboard/eaglelion/5bcm/Kconfig index 65dd802..b3e013e 100644 --- a/src/mainboard/eaglelion/5bcm/Kconfig +++ b/src/mainboard/eaglelion/5bcm/Kconfig @@ -21,11 +21,12 @@ if BOARD_EAGLELION_5BCM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index 7d377f4..4830072 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -22,6 +22,7 @@ if BOARD_ECS_P6IWP_FE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/emulation/qemu-x86/Kconfig b/src/mainboard/emulation/qemu-x86/Kconfig index 9625c0a..466030b 100644 --- a/src/mainboard/emulation/qemu-x86/Kconfig +++ b/src/mainboard/emulation/qemu-x86/Kconfig @@ -3,12 +3,12 @@ if BOARD_EMULATION_QEMU_X86 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select SOUTHBRIDGE_INTEL_I82371EB - select ROMCC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 - select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 35a4be6..ec30859 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -40,7 +40,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_1024 select GFXUMA - select TINY_BOOTBLOCK select CHANNEL_XOR_RANDOMIZATION config MAINBOARD_DIR diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index e20420d..e3dbf6b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select AMDMCT - select TINY_BOOTBLOCK select QRANK_DIMM_SUPPORT config MAINBOARD_DIR diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index 5fab95a..122f40d 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -25,6 +25,7 @@ if BOARD_HP_E_VECTRA_P2706T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 3569e35..02ccfab 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_512 select GFXUMA - select TINY_BOOTBLOCK select CHANNEL_XOR_RANDOMIZATION config MAINBOARD_DIR diff --git a/src/mainboard/iei/juki-511p/Kconfig b/src/mainboard/iei/juki-511p/Kconfig index d948929..0b60dc8 100644 --- a/src/mainboard/iei/juki-511p/Kconfig +++ b/src/mainboard/iei/juki-511p/Kconfig @@ -21,11 +21,12 @@ if BOARD_IEI_JUKI_511P config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977F - select ROMCC select PIRQ_ROUTE select HAVE_PIRQ_TABLE select HAVE_OPTION_TABLE diff --git a/src/mainboard/iei/nova4899r/Kconfig b/src/mainboard/iei/nova4899r/Kconfig index 3cc5ddb..5e02b90 100644 --- a/src/mainboard/iei/nova4899r/Kconfig +++ b/src/mainboard/iei/nova4899r/Kconfig @@ -21,11 +21,12 @@ if BOARD_IEI_NOVA_4899R config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select HAVE_OPTION_TABLE diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig index e393609..4b1e2c4 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig +++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig @@ -3,6 +3,7 @@ if BOARD_IEI_PCISA_LX_800_R10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index ff8c638..2b0161c 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -38,7 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_512 select GFXUMA - select TINY_BOOTBLOCK select CHANNEL_XOR_RANDOMIZATION config MAINBOARD_DIR diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 00aa1ae..e9421ae 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -3,6 +3,7 @@ if BOARD_INTEL_EAGLEHEIGHTS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_BGA956 select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 494086e..2c05fdc 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -3,12 +3,13 @@ if BOARD_INTEL_JARRELL config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_PXHD select SOUTHBRIDGE_INTEL_I82801EX select SUPERIO_NSC_PC87427 - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c index 567d15c..7e4c7f9 100644 --- a/src/mainboard/intel/jarrell/power_reset_check.c +++ b/src/mainboard/intel/jarrell/power_reset_check.c @@ -1,12 +1,15 @@ static void power_down_reset_check(void) { +#if 0 uint8_t cmos; + /* FIXME */ cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; print_debug("Boot byte = "); print_debug_hex8(cmos); print_debug("\n"); if((cmos>2)&&(cmos&1)) full_reset(); +#endif } diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..9362b50 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -100,11 +100,17 @@ static void ich5_watchdog_on(void) unsigned long value, base; unsigned char byte; +#if 0 + /* FIXME */ /* check cmos options */ byte = cmos_read(RTC_BOOT_BYTE-1); if(!(byte & 1)) return; /* no boot watchdog */ byte = cmos_read(RTC_BOOT_BYTE); if(!(byte & 2)) return; /* fallback so ignore */ +#else + /* boot watchdog disabled */ + return; +#endif dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig index 76477b0..62e1748 100644 --- a/src/mainboard/intel/mtarvon/Kconfig +++ b/src/mainboard/intel/mtarvon/Kconfig @@ -3,6 +3,7 @@ if BOARD_INTEL_MTARVON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig index 5f7de08..6077235 100644 --- a/src/mainboard/intel/truxton/Kconfig +++ b/src/mainboard/intel/truxton/Kconfig @@ -3,12 +3,13 @@ if BOARD_INTEL_TRUXTON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_EP80579 select NORTHBRIDGE_INTEL_I3100 select SOUTHBRIDGE_INTEL_I3100 select SUPERIO_INTEL_I3100 select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_HARD_RESET select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig index 9163423..1eec4b9 100644 --- a/src/mainboard/intel/xe7501devkit/Kconfig +++ b/src/mainboard/intel/xe7501devkit/Kconfig @@ -3,12 +3,13 @@ if BOARD_INTEL_XE7501DEVKIT config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801CX select SUPERIO_SMSC_LPC47B272 - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_PIRQ_TABLE diff --git a/src/mainboard/jetway/j7f24/Kconfig b/src/mainboard/jetway/j7f24/Kconfig index fa17eba..f64b04a 100644 --- a/src/mainboard/jetway/j7f24/Kconfig +++ b/src/mainboard/jetway/j7f24/Kconfig @@ -4,6 +4,7 @@ if BOARD_JETWAY_J7F24 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index e242afd..01e4b2f 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_1024 select GFXUMA - select TINY_BOOTBLOCK select CHANNEL_XOR_RANDOMIZATION select OVERRIDE_CLOCK_DISABLE diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig index 136e181..52f5a72 100644 --- a/src/mainboard/lanner/em8510/Kconfig +++ b/src/mainboard/lanner/em8510/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 - select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index c17d843..6c2c195 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select TINY_BOOTBLOCK config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 3b39ed8..b3691a9 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -3,6 +3,7 @@ if BOARD_LENOVO_X60 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig index 4e8cee0..3c1e2f1 100644 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ b/src/mainboard/lippert/frontrunner/Kconfig @@ -3,6 +3,7 @@ if BOARD_LIPPERT_FRONTRUNNER config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig index 9b20aa0..ac7dfa0 100644 --- a/src/mainboard/lippert/hurricane-lx/Kconfig +++ b/src/mainboard/lippert/hurricane-lx/Kconfig @@ -3,6 +3,7 @@ if BOARD_LIPPERT_HURRICANE_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig index 7b45d36..ab5f912 100644 --- a/src/mainboard/lippert/literunner-lx/Kconfig +++ b/src/mainboard/lippert/literunner-lx/Kconfig @@ -3,6 +3,7 @@ if BOARD_LIPPERT_LITERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig index 4e29742..3a0a5fc 100644 --- a/src/mainboard/lippert/roadrunner-lx/Kconfig +++ b/src/mainboard/lippert/roadrunner-lx/Kconfig @@ -3,6 +3,7 @@ if BOARD_LIPPERT_ROADRUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig index f273d6c..a7c1e43 100644 --- a/src/mainboard/lippert/spacerunner-lx/Kconfig +++ b/src/mainboard/lippert/spacerunner-lx/Kconfig @@ -3,6 +3,7 @@ if BOARD_LIPPERT_SPACERUNNER_LX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index fac565e..91ebe98 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -21,6 +21,7 @@ if BOARD_MITAC_6513WU config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index 1d45464..f8e9283 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -21,6 +21,7 @@ if BOARD_MSI_MS_6178 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 948d320..71568d7 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select AMDMCT - select TINY_BOOTBLOCK select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index 55050c0..4100865 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -21,6 +21,7 @@ if BOARD_NEC_POWERMATE_2000 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_PGA370 select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 0a016a5..d18d02b 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -3,6 +3,7 @@ if BOARD_PCENGINES_ALIX1C config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig index 264f5d9..b5d0f1f 100644 --- a/src/mainboard/pcengines/alix2d/Kconfig +++ b/src/mainboard/pcengines/alix2d/Kconfig @@ -3,6 +3,7 @@ if BOARD_PCENGINES_ALIX2D config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index e2879fe..5a9901e 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA - select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 7dfcc7d..d40b5c9 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -3,6 +3,7 @@ if BOARD_RODA_RK886EX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM select SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 195bc5c..3583300 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO - select TINY_BOOTBLOCK select ENABLE_APIC_EXT_ID select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 22760d2..5df0bb4 100755 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -39,7 +39,6 @@ config BOARD_SPECIFIC_OPTIONS select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 - select TINY_BOOTBLOCK #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config AMD_AGESA diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 1d4f8e7..85d0fb0 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select AMDMCT select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO - select TINY_BOOTBLOCK select ENABLE_APIC_EXT_ID select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/supermicro/x6dai_g/Kconfig b/src/mainboard/supermicro/x6dai_g/Kconfig index bac1008..fc843af 100644 --- a/src/mainboard/supermicro/x6dai_g/Kconfig +++ b/src/mainboard/supermicro/x6dai_g/Kconfig @@ -3,11 +3,12 @@ if BOARD_SUPERMICRO_X6DAI_G config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7525 select SOUTHBRIDGE_INTEL_ESB6300 select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig index e8466be..6e52304 100644 --- a/src/mainboard/supermicro/x6dhe_g/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g/Kconfig @@ -3,12 +3,13 @@ if BOARD_SUPERMICRO_X6DHE_G config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_ESB6300 select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig index e9d4041..4c863a0 100644 --- a/src/mainboard/supermicro/x6dhe_g2/Kconfig +++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig @@ -3,12 +3,13 @@ if BOARD_SUPERMICRO_X6DHE_G2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC87427 - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig index a146e77..650f60f 100644 --- a/src/mainboard/supermicro/x6dhr_ig/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig @@ -3,12 +3,13 @@ if BOARD_SUPERMICRO_X6DHR_IG config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig index 6196e2a..26953d2 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig +++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig @@ -3,12 +3,13 @@ if BOARD_SUPERMICRO_X6DHR_IG2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7520 select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE diff --git a/src/mainboard/technologic/ts5300/Kconfig b/src/mainboard/technologic/ts5300/Kconfig index 8def16d..fa5af93 100644 --- a/src/mainboard/technologic/ts5300/Kconfig +++ b/src/mainboard/technologic/ts5300/Kconfig @@ -3,8 +3,9 @@ if BOARD_TECHNOLOGIC_TS5300 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_SC520 - select ROMCC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig index b3233d9..bb2ca11 100644 --- a/src/mainboard/televideo/tc7020/Kconfig +++ b/src/mainboard/televideo/tc7020/Kconfig @@ -21,11 +21,12 @@ if BOARD_TELEVIDEO_TC7020 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_AMD_GX1 select NORTHBRIDGE_AMD_GX1 select SOUTHBRIDGE_AMD_CS5530 select SUPERIO_NSC_PC97317 - select ROMCC select HAVE_PIRQ_TABLE select PIRQ_ROUTE select UDELAY_TSC diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index e4f76fc..d9ea787 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MAINBOARD_RESOURCES select HAVE_SMI_HANDLER select GFXUMA - select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index dd6c8dd..3a907ff 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -3,6 +3,7 @@ if BOARD_TRAVERSE_GEOS config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig index 4aafa3c..9073b5f 100644 --- a/src/mainboard/tyan/s2735/Kconfig +++ b/src/mainboard/tyan/s2735/Kconfig @@ -3,6 +3,7 @@ if BOARD_TYAN_S2735 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_INTEL_SOCKET_MPGA604 select NORTHBRIDGE_INTEL_E7501 select SOUTHBRIDGE_INTEL_I82870 @@ -13,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select UDELAY_TSC select HAVE_OPTION_TABLE - select CACHE_AS_RAM select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index d7d5114..ffe665d 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select AMDMCT - select TINY_BOOTBLOCK select MMCONF_SUPPORT_DEFAULT select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig index e7920e7..c9c34cc 100644 --- a/src/mainboard/via/epia-cn/Kconfig +++ b/src/mainboard/via/epia-cn/Kconfig @@ -3,6 +3,7 @@ if BOARD_VIA_EPIA_CN config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/via/epia-m/Kconfig b/src/mainboard/via/epia-m/Kconfig index bf7f13d..af7d553 100644 --- a/src/mainboard/via/epia-m/Kconfig +++ b/src/mainboard/via/epia-m/Kconfig @@ -3,6 +3,8 @@ if BOARD_VIA_EPIA_M config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_VIA_C3 select NORTHBRIDGE_VIA_VT8623 select SOUTHBRIDGE_VIA_VT8235 @@ -13,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select ROMCC config MAINBOARD_DIR string diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig index 4396cc3..5380c47 100644 --- a/src/mainboard/via/epia-m700/Kconfig +++ b/src/mainboard/via/epia-m700/Kconfig @@ -3,6 +3,7 @@ if BOARD_VIA_EPIA_M700 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_VIA_C7 select NORTHBRIDGE_VIA_VX800 select SUPERIO_WINBOND_W83697HF diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 4806753..19c129a 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -3,6 +3,8 @@ if BOARD_VIA_EPIA_N config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_VIA_C3 select NORTHBRIDGE_VIA_CN400 select SOUTHBRIDGE_VIA_VT8237R @@ -14,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EPIA_VT8237R_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 - select ROMCC config MAINBOARD_DIR string diff --git a/src/mainboard/via/epia/Kconfig b/src/mainboard/via/epia/Kconfig index 60ce4f5..5c19757 100644 --- a/src/mainboard/via/epia/Kconfig +++ b/src/mainboard/via/epia/Kconfig @@ -3,6 +3,8 @@ if BOARD_VIA_EPIA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK + select NO_CACHE_AS_RAM select CPU_VIA_C3 select NORTHBRIDGE_VIA_VT8601 select SOUTHBRIDGE_VIA_VT8231 @@ -10,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 - select ROMCC config MAINBOARD_DIR string diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig index 70aa8d7..cc7ee4a 100644 --- a/src/mainboard/via/pc2500e/Kconfig +++ b/src/mainboard/via/pc2500e/Kconfig @@ -3,6 +3,7 @@ if BOARD_VIA_PC2500E config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_VIA_C7 select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index 6c08007..c9a0105 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 - select TINY_BOOTBLOCK config MAINBOARD_DIR string diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig index 4f367f1..b075273 100644 --- a/src/mainboard/winent/pl6064/Kconfig +++ b/src/mainboard/winent/pl6064/Kconfig @@ -3,6 +3,7 @@ if BOARD_WINENT_PL6064 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_LX select NORTHBRIDGE_AMD_LX select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig index dff01f9..dd4ea96 100644 --- a/src/mainboard/wyse/s50/Kconfig +++ b/src/mainboard/wyse/s50/Kconfig @@ -21,6 +21,7 @@ if BOARD_WYSE_S50 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select USES_BIG_BOOTBLOCK select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 666c7d5..83fb8fc 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -20,7 +20,6 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC - select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 9b164b3..07028a0 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -21,7 +21,6 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC select HAVE_USBDEBUG - select TINY_BOOTBLOCK if SOUTHBRIDGE_AMD_SB600 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index b4cae56..98b8e2a 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -21,13 +21,11 @@ config SOUTHBRIDGE_AMD_SB700 bool select IOAPIC select HAVE_USBDEBUG - select TINY_BOOTBLOCK config SOUTHBRIDGE_AMD_SP5100 bool select IOAPIC select HAVE_USBDEBUG - select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 1afd242..67cb8ef 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -21,7 +21,6 @@ config SOUTHBRIDGE_AMD_SB800 bool select IOAPIC select HAVE_USBDEBUG - select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index dae9a63..d72afd8 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -1,7 +1,6 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool select HAVE_HARD_RESET - select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 3b56796..7e5109a 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB bool - select TINY_BOOTBLOCK select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/intel/i82801cx/early_smbus.c b/src/southbridge/intel/i82801cx/early_smbus.c index b62db80..2e31507 100644 --- a/src/southbridge/intel/i82801cx/early_smbus.c +++ b/src/southbridge/intel/i82801cx/early_smbus.c @@ -85,7 +85,6 @@ static int smbus_wait_until_done(void) static int smbus_read_byte(unsigned device, unsigned address) { - unsigned char global_control_register; unsigned char global_status_register; unsigned char byte; diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index 4b35306..ed2c6c4 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -19,7 +19,6 @@ config SOUTHBRIDGE_INTEL_SCH bool - select TINY_BOOTBLOCK select HAVE_USBDEBUG if SOUTHBRIDGE_INTEL_SCH diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 9ea1423..88ab7ff 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -3,7 +3,6 @@ config SOUTHBRIDGE_NVIDIA_CK804 select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC - select TINY_BOOTBLOCK if SOUTHBRIDGE_NVIDIA_CK804 diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index af6bb2b..adca4bd 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,7 +2,6 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool select HAVE_USBDEBUG select IOAPIC - select TINY_BOOTBLOCK if SOUTHBRIDGE_NVIDIA_MCP55 diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 867d08c..909a741 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -2,7 +2,6 @@ config SOUTHBRIDGE_SIS_SIS966 bool select IOAPIC select HAVE_USBDEBUG - select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT string

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Re: [coreboot] "No valid softstrap base found." hang?
by Kyösti Mälkki 26 Oct '11

26 Oct '11

On Wed, 2011-10-26 at 12:35 +0300, Alp Eren Köse wrote: > No one has an idea about the issue? I really need help on this, cause > I am stuck here. > I am not experienced on such stuff unfortunately:S > I would be grateful if someone could at least point some way. > Thanks in advance, > Alp > > No valid softstrap base found. In northbridge/intel/sch/raminit.c, detect_softstrap_base() reg32 = sch_port_access_read(4, 0x71, 2); reg32 &= 0x700; reg32 = reg32 >> 7; Probably should read: reg32 &= 0x700; reg32 = reg32 >> 8; or (not so likely) reg32 &= 0x380; reg32 = reg32 >> 7; Otherwise it's pointless to test for 7 and 5. Makes me wonder how it has ever worked for anyone. KM

2 1

Re: [coreboot] "No valid softstrap base found." hang?
by Alp Eren Köse 26 Oct '11

26 Oct '11

No one has an idea about the issue? I really need help on this, cause I am stuck here. I am not experienced on such stuff unfortunately:S I would be grateful if someone could at least point some way. Thanks in advance, Alp 2011/10/24 Alp Eren Köse <alperenkose(a)buyutech.com.tr> > Hi all, > > Thank you very much for your help this far, I have managed to get serial > output of my board finally now:) > > But now the system dies just after I start it with the following messages: > ---------- serial output ----------- > > US15W Chipset > > Unknown (07)Setting up ACPI PM1 block Setting up ACPI P block done. > > Setting up RAM controller. > > No valid softstrap base found. > ----------------------------------------- > > I don't know why and how, but somehow the "base_addr" variable in the > "static u32 detect_softstrap_base(void)" function > in file "src/northbridge/intel/sch/raminit.c" gets 0, because of something > about the reg32 variable not being any of (4,5,6 or 7). > > Does anyone have any idea for the cause of the problem and solution? > And by the way what does the softstrap mean, what is it for? > > Thanks in advance, > Alp >

1 0

Re: [coreboot] Status of SeaBIOS VGA bios.
by Kevin O'Connor 26 Oct '11

26 Oct '11

On Wed, Oct 26, 2011 at 12:16:32AM +0100, Julian Pidancet wrote: > Hi, > > I stumbled across the vgasrc directory in the SeaBIOS git tree which > seem to contain the source of a VGA Bios. I havn't found any related > documentation nor announcements regarding this, and there is no > Makefiles or scripts to build it. That's why I'm enquiring here about > the status of this project. You can build the vgabios by running: make out/vgabios.bin There was a brief note on the vga code some time back: http://www.coreboot.org/pipermail/coreboot/2009-May/047775.html > I've got several questions: > - What is the general status of this project ? I started converting the VGA bios from the "lgpl vga bios" project ( http://savannah.nongnu.org/projects/vgabios/ ) a couple of years ago. I converted the base code, but did not have time to convert the "VBE" or the "cirrus" code. There was also an effort a few years back to get the code running on real hardware that had some success. > - Is this code intended to be executed in a 32bit environment by > transitionning from 16bit to 32bit mode for each BIOS call as SeaBIOS > already does ? The current seabios vgabios code runs exclusively in 16bit mode. (Note, SeaBIOS also has some calls handled entirely in 16bit mode as well.) > - Is this code able to run independantly from SeaBIOS ? It should - but I've never tested it that way. > - How can I build the sources ? make out/vgabios.bin > I am currently working on a emulated graphic adapter for Xen and I > would like to implement a VBE driver for it. This VGA BIOS seems to be > a good base for that kind of work. Would that be possible ? It should work. Ideally, someone would complete the port of the "lgpl vgabios". This involves translating the remaining 16bit assembler to C code and then doing lots of testing on the result. -Kevin

3 2

Patch set updated for coreboot: 99df168 w83627hf: add method to retrieve wake event source register to ASL include
by Christoph Grenz 25 Oct '11

25 Oct '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/297 -gerrit commit 99df168f101637175665329fdaec382f3db12a08 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Wed Oct 19 02:25:08 2011 +0200 w83627hf: add method to retrieve wake event source register to ASL include Add a method WAKS to devtree.asl which returns the wake-up source register to simplify retrieving the wake source e.g. in \_WAK. Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/devtree.asl | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl index cbc132d..aa18841 100644 --- a/src/superio/winbond/w83627hf/devtree.asl +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -1503,5 +1503,22 @@ Scope (\_SB) } } #endif + + /* Returns the wake source register. + It is cleared after reading. + Bit 0: Keyboard wake-up event + Bit 1: Mouse wake-up event + Bit 2: Power button event + Bit 3: CIR wake-up event + Bit 4: Power loss event + Bit 5: VSB power loss status + */ + Method (WAKS) { + ENCM () + Store (0x0A, LDN) + Store (CRE3, Local0) + EXCM () + Return (Local0) + } } }

1 0

Status of SeaBIOS VGA bios.
by Julian Pidancet 25 Oct '11

25 Oct '11

Hi, I stumbled across the vgasrc directory in the SeaBIOS git tree which seem to contain the source of a VGA Bios. I havn't found any related documentation nor announcements regarding this, and there is no Makefiles or scripts to build it. That's why I'm enquiring here about the status of this project. I've got several questions: - What is the general status of this project ? - Is this code intended to be executed in a 32bit environment by transitionning from 16bit to 32bit mode for each BIOS call as SeaBIOS already does ? - Is this code able to run independantly from SeaBIOS ? - How can I build the sources ? I am currently working on a emulated graphic adapter for Xen and I would like to implement a VBE driver for it. This VGA BIOS seems to be a good base for that kind of work. Would that be possible ? -- julian

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coreboot October 2011