coreboot October 2011

coreboot@coreboot.org

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501 discussions

New patch to review for coreboot: d150798 Prevent multiple inclusions of cpu/x86/name
by Stefan Reinauer 25 Oct '11

25 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/338 -gerrit commit d1507987b60529ea42105ed295f872c06a83ecf7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 14:32:21 2011 -0700 Prevent multiple inclusions of cpu/x86/name This removes 54 make warnings from the build Change-Id: I94ac9875526febe2f95334c1c3971641c1d27f8f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/name/Makefile.inc | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/name/Makefile.inc b/src/cpu/x86/name/Makefile.inc index 1528ed7..d65404b 100644 --- a/src/cpu/x86/name/Makefile.inc +++ b/src/cpu/x86/name/Makefile.inc @@ -17,5 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ifneq ($(CPU_X86_NAME_INCLUDED),y) +CPU_X86_NAME_INCLUDED:=y + ramstage-y += name.c +endif

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New patch to review for coreboot: 4fa81f7 Fix libpayload speaker driver
by Stefan Reinauer 25 Oct '11

25 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/337 -gerrit commit 4fa81f7cbcce03bb8679a69f073cd9317fde4412 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 14:15:57 2011 -0700 Fix libpayload speaker driver The frequency for the PC speaker has to be specified as 1193180 / frequency according to http://wiki.osdev.org/PC_Speaker Change-Id: Iaca9d45807e080efe834611e719b350680b5fb90 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/drivers/speaker.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/speaker.c b/payloads/libpayload/drivers/speaker.c index 3b3a750..3a561bc 100644 --- a/payloads/libpayload/drivers/speaker.c +++ b/payloads/libpayload/drivers/speaker.c @@ -60,13 +60,15 @@ */ void speaker_enable(u16 freq) { + u16 reg16 = 1193180 / freq; + /* Select counter 2. Read/write LSB first, then MSB. Use mode 3 (square wave generator). Use a 16bit binary counter. */ outb(0xb6, I82C54_CONTROL_WORD_REGISTER); /* Set the desired tone frequency. */ - outb((u8)(freq & 0x00ff), I82C54_COUNTER2); /* LSB. */ - outb((u8)(freq >> 8), I82C54_COUNTER2); /* MSB. */ + outb((u8)(reg16 & 0x00ff), I82C54_COUNTER2); /* LSB. */ + outb((u8)(reg16 >> 8), I82C54_COUNTER2); /* MSB. */ /* Enable the PC speaker (set bits 0 and 1). */ outb(inb(PC_SPEAKER_PORT) | 0x03, PC_SPEAKER_PORT);

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New patch to review for coreboot: 236cdde Add -Werror to xcompile's testcc
by Stefan Reinauer 25 Oct '11

25 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/336 -gerrit commit 236cdde502d46c08e1867ef4a235f4f38ee9f747 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 12:28:40 2011 -0700 Add -Werror to xcompile's testcc If -Werror is not specified, tests for certain compiler flags will emit a warning, which makes the build break since we compile with -Werror. Change-Id: I7be56530ff9f94e5500bad226c83e47145a808d7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/xcompile/xcompile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 9a0a295..4926394 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -21,7 +21,7 @@ testcc() { echo "_start(void) {}" > .$$$$.c - $1 -nostdlib $2 .$$$$.c -o .$$$$.tmp 2>/dev/null >/dev/null + $1 -nostdlib -Werror $2 .$$$$.c -o .$$$$.tmp 2>/dev/null >/dev/null ret=$? rm -f .$$$$.c .$$$$.tmp return $ret

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Patch merged into coreboot/master: a8894c6 X60: enable Cx power saving modes
by gerrit＠coreboot.org 25 Oct '11

25 Oct '11

the following patch was just integrated into master: commit a8894c6ff29a9b7be5b6e90065bd7b404c211e18 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 16:57:50 2011 +0200 X60: enable Cx power saving modes Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Oct 25 21:03:02 2011, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Oct 25 21:03:30 2011, giving +2 See http://review.coreboot.org/331 for details. -gerrit

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Patch set updated for coreboot: a8894c6 X60: enable Cx power saving modes
by Sven Schnelle 25 Oct '11

25 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/331 -gerrit commit a8894c6ff29a9b7be5b6e90065bd7b404c211e18 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 16:57:50 2011 +0200 X60: enable Cx power saving modes Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/devicetree.cb | 18 ++++++++++++++++++ src/mainboard/lenovo/x60/mainboard.c | 13 +++++++++++++ 3 files changed, 32 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 3b39ed8..69f83a8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 55e0b2d..000f9c7 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -60,6 +60,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" + + register "c4onc3_enable" = "1" device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 end @@ -174,6 +176,22 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end + end end chip southbridge/ricoh/rl5c476 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index e59b2e4..5bc1dca 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -36,6 +36,19 @@ #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include "dock.h" +#include <arch/x86/include/arch/acpigen.h> + +static struct cst_entry cst_entries[] = { + { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +}; + +int get_cst_entries(struct cst_entry **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} static void mainboard_enable(device_t dev) {

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Patch merged into coreboot/master: 8ae1d47 T60: add _CST table
by gerrit＠coreboot.org 25 Oct '11

25 Oct '11

the following patch was just integrated into master: commit 8ae1d4744e20ee90d4118f20ba5ee2a93bf0b6d1 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 22 13:41:28 2011 +0200 T60: add _CST table Used by power management code to enable Cx powersaving modes. Change-Id: I02c6b10762245bc48f21a341286236e203421de0 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Oct 25 20:38:29 2011, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Oct 25 20:38:43 2011, giving +2 See http://review.coreboot.org/322 for details. -gerrit

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Patch set updated for coreboot: 8ae1d47 T60: add _CST table
by Sven Schnelle 25 Oct '11

25 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/322 -gerrit commit 8ae1d4744e20ee90d4118f20ba5ee2a93bf0b6d1 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 22 13:41:28 2011 +0200 T60: add _CST table Used by power management code to enable Cx powersaving modes. Change-Id: I02c6b10762245bc48f21a341286236e203421de0 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/mainboard.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index d4f260d..19ac221 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -35,6 +35,19 @@ #include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> + +static struct cst_entry cst_entries[] = { + { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +}; + +int get_cst_entries(struct cst_entry **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} static void mainboard_enable(device_t dev) {

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Patch merged into coreboot/master: 00ed3ec T60: enable C4onC3 mode
by gerrit＠coreboot.org 25 Oct '11

25 Oct '11

the following patch was just integrated into master: commit 00ed3ecace4dfd46b5674580f943230b691e64e2 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 16:36:22 2011 +0200 T60: enable C4onC3 mode It is safe to enable this setting on these Boards. Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Oct 25 09:04:27 2011, giving +2 Build-Tested: build bot (Jenkins) at Sun Oct 23 23:52:58 2011, giving +1 See http://review.coreboot.org/330 for details. -gerrit

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Patch merged into coreboot/master: d53e56b T60: use ICS954309 clock driver
by gerrit＠coreboot.org 25 Oct '11

25 Oct '11

the following patch was just integrated into master: commit d53e56b8e5a8e02c88a02dc4ec74472e8e97dfd7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Oct 25 20:13:01 2011, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Oct 25 20:13:16 2011, giving +2 See http://review.coreboot.org/328 for details. -gerrit

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Patch set updated for coreboot: d53e56b T60: use ICS954309 clock driver
by Sven Schnelle 25 Oct '11

25 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/328 -gerrit commit d53e56b8e5a8e02c88a02dc4ec74472e8e97dfd7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/t60/devicetree.cb | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index c17d843..9141fc9 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_TI_PCI1X2X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 27ce46c..4d0476f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -197,6 +197,21 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end end end end

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coreboot October 2011