coreboot October 2011

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New patch to review for coreboot: 8d6fdfc Add support for AMD IMC controller.
by Rudolf Marek 27 Oct '11

27 Oct '11

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/343 -gerrit commit 8d6fdfc9686dcce013225a9e15eec32c78a73df7 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Thu Oct 27 20:42:11 2011 +0200 Add support for AMD IMC controller. This patch adds support to dump SIO like interface of AMD Embedded Controller in the SB7xx and SB8xxx southbridges. Parts of the register interface are documented in SBxxx RRG BDG. Change-Id: Ib2ccaa3dfe33cfa8e7cba19d8ab0798286ad2f92 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- util/superiotool/Makefile | 2 +- util/superiotool/amd.c | 135 ++++++++++++++++++++++++++++++++++++++++ util/superiotool/superiotool.h | 7 ++ 3 files changed, 143 insertions(+), 1 deletions(-) diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 6f3cfa3..5cc7650 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -57,7 +57,7 @@ CONFIG_PCI = yes ifeq ($(CONFIG_PCI), yes) CFLAGS += -DPCI_SUPPORT LIBS += -lpci -OBJS += pci.o via.o +OBJS += pci.o via.o amd.o endif all: $(PROGRAM) diff --git a/util/superiotool/amd.c b/util/superiotool/amd.c new file mode 100644 index 0000000..1c03523 --- /dev/null +++ b/util/superiotool/amd.c @@ -0,0 +1,135 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2011 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 +#define DEVICE_REV_REG 0x21 + +static const struct superio_registers reg_table[] = { + {0xb7, "SB7xx", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a, + 0x2b,0x2c,0x2e, 0x2f, EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x3, "EC channel 0", + {0x30,0x60,0x61, EOT}, + {NANA,NANA,NANA,EOT}}, + {0x5, "Irda", + {0x30,0x60,0x61,0x70, EOT}, + {NANA,NANA,NANA,NANA,EOT}}, + {0x7, "Keyboard Controller", + {0x30, EOT}, + {NANA,EOT}}, + {0x9, "Mailbox", + {0x30,0x60,0x61, EOT}, + {NANA,NANA,NANA,EOT}}, + {EOT}}}, + {0xb8, "SB8xx", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a, + 0x2b,0x2c,0x2e, 0x2f, EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x3, "EC channel 0", + {0x30,0x60,0x61, EOT}, + {NANA,NANA,NANA,EOT}}, + {0x5, "Irda", + {0x30,0x60,0x61,0x70, EOT}, + {NANA,NANA,NANA,NANA,EOT}}, + {0x7, "Keyboard Controller", + {0x30, EOT}, + {NANA,EOT}}, + {0x9, "Mailbox", + {0x30,0x60,0x61, EOT}, + {NANA,NANA,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + +/* same as serverengines */ +static void enter_conf_mode_ec(uint16_t port) +{ + OUTB(0x5a, port); +} + +static void exit_conf_mode_ec(uint16_t port) +{ + OUTB(0xa5, port); +} + +uint16_t detect_ec(void) +{ + uint16_t ec_port; + struct pci_dev *dev; + + dev = pci_dev_find(0x1002, 0x439d); + + if (!dev) { + return 0; + } + + /* is EC disabled ? */ + if (!(pci_read_byte(dev, 0x40) & (1 << 7))) + return 0; + + ec_port = pci_read_word(dev, 0xa4); + + if (!(ec_port & 0x1)) + return 0; + + ec_port &= ~0x1; + + return ec_port; +} + +void probe_idregs_amd(uint16_t port) +{ + uint8_t rev, devid; + + probing_for("AMD EC", "", port); + + if (!(port = detect_ec())) + return; + + enter_conf_mode_ec(port); + + devid = regval(port, DEVICE_ID_REG); + rev = regval(port, DEVICE_REV_REG); + + if (superio_unknown(reg_table, devid)) { + if (verbose) + printf(NOTFOUND "id=0x%02x, rev=0x%02x\n", devid, rev); + exit_conf_mode_ec(port); + return; + } + + printf("Found AMD EC %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, devid), devid, rev, port); + chip_found = 1; + + dump_superio("AMD EC", reg_table, port, devid, LDN_SEL); + + exit_conf_mode_ec(port); +} + +void print_amd_chips(void) +{ + print_vendor_chips("AMD EC", reg_table); +} diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index c5affec..f705a58 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -182,6 +182,10 @@ void print_vendor_chips(const char *vendor, void probe_idregs_ali(uint16_t port); void print_ali_chips(void); +/* amd.c */ +void probe_idregs_amd(uint16_t port); +void print_amd_chips(void); + /* serverengines.c */ void probe_idregs_serverengines(uint16_t port); void print_serverengines_chips(void); @@ -235,6 +239,8 @@ static const struct { {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, #ifdef PCI_SUPPORT {probe_idregs_via, {0x3f0, EOT}}, + /* in fact read the BASE from HW */ + {probe_idregs_amd, {0xaa, EOT}}, #endif {probe_idregs_serverengines, {0x2e, EOT}}, }; @@ -252,6 +258,7 @@ static const struct { {print_winbond_chips}, #ifdef PCI_SUPPORT {print_via_chips}, + {print_amd_chips}, #endif {print_serverengines_chips}, };

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Patch merged into coreboot/master: dc8b8b6 Added smbus block read/write for amd8111
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit dc8b8b6cde6c1826bd55f56ebdde46b05b5097e9 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Fri Oct 14 02:16:48 2011 +0200 Added smbus block read/write for amd8111 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc Build-Tested: build bot (Jenkins) at Thu Oct 27 12:59:01 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Oct 27 18:28:49 2011, giving +2 See http://review.coreboot.org/281 for details. -gerrit

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Patch merged into coreboot/master: faa83fd Move linux 2.6.11 workaround to generic code
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit faa83fd3074371696f40629a174dad2e883a7553 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Oct 14 23:02:57 2011 +0200 Move linux 2.6.11 workaround to generic code Linux 2.6.11 seems to require a certain order in CPUs listed in mptable, so enforce it. This was only done on arima/hdama, but now is generic. Unfortunately this is somewhat slow. Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Oct 15 03:15:08 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Oct 27 19:09:28 2011, giving +2 See http://review.coreboot.org/280 for details. -gerrit

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New patch to review for coreboot: 269d109 Fix checksum calculation both in romstage and ramstage.
by Stefan Reinauer 27 Oct '11

27 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/342 -gerrit commit 269d1090d86f65b4fe674ee28142b4cdaa1b088f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 27 18:42:53 2011 +0200 Fix checksum calculation both in romstage and ramstage. The earlier fix for CMOS checksums only fixed the function rtc_set_checksum, which would fix the checksum, but then coreboot would no longer honor the settings because it assumed the checksum is wrong after this. This change fixes the remaining functions. Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/mc146818rtc.c | 6 +++--- src/pc80/mc146818rtc_early.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c index 034957a..99d670d 100644 --- a/src/pc80/mc146818rtc.c +++ b/src/pc80/mc146818rtc.c @@ -1,3 +1,4 @@ +#include <stdint.h> #include <console/console.h> #include <pc80/mc146818rtc.h> #include <boot/coreboot_tables.h> @@ -80,12 +81,11 @@ static int rtc_checksum_valid(int range_start, int range_end, int cks_loc) { int i; - unsigned sum, old_sum; + u16 sum, old_sum; sum = 0; for(i = range_start; i <= range_end; i++) { sum += cmos_read(i); } - sum = (~sum)&0x0ffff; old_sum = ((cmos_read(cks_loc)<<8) | cmos_read(cks_loc+1))&0x0ffff; return sum == old_sum; } @@ -93,7 +93,7 @@ static int rtc_checksum_valid(int range_start, int range_end, int cks_loc) static void rtc_set_checksum(int range_start, int range_end, int cks_loc) { int i; - unsigned sum; + u16 sum; sum = 0; for(i = range_start; i <= range_end; i++) { sum += cmos_read(i); diff --git a/src/pc80/mc146818rtc_early.c b/src/pc80/mc146818rtc_early.c index abddf87..0652f27 100644 --- a/src/pc80/mc146818rtc_early.c +++ b/src/pc80/mc146818rtc_early.c @@ -1,3 +1,4 @@ +#include <stdint.h> #include <pc80/mc146818rtc.h> #include <fallback.h> #if CONFIG_USE_OPTION_TABLE @@ -23,13 +24,12 @@ static int cmos_chksum_valid(void) { #if CONFIG_USE_OPTION_TABLE unsigned char addr; - unsigned long sum, old_sum; + u16 sum, old_sum; sum = 0; - /* Comput the cmos checksum */ + /* Compute the cmos checksum */ for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { sum += cmos_read(addr); } - sum = (sum & 0xffff) ^ 0xffff; /* Read the stored checksum */ old_sum = cmos_read(LB_CKS_LOC) << 8;

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Patch merged into coreboot/master: 64ee1fc X60/T60: enable AHCI mode
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit 64ee1fcb2f421819882b5cc2cd5d1f19ef284c33 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Oct 27 13:10:14 2011 +0200 X60/T60: enable AHCI mode Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61 Build-Tested: build bot (Jenkins) at Thu Oct 27 13:29:16 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Oct 27 18:27:23 2011, giving +2 See http://review.coreboot.org/341 for details. -gerrit

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Patch merged into coreboot/master: 1cdccab i82801gx: Fix port status in AHCI mode
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit 1cdccab188602150e7deec78bea8339f733ae68d Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Oct 27 13:05:40 2011 +0200 i82801gx: Fix port status in AHCI mode The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Thu Oct 27 13:19:40 2011, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Oct 27 18:27:07 2011, giving +2 See http://review.coreboot.org/340 for details. -gerrit

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New patch to review for coreboot: 64ee1fc X60/T60: enable AHCI mode
by Sven Schnelle 27 Oct '11

27 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/341 -gerrit commit 64ee1fcb2f421819882b5cc2cd5d1f19ef284c33 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Oct 27 13:10:14 2011 +0200 X60/T60: enable AHCI mode Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61 --- src/mainboard/lenovo/t60/devicetree.cb | 3 ++- src/mainboard/lenovo/x60/devicetree.cb | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index dba3fdd..f8ba137 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -63,7 +63,8 @@ chip northbridge/intel/i945 register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 000f9c7..2f0a179 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -56,7 +56,8 @@ chip northbridge/intel/i945 register "gpi12_routing" = "1" register "gpi8_routing" = "2" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000"

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New patch to review for coreboot: 1cdccab i82801gx: Fix port status in AHCI mode
by Sven Schnelle 27 Oct '11

27 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/340 -gerrit commit 1cdccab188602150e7deec78bea8339f733ae68d Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Oct 27 13:05:40 2011 +0200 i82801gx: Fix port status in AHCI mode The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/chip.h | 1 + src/southbridge/intel/i82801gx/sata.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index b775d39..cc17539 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,6 +68,7 @@ struct southbridge_intel_i82801gx_config { uint32_t ide_enable_primary; uint32_t ide_enable_secondary; uint32_t sata_ahci; + uint32_t sata_ports_implemented; int c4onc3_enable:1; }; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index c390848..0e7a1a7 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -30,6 +30,8 @@ static void sata_init(struct device *dev) { u32 reg32; u16 reg16; + u32 *ahci_bar; + /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -106,9 +108,14 @@ static void sata_init(struct device *dev) /* Set Sata Controller Mode. */ pci_write_config8(dev, 0x90, 0x40); // 40=AHCI - /* Port 0 & 1 enable */ + /* In ACHI mode, bit[3:0] must always be set + * (Port status is controlled through AHCI BAR) + */ pci_write_config8(dev, 0x92, 0x0f); + ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); + ahci_bar[3] = config->sata_ports_implemented; + /* SATA Initialization register */ pci_write_config32(dev, 0x94, 0x1a000180); } else {

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Patch set updated for coreboot: dc8b8b6 Added smbus block read/write for amd8111
by Oskar Enoksson 27 Oct '11

27 Oct '11

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/281 -gerrit commit dc8b8b6cde6c1826bd55f56ebdde46b05b5097e9 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Fri Oct 14 02:16:48 2011 +0200 Added smbus block read/write for amd8111 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc --- src/southbridge/amd/amd8111/acpi.c | 25 +++++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 103 +++++++++++++++++++++++++++ src/southbridge/amd/amd8111/early_smbus.c | 9 +++ 3 files changed, 137 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 2ad54b7..d5b1c18 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -66,6 +66,29 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) return do_smbus_write_byte(res->base, device, address, val); } +static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 bytes, u8 *buffer) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_block_read(res->base, device, cmd, bytes, buffer); +} + +static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_block_write(res->base, device, cmd, bytes, buffer); +} + + #if CONFIG_GENERATE_ACPI_TABLES == 1 unsigned pm_base; #endif @@ -191,6 +214,8 @@ static struct smbus_bus_operations lops_smbus_bus = { .send_byte = lsmbus_send_byte, .read_byte = lsmbus_read_byte, .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write= lsmbus_block_write, }; static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index fe9b3bf..6661e02 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -222,3 +222,106 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned return 0; } +static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, u8 *buf) +{ + unsigned global_status_register; + unsigned i; + u8 msglen; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a block data read */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* clear the length word...*/ + outw(0, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + /* read results of transaction */ + msglen = inw(smbus_io_base + SMBHSTDAT) & 0x3f; + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + + /* read data block */ + for(i=0; i<msglen && i<bytes; i++) { + buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; + } + /* empty fifo */ + while(bytes++<msglen) { + inw(smbus_io_base + SMBHSTFIFO); + } + + return i; +} + +static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + unsigned global_status_register; + unsigned i; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a block data write */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* set the length word...*/ + outw(bytes, smbus_io_base + SMBHSTDAT); + + /* set the data block */ + for(i=0; i<bytes; i++) { + outw(buf[i], smbus_io_base + SMBHSTFIFO); + } + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return 0; +} + + diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index e6d7084..e236286 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -46,3 +46,12 @@ static inline int smbus_write_byte(unsigned device, unsigned address, unsigned c return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } +static inline int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf) +{ + return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + +static inline int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); +}

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Patch merged into coreboot/master: 236cdde Add -Werror to xcompile's testcc
by gerrit＠coreboot.org 27 Oct '11

27 Oct '11

the following patch was just integrated into master: commit 236cdde502d46c08e1867ef4a235f4f38ee9f747 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 12:28:40 2011 -0700 Add -Werror to xcompile's testcc If -Werror is not specified, tests for certain compiler flags will emit a warning, which makes the build break since we compile with -Werror. Change-Id: I7be56530ff9f94e5500bad226c83e47145a808d7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Oct 27 10:50:38 2011, giving +2 See http://review.coreboot.org/336 for details. -gerrit

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coreboot October 2011