coreboot August 2010

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[commit] r5716 - trunk/util/getpir
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 13:32:21 2010 New Revision: 5716 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5716 Log: image parsing for getpir when adding for example build/coreboot_ram as parameter it looks in the file for the PIRQ table prints it to stdout and shows if the checksum is correct. getpir works as before without any commandline parameters. This is very handy for developing a PIRQ table. Signed-off-by: Marc Bertens <mbertens(a)xs4all.nl> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/getpir/getpir.c Modified: trunk/util/getpir/getpir.c ============================================================================== --- trunk/util/getpir/getpir.c Tue Aug 17 13:22:40 2010 (r5715) +++ trunk/util/getpir/getpir.c Tue Aug 17 13:32:21 2010 (r5716) @@ -3,6 +3,8 @@ * Aug 26 2001 , Nikolai Vladychevski, <niko(a)isl.net.mx> * 2007.04.09 Jeremy Jackson <jerj(a)coplanar.net> * updated for amd64 and general 64 bit portability + * 2010.04.24 Marc Bertens <mbertens(a)xs4all.nl> + * Added functionality to read a image file for checking the checksum of the PIR */ #include <stdio.h> @@ -24,27 +26,69 @@ # define MEM_DEV "/dev/mem" #endif -static struct irq_routing_table *probe_table(int fd_mem) +/** + * The probe_table() is now called with the pointer to the memory, + * this is to handle both the assessing memory and a file. + * + * This function now dumps the table found to the stdout, with + * descriptions, it is special handy when building a PIRQ table + * for a board to check the checksum. + */ +static struct irq_routing_table *probe_table(char* ptr) { - char *ptr, signature[] = "$PIR"; - struct irq_routing_table *rt; + /** + * Signature to search for $PIR<2-byte-version> + * + * this is to be sure that we find the correct table. + */ + char signature[] = "$PIR\x00\x01"; + /** cast the pointer */ + struct irq_routing_table *rt = (struct irq_routing_table *)ptr; int size = 16; - - ptr = mmap(0, 0x10000, PROT_READ, MAP_SHARED, - fd_mem, (off_t) 0xf0000); - - if (ptr == MAP_FAILED) { - perror("Mapping system memory failed: "); - return NULL; - } - + int checksum_result; do { - rt = (struct irq_routing_table *) memmem(ptr + size, 16, signature, 4); + /** find the PIRQ table */ + rt = (struct irq_routing_table *) memmem(ptr + size, 16, signature, 6); if (rt != NULL) { - printf("Found PCI IRQ routing table signature at %p.\n", - (void *) ((char *) rt - ptr + 0xf0000)); - printf("Validating... "); - if (!calc_checksum(rt)) { + /** found the table */ + int i, ts = (rt->size - 32) / 16; + struct irq_info *se_arr; + se_arr = (struct irq_info *) ((char *) rt + 32); + /** Dump the table information to the stdout */ + printf("Found PCI IRQ routing table signature at %p.\n", (void *) ((char *) rt - ptr + 0xf0000)); + printf("SIGNATURE = %s\n", (char*)&rt->signature); + printf("VERSION = %04x\n", rt->version); + printf("SIZE = %i\n", rt->size); + printf("MAX_DEVICES_ON_BUS = 32 + 16 * %d\n", ts); + printf("INT_ROUTER_BUS = 0x%02x\n", rt->rtr_bus); + printf("INT_ROUTER DEVICE = (0x%02x << 3) | 0x%01x\n", rt->rtr_devfn >> 3, rt->rtr_devfn & 7); + printf("IRQ_DEVOTED_TO_PCI = %#x\n", rt->exclusive_irqs); + printf("VENDOR = %#x\n", rt->rtr_vendor); + printf("DEVICE = %#x\n", rt->rtr_device); + printf("MINIPORT = %#x\n", rt->miniport_data); + printf("CHECKSUM = %#x\n", rt->checksum); + printf("\tbus , dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu\n"); + for (i = 0; i < ts; i++) { + printf("\t0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", + (se_arr+i)->bus, (se_arr+i)->devfn >> 3, + (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, + (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link, + (se_arr+i)->irq[1].bitmap, (se_arr+i)->irq[2].link, + (se_arr+i)->irq[2].bitmap, (se_arr+i)->irq[3].link, + (se_arr+i)->irq[3].bitmap, (se_arr+i)->slot, + (se_arr+i)->rfu); + } + /** A table should not be over 0x400 bytes */ + if (rt->size > 0x400) { + return NULL; + } + printf("Validating...\n"); + /** Calculate the checksum value */ + checksum_result = calc_checksum(rt); + /** Show the calculatedchecksum value */ + printf("CHECKSUM = %#x\n", 0x100-((checksum_result - rt->checksum) & 0xFF)); + /** and the result of the calculation */ + if (!checksum_result) { printf("checksum is ok.\n"); break; } else { @@ -53,41 +97,93 @@ } size += 16; } while (size < 0xFFFF); - if (size >= 0xFFFF) { + /** When the functions comes here there is no PIRQ table found. */ printf("No PCI IRQ routing table signature found.\n"); - munmap(ptr, 0x10000); return NULL; } return rt; } -int main(void) +int main(int argc, char* argv[]) { - int fd_mem; - struct irq_routing_table *rt; - - if (getuid()) { - fprintf(stderr, "Run me as root, I need access to " MEM_DEV ".\n"); + char* ptr; + int fd_mem = -1; + struct irq_routing_table* rt = NULL; + void* bios_image = NULL; + if ( argc > 1 ) + { + /** there a paramater passed to the program, assume that it is a menory file */ + printf("Opening memory image file '%s'\n", argv[1]); + /** Open the file */ + fd_mem = open(argv[1], O_RDONLY); + if (fd_mem > 0) { + /** get tyhe size of the file */ + int file_size = lseek(fd_mem, 0, SEEK_END); + printf("Memory image '%i'\n", file_size); + /** get a memory block for it. */ + bios_image = malloc(file_size); + if (bios_image) { + /** Fill the created buffer */ + lseek(fd_mem, 0, SEEK_SET); + read(fd_mem, bios_image, file_size); + /** set the pointer for the probe function */ + ptr = (char*)bios_image; + } else { + /* no memory available ? */ + perror("Failed to open imagefile\n"); + return (-3); + } + } else { + /** An error occourd, just exit with a message */ + perror("Failed to open imagefile"); + return (-2); + } + } else { + /** No paramaters means that the program will access the system memory */ + printf("Accessing memory\n"); + if (getuid()) { + /** i'm not root message !!!! */ + fprintf(stderr, "Run me as root, I need access to " MEM_DEV ".\n"); + } + /** open the system memory */ + fd_mem = open(MEM_DEV, O_RDONLY); + if (fd_mem < 0) { + /** could not open the system memory, exit with a message */ + perror("Could not open " MEM_DEV ":"); + exit(1); + } + printf("Probing PIRQ table in memory.\n"); + ptr = mmap(0, 0x10000, PROT_READ, MAP_SHARED, fd_mem, (off_t)0xf0000); + if (ptr == MAP_FAILED) { + /** could not map the system memory, exit with a message */ + perror("Mapping system memory failed: "); + close(fd_mem); + return (1); + } } - - fd_mem = open(MEM_DEV, O_RDONLY); - if (fd_mem < 0) { - perror("Could not open " MEM_DEV ":"); - exit(1); + if (ptr) { + /** now do the actual probe function */ + rt = probe_table(ptr); + if (rt != NULL && bios_image == NULL) { + /** when probing system memory we write the 'irq_tables.c' code file */ + printf("Creating irq_tables.c ...\n"); + code_gen("irq_tables.c", rt); + printf("Done, you can move the file to the coreboot tree now.\n"); + } + } else { + printf("invalid memory pointer\n"); } - - printf("Probing PIRQ table in memory.\n"); - rt = probe_table(fd_mem); - if (rt != NULL) { - printf("Creating irq_tables.c ...\n"); - code_gen("irq_tables.c", rt); - printf - ("Done, you can move the file to the coreboot tree now.\n"); + if (bios_image) { + /** when we are reading from a file the memory must be released */ + free(bios_image); + } else { + /** when reading from the system memory, it must be unmapped */ + munmap(ptr, 0x10000); } + /** Close the file handle */ close(fd_mem); - - + /** return 0 as OK ) */ return 0; }

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[commit] r5715 - in trunk/src/mainboard/gigabyte: . ma78gm ma78gm/acpi
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 13:22:40 2010 New Revision: 5715 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5715 Log: Another AMD 780/700 mainboard: Gigabyte MA78GM-US2H http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov the simple config is AM2+DDR2+SB700+RS780, the superIO is IT8718F The patch has been tested with SeaBIOS + SUSE11.2 Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/mainboard/gigabyte/ma78gm/ - copied from r5712, trunk/src/mainboard/amd/tilapia_fam10/ Replaced: trunk/src/mainboard/gigabyte/ma78gm/mainboard.c - copied, changed from r5714, trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Deleted: trunk/src/mainboard/gigabyte/ma78gm/mb_sysconf.h trunk/src/mainboard/gigabyte/ma78gm/spd_addr.h Modified: trunk/src/mainboard/gigabyte/Kconfig trunk/src/mainboard/gigabyte/ma78gm/Kconfig trunk/src/mainboard/gigabyte/ma78gm/acpi/routing.asl trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c trunk/src/mainboard/gigabyte/ma78gm/chip.h trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl trunk/src/mainboard/gigabyte/ma78gm/mptable.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c Modified: trunk/src/mainboard/gigabyte/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/Kconfig Tue Aug 17 13:11:09 2010 (r5714) +++ trunk/src/mainboard/gigabyte/Kconfig Tue Aug 17 13:22:40 2010 (r5715) @@ -26,5 +26,6 @@ source "src/mainboard/gigabyte/ga-6bxe/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" +source "src/mainboard/gigabyte/ma78gm/Kconfig" endchoice Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig Tue Aug 17 13:22:40 2010 (r5715) @@ -1,7 +1,7 @@ -config BOARD_AMD_TILAPIA_FAM10 - bool "Tilapia (Fam10)" +config BOARD_GIGABYTE_MA78GM + bool "MA78GM-US2H" select ARCH_X86 - select CPU_AMD_SOCKET_AM3 + select CPU_AMD_SOCKET_AM2R2 select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 @@ -26,100 +26,100 @@ config MAINBOARD_DIR string - default amd/tilapia_fam10 - depends on BOARD_AMD_TILAPIA_FAM10 + default gigabyte/ma78gm + depends on BOARD_GIGABYTE_MA78GM config APIC_ID_OFFSET hex default 0x0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config MAINBOARD_PART_NUMBER string - default "Tilapia (Fam10)" - depends on BOARD_AMD_TILAPIA_FAM10 + default "GIGABYTE MA78GM" + depends on BOARD_GIGABYTE_MA78GM config HW_MEM_HOLE_SIZEK hex default 0x100000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config MAX_CPUS int default 8 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config MAX_PHYSICAL_CPUS int default 2 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config MEM_TRAIN_SEQ int default 2 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config SB_HT_CHAIN_ON_BUS0 int default 1 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config HT_CHAIN_END_UNITID_BASE hex default 0x1 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config HT_CHAIN_UNITID_BASE hex default 0x0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config IRQ_SLOT_COUNT int default 11 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000b6.h" - depends on BOARD_AMD_TILAPIA_FAM10 + default "mc_patch_01000095.h" + depends on BOARD_GIGABYTE_MA78GM config RAMTOP hex default 0x2000000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config HEAP_SIZE hex default 0xc0000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config ACPI_SSDTX_NUM int default 0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x1022 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config RAMBASE hex default 0x200000 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM config COMPRESS hex default 0 - depends on BOARD_AMD_TILAPIA_FAM10 + depends on BOARD_GIGABYTE_MA78GM Modified: trunk/src/mainboard/gigabyte/ma78gm/acpi/routing.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi/routing.asl Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/acpi/routing.asl Tue Aug 17 13:22:40 2010 (r5715) @@ -62,16 +62,21 @@ /* SB devices */ /* Bus 0, Dev 17 - SATA controller #2 */ /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, + Package(){0x0011FFFF, 0, INTA, 0 }, - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, + Package(){0x0012FFFF, 2, INTC, 0 }, - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTD, 0 }, + Package(){0x0013FFFF, 2, INTA, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, @@ -136,16 +141,22 @@ /* Bus 0, Dev 18 - SATA controller #1 */ Package(){0x0011FFFF, 0, 0, 22 }, - /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0013FFFF, 2, 0, 16 }, + + /* Package(){0x00140000, 0, 0, 16 }, */ + /* Package(){0x00130004, 2, 0, 18 }, */ /* Package(){0x00130005, 3, 0, 19 }, */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Modified: trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/acpi_tables.c Tue Aug 17 13:22:40 2010 (r5715) @@ -26,7 +26,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -#include "mb_sysconf.h" #define DUMP_ACPI_TABLES 0 Modified: trunk/src/mainboard/gigabyte/ma78gm/chip.h ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/chip.h Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/chip.h Tue Aug 17 13:22:40 2010 (r5715) @@ -21,6 +21,4 @@ extern struct chip_operations mainboard_ops; struct mainboard_config { -// int fixup_scsi; -// int fixup_vga; }; Modified: trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/devicetree.cb Tue Aug 17 13:22:40 2010 (r5715) @@ -1,7 +1,7 @@ -# sample config for amd/tilapia_fam10 +# sample config for gigabyte/ma78gm chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 + chip cpu/amd/socket_AM2r2 #L1 and DDR2 device lapic 0 on end end end @@ -24,8 +24,7 @@ register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - + register "gfx_dual_slot" = "1" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0" register "gfx_compliance" = "0" @@ -115,31 +114,4 @@ end end #pci_domain #for node 32 to node 63 -# device pci_domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # hard reset -# device pnp 0.9 off end # mcp55 -# device pnp 0.a on end # GH ext table -# end end Modified: trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl Tue Aug 17 13:22:40 2010 (r5715) @@ -22,8 +22,8 @@ "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "TILAPIA ", /* TABLE ID */ + "GIGA ", /* OEMID */ + "MA78GM-US2H", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ Copied and modified: trunk/src/mainboard/gigabyte/ma78gm/mainboard.c (from r5714, trunk/src/mainboard/amd/tilapia_fam10/mainboard.c) ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Tue Aug 17 13:11:09 2010 (r5714, copy source) +++ trunk/src/mainboard/gigabyte/ma78gm/mainboard.c Tue Aug 17 13:22:40 2010 (r5715) @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -28,20 +29,6 @@ #include <southbridge/amd/sb700/sb700.h> #include "chip.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ - -extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); - -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - #define SMBUS_IO_BASE 0x6000 uint64_t uma_memory_base, uma_memory_size; @@ -49,262 +36,70 @@ void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); - +/* + * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to + * pull it up before training the slot. + ***/ void set_pcie_dereset() { - u8 byte; u16 word; device_t sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ + /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset() -{ - u8 byte; - u16 word; - device_t sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); + word = pci_read_config16(sm_dev, 0xA8); + word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ + word &= ~((1 << 8) | (1 << 10)); + pci_write_config16(sm_dev, 0xA8, word); } -#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif - -/* - * justify the dev3 is exist or not - */ -u8 is_dev3_present(void) +void set_pcie_reset() { u16 word; device_t sm_dev; - - /* access the smbus extended register */ + /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - if(word & (1 << 10)){ - /*not exist*/ - return 0; - }else{ - /*exist*/ - return 1; - } + word = pci_read_config16(sm_dev, 0xA8); + word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ + word &= ~((1 << 8) | (1 << 10)); + pci_write_config16(sm_dev, 0xA8, word); } -/* - * set gpio40 gfx - */ -static void set_gpio40_gfx(void) -{ - u8 byte; - u32 dword; - device_t sm_dev; - /* disable the GPIO40 as CLKREQ2# function */ - byte = pm_ioread(0xd3); - byte &= ~(1 << 7); - pm_iowrite(0xd3, byte); - - /* disable the GPIO40 as CLKREQ3# function */ - byte = pm_ioread(0xd4); - byte &= ~(1 << 0); - pm_iowrite(0xd4, byte); - - /* enable pull up for GPIO68 */ - byte = pm2_ioread(0xf1); - byte &= ~(1 << 4); - pm2_iowrite(0xf1, byte); - - /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - /*if the dev3 is present, set the gfx to 2x8 lanes*/ - /*otherwise set the gfx to 1x16 lanes*/ - if(is_dev3_present()){ - - printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword |= (1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - - }else{ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - } -} - -/* - * set thermal config - */ -static void set_thermal_config(void) +u8 is_dev3_present(void) { - u8 byte; - u16 word; - device_t sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ + return 0; } /************************************************* -* enable the dedicated function in tilapia board. +* enable the dedicated function in board. * This function called early than rs780_enable. *************************************************/ -static void tilapia_enable(device_t dev) +static void ma78gm_enable(device_t dev) { /* Leave it for furture use. */ /* struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; */ - printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi); + /* refer to UMA Size Consideration in 780 BDG. */ switch (msr.lo) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ @@ -331,8 +126,6 @@ set_pcie_dereset(); /* get_ide_dma66(); */ - set_thermal_config(); - set_gpio40_gfx(); } int add_mainboard_resources(struct lb_memory *mem) @@ -350,6 +143,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TILAPIA Mainboard") - .enable_dev = tilapia_enable, + CHIP_NAME("GIGABYTE MA78GM-US2H") + .enable_dev = ma78gm_enable, }; Modified: trunk/src/mainboard/gigabyte/ma78gm/mptable.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mptable.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/mptable.c Tue Aug 17 13:22:40 2010 (r5715) @@ -43,7 +43,7 @@ { static const char sig[4] = "PCMP"; static const char oem[8] = "COREBOOT"; - static const char productid[12] = "TILAPIA "; + static const char productid[12] = "MA78GM-US2H "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Aug 17 12:54:36 2010 (r5712) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Aug 17 13:22:40 2010 (r5715) @@ -95,7 +95,6 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -//#include "spd_addr.h" #define RC00 0 #define RC01 1 @@ -137,11 +136,11 @@ sb700_lpc_init(); it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + it8718f_disable_reboot(); uart_init(); console_init(); printk(BIOS_DEBUG, "\n"); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -250,7 +249,6 @@ // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); @@ -261,3 +259,4 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } +

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[commit] r5714 - in trunk/src: mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh southbridge/amd/rs780
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 13:11:09 2010 New Revision: 5714 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5714 Log: Tilapila supports both dual slot and single slot. The difference should be detected by the existence of dev3. Some other RS780 mainboard has the same function. The patch added the function to make these boards work smoothly. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/mainboard/amd/mahogany/mainboard.c trunk/src/mainboard/amd/mahogany_fam10/mainboard.c trunk/src/mainboard/amd/tilapia_fam10/mainboard.c trunk/src/mainboard/asrock/939a785gmh/mainboard.c trunk/src/southbridge/amd/rs780/rs780_gfx.c Modified: trunk/src/mainboard/amd/mahogany/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/mainboard.c Tue Aug 17 13:08:31 2010 (r5713) +++ trunk/src/mainboard/amd/mahogany/mainboard.c Tue Aug 17 13:11:09 2010 (r5714) @@ -34,7 +34,7 @@ void set_pcie_dereset(void); void set_pcie_reset(void); - +u8 is_dev3_present(void); /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. @@ -94,6 +94,10 @@ } #endif /* get_ide_dma66 */ +u8 is_dev3_present(void) +{ + return 0; +} /************************************************* * enable the dedicated function in mahogany board. * This function called early than rs780_enable. Modified: trunk/src/mainboard/amd/mahogany_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/mainboard.c Tue Aug 17 13:08:31 2010 (r5713) +++ trunk/src/mainboard/amd/mahogany_fam10/mainboard.c Tue Aug 17 13:11:09 2010 (r5714) @@ -34,7 +34,7 @@ void set_pcie_dereset(void); void set_pcie_reset(void); - +u8 is_dev3_present(void); /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. @@ -94,6 +94,11 @@ } #endif /* get_ide_dma66() */ +u8 is_dev3_present(void) +{ + return 0; +} + /************************************************* * enable the dedicated function in mahogany board. * This function called early than rs780_enable. Modified: trunk/src/mainboard/amd/tilapia_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Tue Aug 17 13:08:31 2010 (r5713) +++ trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Tue Aug 17 13:11:09 2010 (r5714) @@ -48,6 +48,7 @@ void set_pcie_dereset(void); void set_pcie_reset(void); +u8 is_dev3_present(void); void set_pcie_dereset() { @@ -130,6 +131,90 @@ #endif /* + * justify the dev3 is exist or not + */ +u8 is_dev3_present(void) +{ + u16 word; + device_t sm_dev; + + /* access the smbus extended register */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + /* put the GPIO68 output to tristate */ + word = pci_read_config16(sm_dev, 0x7e); + word |= 1 << 6; + pci_write_config16(sm_dev, 0x7e,word); + + /* read the GPIO68 input status */ + word = pci_read_config16(sm_dev, 0x7e); + + if(word & (1 << 10)){ + /*not exist*/ + return 0; + }else{ + /*exist*/ + return 1; + } +} + + +/* + * set gpio40 gfx + */ +static void set_gpio40_gfx(void) +{ + u8 byte; + u32 dword; + device_t sm_dev; + /* disable the GPIO40 as CLKREQ2# function */ + byte = pm_ioread(0xd3); + byte &= ~(1 << 7); + pm_iowrite(0xd3, byte); + + /* disable the GPIO40 as CLKREQ3# function */ + byte = pm_ioread(0xd4); + byte &= ~(1 << 0); + pm_iowrite(0xd4, byte); + + /* enable pull up for GPIO68 */ + byte = pm2_ioread(0xf1); + byte &= ~(1 << 4); + pm2_iowrite(0xf1, byte); + + /* access the smbus extended register */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + /*if the dev3 is present, set the gfx to 2x8 lanes*/ + /*otherwise set the gfx to 1x16 lanes*/ + if(is_dev3_present()){ + + printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); + /* when the gpio40 is configured as GPIO, this will enable the output */ + pci_write_config32(sm_dev, 0xf8, 0x4); + dword = pci_read_config32(sm_dev, 0xfc); + dword &= ~(1 << 10); + + /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* 1 :enable two x8 , 0 : master slot enable only */ + dword |= (1 << 26); + pci_write_config32(sm_dev, 0xfc, dword); + + }else{ + printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); + /* when the gpio40 is configured as GPIO, this will enable the output */ + pci_write_config32(sm_dev, 0xf8, 0x4); + dword = pci_read_config32(sm_dev, 0xfc); + dword &= ~(1 << 10); + + /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* 1 :enable two x8 , 0 : master slot enable only */ + dword &= ~(1 << 26); + pci_write_config32(sm_dev, 0xfc, dword); + } +} + +/* * set thermal config */ static void set_thermal_config(void) @@ -247,6 +332,7 @@ set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); + set_gpio40_gfx(); } int add_mainboard_resources(struct lb_memory *mem) Modified: trunk/src/mainboard/asrock/939a785gmh/mainboard.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/mainboard.c Tue Aug 17 13:08:31 2010 (r5713) +++ trunk/src/mainboard/asrock/939a785gmh/mainboard.c Tue Aug 17 13:11:09 2010 (r5714) @@ -34,7 +34,7 @@ void set_pcie_dereset(void); void set_pcie_reset(void); - +u8 is_dev3_present(void); /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to * pull it up before training the slot. @@ -94,6 +94,11 @@ } #endif /* get_ide_dma66 */ +u8 is_dev3_present(void) +{ + return 0; +} + /************************************************* * enable the dedicated function in mahogany board. * This function called early than rs780_enable. Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Aug 17 13:08:31 2010 (r5713) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Aug 17 13:11:09 2010 (r5714) @@ -35,7 +35,7 @@ #include <delay.h> #include <cpu/x86/msr.h> #include "rs780.h" - +extern int is_dev3_present(void); void set_pcie_reset(void); void set_pcie_dereset(void); @@ -1214,6 +1214,40 @@ printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); dual_port_configuration(nb_dev, dev); break; + + case 2: + + if(is_dev3_present()){ + /* step 1, lane reversal (only need if CMOS option is enabled) */ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + } + printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); + /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ + /* AMD calls the configuration CrossFire */ + set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); + printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); + + + printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3); + dual_port_configuration(nb_dev, dev); + + }else{ + if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + } + printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); + printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); + + if((dev->path.pci.devfn >> 3) == 2) + single_port_configuration(nb_dev, dev); + else{ + set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */ + printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n"); + } + } + default: printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n"); break;

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[commit] r5712 - trunk/src/mainboard/nokia/ip530
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 12:54:36 2010 New Revision: 5712 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5712 Log: fix nokia ip530 Kconfig, missed on last check-in Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/nokia/ip530/Kconfig Modified: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- trunk/src/mainboard/nokia/ip530/Kconfig Tue Aug 17 12:14:50 2010 (r5711) +++ trunk/src/mainboard/nokia/ip530/Kconfig Tue Aug 17 12:54:36 2010 (r5712) @@ -25,7 +25,7 @@ select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_SMSC_SMSCSUPERIO select SOUTHBRIDGE_TI_PCI1X2X - select SOUTHBRIDGE_DEC_21143 + select DRIVERS_DEC_21143 select BOARD_ROMSIZE_KB_256 select ROMCC select PIRQ_ROUTE

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[filo] [PATCH trivial] 'make distclean' forgot to rm .xcompile
by Jens Rottmann 17 Aug '10

17 Aug '10

filo: 'make distclean' forgot to rm .xcompile Added to Makefile. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- --- filo/Makefile (revision 135) +++ filo/Makefile (working copy) @@ -159,7 +159,7 @@ distclean: clean $(Q)rm -rf build - $(Q)rm -f .config lib.config .config.old ..config.tmp .kconfig.d .tmpconfig* + $(Q)rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig* FORCE: _

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[commit] r5711 - in trunk/payloads/libpayload: drivers include
by repository service 17 Aug '10

17 Aug '10

Author: oxygene Date: Tue Aug 17 12:14:50 2010 New Revision: 5711 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5711 Log: libpayload: Add function to fix CMOS checksum. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/payloads/libpayload/drivers/options.c trunk/payloads/libpayload/include/libpayload.h Modified: trunk/payloads/libpayload/drivers/options.c ============================================================================== --- trunk/payloads/libpayload/drivers/options.c Tue Aug 17 11:52:01 2010 (r5710) +++ trunk/payloads/libpayload/drivers/options.c Tue Aug 17 12:14:50 2010 (r5711) @@ -48,6 +48,23 @@ return (checksum_old == checksum); } +void fix_options_checksum(void) +{ + int i; + int range_start = lib_sysinfo.cmos_range_start / 8; + int range_end = lib_sysinfo.cmos_range_end / 8; + int checksum_location = lib_sysinfo.cmos_checksum_location / 8; + u16 checksum = 0; + + for(i = range_start; i <= range_end; i++) { + checksum += nvram_read(i); + } + checksum = (~checksum)&0xffff; + + nvram_write((checksum >> 8), checksum_location); + nvram_write((checksum & 0xff), checksum_location + 1); +} + static int get_cmos_value(u32 bitnum, u32 len, void *valptr) { u8 *value = (u8 *)valptr; Modified: trunk/payloads/libpayload/include/libpayload.h ============================================================================== --- trunk/payloads/libpayload/include/libpayload.h Tue Aug 17 11:52:01 2010 (r5710) +++ trunk/payloads/libpayload/include/libpayload.h Tue Aug 17 12:14:50 2010 (r5711) @@ -194,6 +194,7 @@ /** @} */ /* drivers/option.c */ +void fix_options_checksum(void); int get_option(void *dest, char *name); /**

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[FILO] r136 - trunk/filo
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 12:14:40 2010 New Revision: 136 URL: http://tracker.coreboot.org/trac/filo/changeset/136 Log: filo: 'make distclean' forgot to rm .xcompile Added to Makefile. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/filo/Makefile Modified: trunk/filo/Makefile ============================================================================== --- trunk/filo/Makefile Mon Jul 19 20:33:46 2010 (r135) +++ trunk/filo/Makefile Tue Aug 17 12:14:40 2010 (r136) @@ -159,7 +159,7 @@ distclean: clean $(Q)rm -rf build - $(Q)rm -f .config lib.config .config.old ..config.tmp .kconfig.d .tmpconfig* + $(Q)rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig* FORCE:

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[commit] r5710 - in trunk/src: drivers drivers/dec drivers/dec/21143 drivers/generic/generic drivers/sil/3114 mainboard/amd/mahogany mainboard/tyan/s2881 mainboard/tyan/s2882 southbridge southbridg...
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 11:52:01 2010 New Revision: 5710 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5710 Log: Whatever happened here,... The DEC Tulip is a network card, no bridge of any kind. Move it to drivers and make the necessary adaptions. Also drop empty drivers/generic/generic and start cleaning up Makefiles in drivers/ Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/drivers/dec/ - copied from r5709, trunk/src/southbridge/dec/ Deleted: trunk/src/drivers/generic/generic/ trunk/src/southbridge/dec/ Modified: trunk/src/drivers/Kconfig trunk/src/drivers/Makefile.inc trunk/src/drivers/dec/21143/Kconfig trunk/src/drivers/dec/Kconfig trunk/src/drivers/dec/Makefile.inc trunk/src/drivers/sil/3114/Makefile.inc trunk/src/mainboard/amd/mahogany/dsdt.asl trunk/src/mainboard/tyan/s2881/Kconfig trunk/src/mainboard/tyan/s2882/Kconfig trunk/src/southbridge/Kconfig trunk/src/southbridge/Makefile.inc Modified: trunk/src/drivers/Kconfig ============================================================================== --- trunk/src/drivers/Kconfig Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/drivers/Kconfig Tue Aug 17 11:52:01 2010 (r5710) @@ -17,9 +17,13 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config DRIVERS_SIL +config DRIVERS_SIL_3114 bool "Silicon Image SIL3114" default n help It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it. + + +source src/drivers/dec/Kconfig + Modified: trunk/src/drivers/Makefile.inc ============================================================================== --- trunk/src/drivers/Makefile.inc Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/drivers/Makefile.inc Tue Aug 17 11:52:01 2010 (r5710) @@ -1,5 +1,35 @@ -subdirs-y += generic/debug +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += dec + +# should these be cleaned up to behave like all other subdirectories? + subdirs-y += ati/ragexl +subdirs-y += emulation/qemu +subdirs-y += generic/debug +subdirs-y += i2c/adm1026 +subdirs-y += i2c/adm1027 +subdirs-y += i2c/adt7463 +subdirs-y += i2c/i2cmux +subdirs-y += i2c/i2cmux2 +subdirs-y += i2c/lm63 subdirs-y += sil/3114 -subdirs-y += ti/pcmcia-cardbus -subdirs-y += dec/21143 +subdirs-y += trident/blade3d + Modified: trunk/src/drivers/dec/21143/Kconfig ============================================================================== --- trunk/src/southbridge/dec/21143/Kconfig Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/drivers/dec/21143/Kconfig Tue Aug 17 11:52:01 2010 (r5710) @@ -1,2 +1,2 @@ -config SOUTHBRIDGE_DEC_21143 +config DRIVERS_DEC_21143 bool Modified: trunk/src/drivers/dec/Kconfig ============================================================================== --- trunk/src/southbridge/dec/Kconfig Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/drivers/dec/Kconfig Tue Aug 17 11:52:01 2010 (r5710) @@ -1 +1 @@ -source src/southbridge/dec/21143/Kconfig +source src/drivers/dec/21143/Kconfig Modified: trunk/src/drivers/dec/Makefile.inc ============================================================================== --- trunk/src/southbridge/dec/Makefile.inc Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/drivers/dec/Makefile.inc Tue Aug 17 11:52:01 2010 (r5710) @@ -1 +1 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_DEC_21143) += 21143 +subdirs-$(CONFIG_DRIVERS_DEC_21143) += 21143 Modified: trunk/src/drivers/sil/3114/Makefile.inc ============================================================================== --- trunk/src/drivers/sil/3114/Makefile.inc Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/drivers/sil/3114/Makefile.inc Tue Aug 17 11:52:01 2010 (r5710) @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_SIL) += sil_sata.o +driver-$(CONFIG_DRIVERS_SIL_3114) += sil_sata.o Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany/dsdt.asl Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/mainboard/amd/mahogany/dsdt.asl Tue Aug 17 11:52:01 2010 (r5710) @@ -270,7 +270,7 @@ /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ + */ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ Modified: trunk/src/mainboard/tyan/s2881/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2881/Kconfig Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/mainboard/tyan/s2881/Kconfig Tue Aug 17 11:52:01 2010 (r5710) @@ -14,7 +14,7 @@ select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select DRIVERS_SIL + select DRIVERS_SIL_3114 config MAINBOARD_DIR string Modified: trunk/src/mainboard/tyan/s2882/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2882/Kconfig Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/mainboard/tyan/s2882/Kconfig Tue Aug 17 11:52:01 2010 (r5710) @@ -13,7 +13,7 @@ select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select DRIVERS_SIL + select DRIVERS_SIL_3114 config MAINBOARD_DIR string Modified: trunk/src/southbridge/Kconfig ============================================================================== --- trunk/src/southbridge/Kconfig Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/southbridge/Kconfig Tue Aug 17 11:52:01 2010 (r5710) @@ -1,6 +1,5 @@ source src/southbridge/amd/Kconfig source src/southbridge/broadcom/Kconfig -source src/southbridge/dec/Kconfig source src/southbridge/intel/Kconfig source src/southbridge/nvidia/Kconfig source src/southbridge/ricoh/Kconfig Modified: trunk/src/southbridge/Makefile.inc ============================================================================== --- trunk/src/southbridge/Makefile.inc Tue Aug 17 10:33:44 2010 (r5709) +++ trunk/src/southbridge/Makefile.inc Tue Aug 17 11:52:01 2010 (r5710) @@ -1,6 +1,5 @@ subdirs-y += amd subdirs-y += broadcom -subdirs-y += dec subdirs-y += intel subdirs-y += nvidia subdirs-y += ricoh

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[commit] r5709 - trunk/util/inteltool
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 10:33:44 2010 New Revision: 5709 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5709 Log: Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges. Both are tested and appear to be working, however I'm not 100% clear on if the NM10 has any other PCI IDs. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Modified: trunk/util/inteltool/gpio.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/powermgt.c trunk/util/inteltool/rootcmplx.c Modified: trunk/util/inteltool/gpio.c ============================================================================== --- trunk/util/inteltool/gpio.c Tue Aug 17 10:24:01 2010 (r5708) +++ trunk/util/inteltool/gpio.c Tue Aug 17 10:33:44 2010 (r5709) @@ -171,6 +171,7 @@ gpio_registers = ich9_gpio_registers; size = ARRAY_SIZE(ich9_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich8_gpio_registers; @@ -180,6 +181,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_NM10: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Tue Aug 17 10:24:01 2010 (r5708) +++ trunk/util/inteltool/inteltool.c Tue Aug 17 10:33:44 2010 (r5709) @@ -61,6 +61,8 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9M, "ICH9M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9ME, "ICH9M-E" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8, "ICH8" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10, "NM10" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Tue Aug 17 10:24:01 2010 (r5708) +++ trunk/util/inteltool/inteltool.h Tue Aug 17 10:33:44 2010 (r5709) @@ -43,6 +43,8 @@ #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_NM10 0x27bc +#define PCI_DEVICE_ID_INTEL_ICH8 0x2810 #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_ICH9DH 0x2912 #define PCI_DEVICE_ID_INTEL_ICH9DO 0x2914 Modified: trunk/util/inteltool/powermgt.c ============================================================================== --- trunk/util/inteltool/powermgt.c Tue Aug 17 10:24:01 2010 (r5708) +++ trunk/util/inteltool/powermgt.c Tue Aug 17 10:33:44 2010 (r5709) @@ -477,6 +477,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_NM10: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich7_pm_registers; size = ARRAY_SIZE(ich7_pm_registers); @@ -491,6 +492,7 @@ pm_registers = ich9_pm_registers; size = ARRAY_SIZE(ich9_pm_registers); break; + case PCI_DEVICE_ID_INTEL_ICH8: case PCI_DEVICE_ID_INTEL_ICH8M: pmbase = pci_read_word(sb, 0x40) & 0xfffc; pm_registers = ich8_pm_registers; Modified: trunk/util/inteltool/rootcmplx.c ============================================================================== --- trunk/util/inteltool/rootcmplx.c Tue Aug 17 10:24:01 2010 (r5708) +++ trunk/util/inteltool/rootcmplx.c Tue Aug 17 10:33:44 2010 (r5709) @@ -43,6 +43,8 @@ case PCI_DEVICE_ID_INTEL_ICH9M: case PCI_DEVICE_ID_INTEL_ICH9ME: case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH8: + case PCI_DEVICE_ID_INTEL_NM10: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH:

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[commit] r5708 - trunk/util/superiotool
by repository service 17 Aug '10

17 Aug '10

Author: stepan Date: Tue Aug 17 10:24:01 2010 New Revision: 5708 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5708 Log: Add support for Fintek F81216D/DG/AD Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/superiotool/fintek.c trunk/util/superiotool/superiotool.c trunk/util/superiotool/superiotool.h Modified: trunk/util/superiotool/fintek.c ============================================================================== --- trunk/util/superiotool/fintek.c Tue Aug 17 09:46:50 2010 (r5707) +++ trunk/util/superiotool/fintek.c Tue Aug 17 10:24:01 2010 (r5708) @@ -153,6 +153,46 @@ {EOT}}}, {0x0581, "F8000", { /* Fintek/ASUS F8000 */ {EOT}}}, + {0x0802, "F81216D/DG", { + {NOLDN, NULL, + {0x25,0x2f,EOT}, + {0x00,RSVD,EOT}}, + {0x0, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x40,EOT}}, + {0x1, "UART2", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {NANA,NANA,NANA,NANA,0x00,EOT}}, + {0x2, "UART3", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {NANA,NANA,NANA,NANA,0x00,EOT}}, + {0x3, "UART4", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {NANA,NANA,NANA,NANA,0x00,EOT}}, + {0x8, "WDT", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, + {0x1602, "F81216AD", { + {NOLDN, NULL, + {0x25,0x27,EOT}, + {0x00,NANA,EOT}}, + {0x0, "UART1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x40,0x00,0x00,EOT}}, + {0x1, "UART2", + {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x2, "UART3", + {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x3, "UART4", + {0x30,0x60,0x61,0x70,0xf0,0xf4,0xf5,EOT}, + {NANA,NANA,NANA,NANA,0x00,0x00,0x00,EOT}}, + {0x8, "WDT", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {EOT} }; @@ -186,6 +226,37 @@ exit_conf_mode_winbond_fintek_ite_8787(port); } + +void probe_idregs_fintek_alternative(uint16_t port) +{ + uint16_t vid, did; + + probing_for("Fintek", "", port); + + enter_conf_mode_fintek_7777(port); + + did = regval(port, DEVICE_ID_BYTE1_REG); + did |= (regval(port, DEVICE_ID_BYTE2_REG) << 8); + + vid = regval(port, VENDOR_ID_BYTE1_REG); + vid |= (regval(port, VENDOR_ID_BYTE2_REG) << 8); + + if (vid != FINTEK_VENDOR_ID || superio_unknown(reg_table, did)) { + if (verbose) + printf(NOTFOUND "vid=0x%04x, id=0x%04x\n", vid, did); + exit_conf_mode_fintek_7777(port); + return; + } + + printf("Found Fintek %s (vid=0x%04x, id=0x%04x) at 0x%x\n", + get_superio_name(reg_table, did), vid, did, port); + chip_found = 1; + + dump_superio("Fintek", reg_table, port, did, LDN_SEL); + + exit_conf_mode_fintek_7777(port); +} + void print_fintek_chips(void) { print_vendor_chips("Fintek", reg_table); Modified: trunk/util/superiotool/superiotool.c ============================================================================== --- trunk/util/superiotool/superiotool.c Tue Aug 17 09:46:50 2010 (r5707) +++ trunk/util/superiotool/superiotool.c Tue Aug 17 10:24:01 2010 (r5708) @@ -58,11 +58,23 @@ regwrite(port, 0x02, 0x02); /* ITE */ } +void enter_conf_mode_fintek_7777(uint16_t port) +{ + OUTB(0x77, port); + OUTB(0x77, port); +} + +void exit_conf_mode_fintek_7777(uint16_t port) +{ + OUTB(0xaa, port); /* Fintek */ +} + int superio_unknown(const struct superio_registers reg_table[], uint16_t id) { return !strncmp(get_superio_name(reg_table, id), "<unknown>", 9); } + const char *get_superio_name(const struct superio_registers reg_table[], uint16_t id) { Modified: trunk/util/superiotool/superiotool.h ============================================================================== --- trunk/util/superiotool/superiotool.h Tue Aug 17 09:46:50 2010 (r5707) +++ trunk/util/superiotool/superiotool.h Tue Aug 17 10:24:01 2010 (r5708) @@ -117,6 +117,8 @@ void regwrite(uint16_t port, uint8_t reg, uint8_t val); void enter_conf_mode_winbond_fintek_ite_8787(uint16_t port); void exit_conf_mode_winbond_fintek_ite_8787(uint16_t port); +void enter_conf_mode_fintek_7777(uint16_t port); +void exit_conf_mode_fintek_7777(uint16_t port); int superio_unknown(const struct superio_registers reg_table[], uint16_t id); const char *get_superio_name(const struct superio_registers reg_table[], uint16_t id); @@ -133,6 +135,7 @@ /* fintek.c */ void probe_idregs_fintek(uint16_t port); +void probe_idregs_fintek_alternative(uint16_t port); void print_fintek_chips(void); /* ite.c */ @@ -168,6 +171,7 @@ } superio_ports_table[] = { {probe_idregs_ali, {0x3f0, 0x370, EOT}}, {probe_idregs_fintek, {0x2e, 0x4e, EOT}}, + {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}}, /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}},

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coreboot August 2010