coreboot August 2010

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267 discussions

build service results for r5720
by repository service 17 Aug '10

17 Aug '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 5720 to the coreboot repository. This caused the following changes: Change Log: Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and I removed the gpio asserts - I think those are not used here. The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better. The classic PCI slot works fine too. However it seems SATA has some issues. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5720&device=pa78vm5&vendor… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] tidy up Asrock 939A785GMH
by Rudolf Marek 17 Aug '10

17 Aug '10

Hi all, Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and I removed the gpio asserts - I think those are not used here. The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better. The classic PCI slot works fine too. However it seems SATA has some issues. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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[commit] r5720 - in trunk/src/mainboard/asrock/939a785gmh: . acpi
by repository service 17 Aug '10

17 Aug '10

Author: ruik Date: Tue Aug 17 23:03:17 2010 New Revision: 5720 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5720 Log: Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and I removed the gpio asserts - I think those are not used here. The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better. The classic PCI slot works fine too. However it seems SATA has some issues. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl trunk/src/mainboard/asrock/939a785gmh/devicetree.cb trunk/src/mainboard/asrock/939a785gmh/dsdt.asl trunk/src/mainboard/asrock/939a785gmh/mainboard.c Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl Tue Aug 17 18:32:42 2010 (r5719) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl Tue Aug 17 23:03:17 2010 (r5720) @@ -32,31 +32,12 @@ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices */ @@ -69,12 +50,12 @@ Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, Package(){0x0012FFFF, 2, INTC, 0 }, + Package(){0x0012FFFF, 3, INTD, 0 }, Package(){0x0013FFFF, 0, INTC, 0 }, Package(){0x0013FFFF, 1, INTD, 0 }, Package(){0x0013FFFF, 2, INTA, 0 }, - - /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + Package(){0x0013FFFF, 3, INTB, 0 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, @@ -93,47 +74,21 @@ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, - /* Bus 0, Dev 9 - PCIe Bridge for network card */ + /* Bus 0, Dev 9 - PCIe x1 slot */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ - /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x0009FFFF, 1, 0, 18 }, + Package(){0x0009FFFF, 2, 0, 19 }, + Package(){0x0009FFFF, 3, 0, 10 }, + + /* Bus 0, Dev A - PCIe internal ethernet */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ + Package(){0x000AFFFF, 1, 0, 19 }, + Package(){0x000AFFFF, 2, 0, 16 }, + Package(){0x000AFFFF, 3, 0, 17 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ @@ -146,41 +101,34 @@ Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 1, 0, 17 }, Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0012FFFF, 3, 0, 19 }, Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 19 }, Package(){0x0013FFFF, 2, 0, 16 }, - - /* Package(){0x00140000, 0, 0, 16 }, */ - - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ + Package(){0x0013FFFF, 3, 0, 17 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ }) Name(PR1, Package(){ /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, + Package(){0x0005FFFF, 0, INTC, 0 }, + Package(){0x0005FFFF, 1, INTD, 0 }, + Package(){0x0005FFFF, 2, INTA, 0 }, + Package(){0x0005FFFF, 3, INTB, 0 }, }) Name(APR1, Package(){ /* Internal graphics - RS780 VGA, Bus1, Dev5 */ Package(){0x0005FFFF, 0, 0, 18 }, Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ + Package(){0x0005FFFF, 2, 0, 16 }, + Package(){0x0005FFFF, 3, 0, 11 }, }) Name(PS2, Package(){ @@ -198,72 +146,9 @@ Package(){0x0000FFFF, 2, 0, 16 }, Package(){0x0000FFFF, 3, 0, 17 }, }) - - Name(PS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - - Name(APS4, Package(){ - /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - - Name(APS5, Package(){ - /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - - Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - - Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) + Name(PS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ + /* PCIe slot - Hooked to PCIe x1 */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, @@ -271,14 +156,14 @@ }) Name(APS9, Package(){ - /* PCIe slot - Hooked to PCIe slot 9 */ + /* PCIe slot - Hooked to PCIe x1 */ Package(){0x0000FFFF, 0, 0, 17 }, Package(){0x0000FFFF, 1, 0, 18 }, Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 3, 0, 16 }, }) Name(PSa, Package(){ - /* PCIe slot - Hooked to PCIe slot 10 */ + /* PCIe slot - Hooked to ethernet */ Package(){0x0000FFFF, 0, INTD, 0 }, Package(){0x0000FFFF, 1, INTA, 0 }, Package(){0x0000FFFF, 2, INTB, 0 }, Modified: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Tue Aug 17 18:32:42 2010 (r5719) +++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Tue Aug 17 23:03:17 2010 (r5720) @@ -1,8 +1,9 @@ -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define gppsb_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots) #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support #Define gfx_compliance, 0: didn't support compliance, 1: support @@ -20,20 +21,20 @@ chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 2.0 on end # PCIE P2P bridge 16x slot + device pci 3.0 off end # used in dual slot config + device pci 4.0 off end # GPPSB + device pci 5.0 off end # GPPSB + device pci 6.0 off end # GPPSB + device pci 7.0 off end # GPPSB device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B + device pci 9.0 on end # GPP for x1 slot + device pci a.0 on end # GPP for internal network adapter + register "gppsb_configuration" = "4" # Configuration ? register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" + register "port_enable" = "0x60c" register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" + register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" register "gfx_tmds" = "0" register "gfx_compliance" = "0" Modified: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Tue Aug 17 18:32:42 2010 (r5719) +++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Tue Aug 17 23:03:17 2010 (r5720) @@ -1064,10 +1064,6 @@ Method(_L18) { /* DBGO("\\_GPE\\_L18\n") */ Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } @@ -1166,46 +1162,7 @@ } /* end _PRT */ } /* end PBR2 */ - /* Dev3 is also an external GFX bridge, not used in Herring */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - /* GPP */ + /* GPP x1 */ Device(PBR9) { Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) @@ -1215,6 +1172,7 @@ } /* end _PRT */ } /* end PBR9 */ + /* ethernet */ Device(PBRa) { Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Modified: trunk/src/mainboard/asrock/939a785gmh/mainboard.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/mainboard.c Tue Aug 17 18:32:42 2010 (r5719) +++ trunk/src/mainboard/asrock/939a785gmh/mainboard.c Tue Aug 17 23:03:17 2010 (r5720) @@ -35,34 +35,12 @@ void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); -/* - * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to - * pull it up before training the slot. - ***/ void set_pcie_dereset() { - u16 word; - device_t sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - word = pci_read_config16(sm_dev, 0xA8); - word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); } void set_pcie_reset() { - u16 word; - device_t sm_dev; - /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - word = pci_read_config16(sm_dev, 0xA8); - word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ - word &= ~((1 << 8) | (1 << 10)); - pci_write_config16(sm_dev, 0xA8, word); } #if 0 /* not tested yet */ @@ -103,13 +81,13 @@ * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mahogany_enable(device_t dev) +static void mb_enable(device_t dev) { /* Leave it for future. */ /* struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info;*/ - printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -170,6 +148,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD MAHOGANY Mainboard") - .enable_dev = mahogany_enable, + CHIP_NAME("Asrock 939A785GMH/128M Mainboard") + .enable_dev = mb_enable, };

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build service results for r5719
by repository service 17 Aug '10

17 Aug '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5719 to the coreboot repository. This caused the following changes: Change Log: Correct for size_t would be %zx, but coreboot's printf doesn't support this. Trying to keep it simple: Two sizes are expected equal so use same %x for both. Cast to unsigned int to make sure it fits. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5719&device=pa78vm5&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] sizeof doesn't always return long, it seems
by Jens Rottmann 17 Aug '10

17 Aug '10

coreboot: sizeof doesn't always return long, it seems Correct for size_t would be %zx, but coreboot's printf doesn't support this. Trying to keep it simple: Two sizes are expected equal so use same %x for both. Cast to unsigned int to make sure it fits. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> --- Hi Myles, you have changed this from %x to %lx with rev 5603. But my gcc 4.3.2 (32 bits) appearently doesn't like it. Maybe you have a 64 bit system? If my approach is ok for you, would you please commit? Thanks, Jens --- src/arch/i386/boot/pirq_routing.c (revision 5697) +++ src/arch/i386/boot/pirq_routing.c (working copy) @@ -13,8 +13,8 @@ printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n"); if (sizeof(struct irq_routing_table) != rt->size) { - printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%lx/0x%x).\n", - sizeof(struct irq_routing_table), + printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", + (unsigned int)sizeof(struct irq_routing_table), rt->size ); rt->size=sizeof(struct irq_routing_table); _

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[commit] r5719 - trunk/src/arch/i386/boot
by repository service 17 Aug '10

17 Aug '10

Author: myles Date: Tue Aug 17 18:32:42 2010 New Revision: 5719 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5719 Log: Correct for size_t would be %zx, but coreboot's printf doesn't support this. Trying to keep it simple: Two sizes are expected equal so use same %x for both. Cast to unsigned int to make sure it fits. Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/arch/i386/boot/pirq_routing.c Modified: trunk/src/arch/i386/boot/pirq_routing.c ============================================================================== --- trunk/src/arch/i386/boot/pirq_routing.c Tue Aug 17 17:19:32 2010 (r5718) +++ trunk/src/arch/i386/boot/pirq_routing.c Tue Aug 17 18:32:42 2010 (r5719) @@ -13,8 +13,8 @@ printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n"); if (sizeof(struct irq_routing_table) != rt->size) { - printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%lx/0x%x).\n", - sizeof(struct irq_routing_table), + printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", + (unsigned int) sizeof(struct irq_routing_table), rt->size ); rt->size=sizeof(struct irq_routing_table);

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DL145 G1 with dual dualcore CPU using coreboot ?
by Oskar Enoksson 17 Aug '10

17 Aug '10

Hello. Sorry to bother you all with a BIOS problem ... I have a large number of old HP DL145 G1 servers with two Opteron 248 each (single core). I want to upgrade the CPU's to Opteron 280 (dualcore). I have tried to simply install two 280 CPU's and boot up. The BIOS bootup process first seems to work fine detecting the harddrive, USB, management processor, memory etc. Then there is a warning text "Warning: Unknown processor. Please contact your BIOS vendor for appropriate updates". After that it detects the BMC I already have the last BIOS available from HP (from 21/7 2005) installed. Would it be possible to tweak coreboot to make these servers work with dualcore CPU's? The DL145 G1 Mobo is a re-branded Celestica A2210. Thanks! /Oskar Here follows output from lcpci, lspci -tvnn and dmidecode on one of the servers. [root@cl001 coreboot]# lspci 00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 00:01.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 00:02.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 00:02.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) 00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 05) 00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev 03) 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:00.0 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b) 01:00.1 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b) 01:04.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27) 02:03.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5704 Gigabit Ethernet (rev 03) 02:03.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5704 Gigabit Ethernet (rev 03) 03:01.0 Network controller: MYRICOM Inc. Myrinet 2000 Scalable Cluster Interconnect (rev 04) bash-3.2$ lspci -tvnn -[0000:00]-+-01.0-[0000:03]----01.0 14c1:8043 +-01.1 1022:7451 +-02.0-[0000:02]--+-03.0 14e4:1648 | \-03.1 14e4:1648 +-02.1 1022:7451 +-06.0-[0000:01]--+-00.0 1022:7464 | +-00.1 1022:7464 | \-04.0 1002:4752 +-07.0 1022:7468 +-07.1 1022:7469 +-07.3 1022:746b +-18.0 1022:1100 +-18.1 1022:1101 +-18.2 1022:1102 +-18.3 1022:1103 +-19.0 1022:1100 +-19.1 1022:1101 +-19.2 1022:1102 \-19.3 1022:1103 # dmidecode 2.10 SMBIOS 2.3 present. 64 structures occupying 2400 bytes. Table at 0x000F85B0. Handle 0x0000, DMI type 0, 20 bytes BIOS Information Vendor: American Megatrends Inc. Version: 080008 Release Date: 07/21/2005 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 512 kB Characteristics: ISA is supported PCI is supported PNP is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 kB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported LS-120 boot is supported ATAPI Zip drive boot is supported BIOS boot specification is supported Function key-initiated network boot is supported Handle 0x0001, DMI type 1, 25 bytes System Information Manufacturer: HP Product Name: ProLiant DL145 G1 Version: Serial Number: 8022MNMZ49 UUID: 91FAEE80-5664-11D9-8000-00001A1A5F86 Wake-up Type: Power Switch Handle 0x0002, DMI type 2, 8 bytes Base Board Information Manufacturer: HP Product Name: PCBA Serenade-3 V0100219-300 Version: Serial Number: Handle 0x0003, DMI type 3, 17 bytes Chassis Information Manufacturer: HP Type: Rack Mount Chassis Lock: Not Present Version: Serial Number: Asset Tag: ................ Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Handle 0x0004, DMI type 4, 35 bytes Processor Information Socket Designation: H0 Type: Central Processor Family: Opteron Manufacturer: AMD ID: 5A 0F 00 00 FF FB 8B 07 Signature: Family 15, Model 5, Stepping 10 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) Version: AMD Opteron(tm) Processor 248 Voltage: 3.3 V 2.9 V External Clock: 200 MHz Max Speed: 2200 MHz Current Speed: 2200 MHz Status: Populated, Enabled Upgrade: Socket 940 L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: Not Implemented Asset Tag: Not Implemented Part Number: Not Implemented Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 64 kB Maximum Size: 64 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Data Associativity: 4-way Set-associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 1024 kB Maximum Size: 1024 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 4-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Disabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 0 kB Maximum Size: 0 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x0008, DMI type 4, 35 bytes Processor Information Socket Designation: H1 Type: Central Processor Family: Opteron Manufacturer: AMD ID: 5A 0F 00 00 FF FB 8B 07 Signature: Family 15, Model 5, Stepping 10 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) Version: AMD Opteron(tm) Processor 248 Voltage: 3.3 V 2.9 V External Clock: 200 MHz Max Speed: 2200 MHz Current Speed: 2200 MHz Status: Populated, Enabled Upgrade: Socket 940 L1 Cache Handle: 0x0009 L2 Cache Handle: 0x000A L3 Cache Handle: 0x000B Serial Number: Not Implemented Asset Tag: Not Implemented Part Number: Not Implemented Handle 0x0009, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 64 kB Maximum Size: 64 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Data Associativity: 4-way Set-associative Handle 0x000A, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 1024 kB Maximum Size: 1024 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 4-way Set-associative Handle 0x000B, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Disabled, Not Socketed, Level 3 Operational Mode: Unknown Location: Internal Installed Size: 0 kB Maximum Size: 0 kB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: PS2Mouse External Connector Type: PS/2 Port Type: Mouse Port Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1A1 Internal Connector Type: None External Reference Designator: Keyboard External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2 Internal Connector Type: None External Reference Designator: USB1 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A2 Internal Connector Type: None External Reference Designator: USB2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2A1 Internal Connector Type: None External Reference Designator: COM A External Connector Type: DB-9 male Port Type: Serial Port 16550A Compatible Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6A1 Internal Connector Type: None External Reference Designator: Audio Mic In External Connector Type: Mini Jack (headphones) Port Type: Audio Port Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6A1 Internal Connector Type: None External Reference Designator: Audio Line In External Connector Type: Mini Jack (headphones) Port Type: Audio Port Handle 0x0013, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6B1 - AUX IN Internal Connector Type: On Board Sound Input From CD-ROM External Reference Designator: Not Specified External Connector Type: None Port Type: Audio Port Handle 0x0014, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6B2 - CDIN Internal Connector Type: On Board Sound Input From CD-ROM External Reference Designator: Not Specified External Connector Type: None Port Type: Audio Port Handle 0x0015, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6J2 - PRI IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0016, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6J1 - SEC IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0017, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J4J1 - FLOPPY Internal Connector Type: On Board Floppy External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0018, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9H1 - FRONT PNL Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0019, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1B1 - CHASSIS REAR FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001A, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2F1 - CPU FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J8B4 - FRONT FAN Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G2 - FNT USB Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J6C3 - FP AUD Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G1 - CONFIG Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x001F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J8C1 - SCSI LED Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0020, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9J2 - INTRUDER Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0021, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J9G4 - ITP Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0022, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J2H1 - MAIN POWER Internal Connector Type: Other External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x0023, DMI type 9, 13 bytes System Slot Information Designation: AGP Type: 32-bit AGP 4x Current Usage: Available Length: Short ID: 0 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0024, DMI type 9, 13 bytes System Slot Information Designation: PCI1 Type: 32-bit PCI Current Usage: In Use Length: Short ID: 1 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0025, DMI type 126, 6 bytes Inactive Handle 0x0026, DMI type 10, 6 bytes On Board Device Information Type: Ethernet Status: Enabled Description: Broadcom LAN Handle 0x0027, DMI type 10, 6 bytes On Board Device Information Type: Other Status: Enabled Description: QLogic BMC Handle 0x0028, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 1 en|US|iso8859-1 Currently Installed Language: en|US|iso8859-1 Handle 0x0029, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 8 GB Error Information Handle: Not Provided Number Of Devices: 4 Handle 0x002A, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000F9FFFFFF Range Size: 4000 MB Physical Array Handle: 0x0029 Partition Width: 0 Handle 0x002B, DMI type 17, 27 bytes Memory Device Array Handle: 0x0029 Error Information Handle: Not Provided Total Width: 72 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: H0_DIMM0 Bank Locator: BANK0 Type: DDR Type Detail: Synchronous Speed: 333 MHz Manufacturer: Manufacturer1 Serial Number: SerNum1 Asset Tag: AssetTagNum1 Part Number: PartNum1 Handle 0x002C, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0003FFFFFFF Range Size: 1 GB Physical Device Handle: 0x002B Memory Array Mapped Address Handle: 0x002A Partition Row Position: 1 Handle 0x002D, DMI type 17, 27 bytes Memory Device Array Handle: 0x0029 Error Information Handle: Not Provided Total Width: 72 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: H0_DIMM1 Bank Locator: BANK1 Type: DDR Type Detail: Synchronous Speed: 333 MHz Manufacturer: Manufacturer2 Serial Number: SerNum2 Asset Tag: AssetTagNum2 Part Number: PartNum2 Handle 0x002E, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00040000000 Ending Address: 0x0007FFFFFFF Range Size: 1 GB Physical Device Handle: 0x002D Memory Array Mapped Address Handle: 0x002A Partition Row Position: 1 Handle 0x002F, DMI type 17, 27 bytes Memory Device Array Handle: 0x0029 Error Information Handle: Not Provided Total Width: 64 bits Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: H0_DIMM2 Bank Locator: BANK2 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer3 Serial Number: SerNum3 Asset Tag: AssetTagNum3 Part Number: PartNum3 Handle 0x0030, DMI type 126, 19 bytes Inactive Handle 0x0031, DMI type 17, 27 bytes Memory Device Array Handle: 0x0029 Error Information Handle: Not Provided Total Width: 64 bits Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: H0_DIMM3 Bank Locator: BANK3 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer4 Serial Number: SerNum4 Asset Tag: AssetTagNum4 Part Number: PartNum4 Handle 0x0032, DMI type 126, 19 bytes Inactive Handle 0x0033, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 8 GB Error Information Handle: Not Provided Number Of Devices: 4 Handle 0x0034, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000F9FFFFFF Range Size: 4000 MB Physical Array Handle: 0x0033 Partition Width: 0 Handle 0x0035, DMI type 17, 27 bytes Memory Device Array Handle: 0x0033 Error Information Handle: Not Provided Total Width: 72 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: H1_DIMM0 Bank Locator: BANK4 Type: DDR Type Detail: Synchronous Speed: 333 MHz Manufacturer: Manufacturer5 Serial Number: SerNum5 Asset Tag: AssetTagNum5 Part Number: PartNum5 Handle 0x0036, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00080000000 Ending Address: 0x000BFFFFFFF Range Size: 1 GB Physical Device Handle: 0x0035 Memory Array Mapped Address Handle: 0x0034 Partition Row Position: 1 Handle 0x0037, DMI type 17, 27 bytes Memory Device Array Handle: 0x0033 Error Information Handle: Not Provided Total Width: 72 bits Data Width: 64 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: H1_DIMM1 Bank Locator: BANK5 Type: DDR Type Detail: Synchronous Speed: 333 MHz Manufacturer: Manufacturer6 Serial Number: SerNum6 Asset Tag: AssetTagNum6 Part Number: PartNum6 Handle 0x0038, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x000C0000000 Ending Address: 0x000FFFFFFFF Range Size: 1 GB Physical Device Handle: 0x0037 Memory Array Mapped Address Handle: 0x0034 Partition Row Position: 1 Handle 0x0039, DMI type 17, 27 bytes Memory Device Array Handle: 0x0033 Error Information Handle: Not Provided Total Width: 64 bits Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: H1_DIMM2 Bank Locator: BANK6 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer7 Serial Number: SerNum7 Asset Tag: AssetTagNum7 Part Number: PartNum7 Handle 0x003A, DMI type 126, 19 bytes Inactive Handle 0x003B, DMI type 17, 27 bytes Memory Device Array Handle: 0x0033 Error Information Handle: Not Provided Total Width: 64 bits Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: H1_DIMM3 Bank Locator: BANK7 Type: Unknown Type Detail: Unknown Speed: Unknown Manufacturer: Manufacturer8 Serial Number: SerNum8 Asset Tag: AssetTagNum8 Part Number: PartNum8 Handle 0x003C, DMI type 126, 19 bytes Inactive Handle 0x003D, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x003E, DMI type 38, 16 bytes IPMI Device Information Interface Type: KCS (Keyboard Control Style) Specification Version: 1.5 I2C Slave Address: 0x00 NV Storage Device: Not Present Base Address: 0x0000000000000CA2 (Memory-mapped) Handle 0x003F, DMI type 127, 4 bytes End Of Table

6 25

build service results for r5718
by repository service 17 Aug '10

17 Aug '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5718 to the coreboot repository. This caused the following changes: Change Log: Commit (non-working!) Jetway PA78VM5 mainboard Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5718&device=pa78vm5&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

Progress about ASRock 939A785GMH/128M
by axm.ffm＠gmx.de 17 Aug '10

17 Aug '10

Hi, I'm the owner of this MB and would like to ask if it coreboot V4 can be used or is there something important missing? Best regards, Alex -- GMX DSL SOMMER-SPECIAL: Surf & Phone Flat 16.000 für nur 19,99 ¿/mtl.!* http://portal.gmx.net/de/go/dsl

2 1

[PATCH] filo kconfig
by baiyin cai 17 Aug '10

17 Aug '10

hi all, i updated an new patch for filo kconfig. which involves following things: 1. Using make -C command to replace the old method which use filo/kconfig to load libpayload .config file. it make the code seems much simpler. 2. The latest filo kconfig did only printf an message the reminder that lib.config is missing. In the new patch,filo will load the default config for libpayload. 3. Fixing the bug which cause the libpayload building each time the filo is buiding. Any consideration is welcome about these filo kconfig. Signed-off-by: Cai Bai Yin <caibayin.pku(a)gmail.com>

2 1

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coreboot August 2010