coreboot August 2010

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[commit] r5730 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdmct
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:48:29 2010 New Revision: 5730 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5730 Log: Include RB_C3 in erratum 346 Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:45:57 2010 (r5729) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:48:29 2010 (r5730) @@ -290,9 +290,9 @@ [5] DisPciCfgCpuMstAbtRsp = 1, [1] SyncFloodOnUsPwDataErr = 1 */ - /* errata 346 - Fam10 C2 + /* errata 346 - Fam10 C2 -- FIXME at 25.6.2010 should apply to BL-C[23] too but I can't find their constants * System software should set F3x188[22] to 1b. */ - { 3, 0x188, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, + { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL, 0x00400000, 0x00400000 }, /* L3 Control Register */ Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Sun Aug 22 21:45:57 2010 (r5729) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Sun Aug 22 21:48:29 2010 (r5730) @@ -66,6 +66,7 @@ #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) #define AMD_DR_Dx (AMD_HY_D0) +#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )

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[commit] r5729 - in trunk/src: cpu/amd/model_10xxx northbridge/amd/amdmct
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:45:57 2010 New Revision: 5729 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5729 Log: Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc. While reviewing impact of this change it seems code for erratum 531 was not in sync with current docs. I have checked uses of AMD_FAM10_ALL, but I haven't looked up the docs for all of them, at first sight it seems ok to include all FAM10 revisions in this mask. Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010. Before it was applied also to DR-B0, DA-C3 or HY-D0 which are not affected according to current docs. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:41:47 2010 (r5728) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:45:57 2010 (r5729) @@ -136,27 +136,27 @@ * program Link Global Extended Control Register[ForceFullT0] * (F0x16C[15:13]) to 000b */ - { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */ + { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */ 0x00000000, 0x00000100 }, - { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x174, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x178, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x17C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x180, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x184, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x188, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x18C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, - { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000000, 0x00000100 }, /* Link Global Extended Control Register */ - { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL, + { 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, * Set T0Time 14h per BKDG */ Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Sun Aug 22 21:41:47 2010 (r5728) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Sun Aug 22 21:45:57 2010 (r5729) @@ -62,10 +62,11 @@ #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) #define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) #define AMD_DR_Dx (AMD_HY_D0) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) /*

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[PATCH] superiotool: Add suport for normal register dumping on ite8510E/TE/G
by Anders Juel Jensen 22 Aug '10

22 Aug '10

Add suport for normal register dumping on ite8510E/TE/G Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com> I am going to add support for --extra-dump when i grok the data sheet a little better.... Unless someone beats me to it ;-)

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[commit] r5728 - trunk/util/superiotool
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:41:47 2010 New Revision: 5728 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5728 Log: Add suport for normal register dumping on ite8510E/TE/G Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/ite.c Modified: trunk/util/superiotool/ite.c ============================================================================== --- trunk/util/superiotool/ite.c Sun Aug 22 21:40:58 2010 (r5727) +++ trunk/util/superiotool/ite.c Sun Aug 22 21:41:47 2010 (r5728) @@ -95,6 +95,66 @@ {0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}}, {EOT}}}, {0x8510, "IT8510E/TE/G", { + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x85,0x10, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x21,EOT}}, + {NOLDN, "Super I/O Control Reigster (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {NOLDN, "Super I/O Configuration Register (SIOIRQ)", + {0x25,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O General Purpose Register (SIOGP)", + {0x26,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O Power Mode Register (SIOPWR)", + {0x2d,EOT}, + {0x00,EOT}}, + {NOLDN, "Logical Device Activate Register (LDA)", + {0x30,EOT}, + {0x00,EOT}}, + {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", + {0x60,0x61,EOT}, + {NANA,NANA,EOT}}, + {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", + {0x62,0x63,EOT}, + {NANA,NANA,EOT}}, + {NOLDN, "Interupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", + {0x70,EOT}, + {NANA,EOT}}, + {NOLDN, "Interrupt Request Type Select (IRQTP)", + {0x71,EOT}, + {NANA,EOT}}, + {NOLDN, "DMA Channel Select 0 (DMAS0)", + {0x74,EOT}, + {0x04,EOT}}, + {NOLDN, "DMA Channel Select 1 (DMAS1)", + {0x75,EOT}, + {0x04,EOT}}, + {0x4, "System Wakup-Up (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x03,EOT}}, + {0x5, "Keyboard/Mouse", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0c,0x03,EOT}}, + {0x6, "Keyboard/Mouse", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x03,EOT}}, + {0xf, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x10, "Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,0x4a,EOT}}, + {0x11, "Power Management Interface Channel 1", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x03,EOT}}, + {0x12, "Power Management Interface Channel 2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, {EOT}}}, {0x8511, "IT8511E/TE/G", { {NOLDN, NULL,

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[commit] r5727 - trunk/util/superiotool
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:40:58 2010 New Revision: 5727 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5727 Log: Add another port to find ite8510 on. Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/superiotool.h Modified: trunk/util/superiotool/superiotool.h ============================================================================== --- trunk/util/superiotool/superiotool.h Sun Aug 22 21:40:11 2010 (r5726) +++ trunk/util/superiotool/superiotool.h Sun Aug 22 21:40:58 2010 (r5727) @@ -173,7 +173,7 @@ {probe_idregs_fintek, {0x2e, 0x4e, EOT}}, {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}}, /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ - {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, + {probe_idregs_ite, {0x25e, 0x2e, 0x4e, 0x370, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, /* I/O pairs on Nuvoton EC chips can be configured by firmware in * addition to the following hardware strapping options. */

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[commit] r5726 - trunk/util/superiotool
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:40:11 2010 New Revision: 5726 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5726 Log: Add support for non LDN register/device naming. Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/superiotool.c Modified: trunk/util/superiotool/superiotool.c ============================================================================== --- trunk/util/superiotool/superiotool.c Sun Aug 22 21:39:04 2010 (r5725) +++ trunk/util/superiotool/superiotool.c Sun Aug 22 21:40:11 2010 (r5726) @@ -105,7 +105,10 @@ printf(" (%s)", reg_table[i].ldn[j].name); regwrite(port, ldn_sel, reg_table[i].ldn[j].ldn); } else { - printf("Register dump:"); + if (reg_table[i].ldn[j].name == NULL) + printf("Register dump:"); + else + printf("(%s)", reg_table[i].ldn[j].name); } idx = reg_table[i].ldn[j].idx;

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[commit] r5725 - trunk/util/superiotool
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:39:04 2010 New Revision: 5725 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5725 Log: The LDFLAGS = -lz is needed to compile on slackware. Clubbering CFLAGS is never a good idea. Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/Makefile Modified: trunk/util/superiotool/Makefile ============================================================================== --- trunk/util/superiotool/Makefile Fri Aug 20 22:45:04 2010 (r5724) +++ trunk/util/superiotool/Makefile Sun Aug 22 21:39:04 2010 (r5725) @@ -29,8 +29,9 @@ SVNDEF := -D'SUPERIOTOOL_VERSION="$(shell svnversion -cn . \ | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' -CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ +CFLAGS += -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) +LDFLAGS += -lz OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o winbond.o

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Abit AX8 - Support
by mama fua 22 Aug '10

22 Aug '10

Hello, it's my first e-mail here on coreboot mailing list. I would like to ask if there is someone already working or interested on supporting the mainboard Abit AX8. It has these components: -Socket 939 -Northbridge K8T890 -Southbridge VT8237 -SuperIO Winbond W83627HF All already supported by coreboot. One thing that may cause problems is the device uGuru, that controls voltage memory and overclocking. So, as a student of computer engineering, I would like to help support this board, but I have no previous experience with BIOS or coreboot. It would be better if I found someone already working on the board and contribute with something I'm capable of. Anyone interested? Thanks in advance, Lucas.

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[PATCH] superiotool: Add another port to find ite8510 on.
by Anders Juel Jensen 22 Aug '10

22 Aug '10

Add another port to find ite8510 on. Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com>

1 0

[PATCH] superiotool: Add support for non LDN register/device naming.
by Anders Juel Jensen 22 Aug '10

22 Aug '10

Add support for non LDN register/device naming. Signed-off-by: Anders Juel Jensen <andersjjensen(a)gmail.com>

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coreboot August 2010