coreboot August 2010

coreboot@coreboot.org

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267 discussions

[PATCH] remove unused devicetree.cb entries
by Rudolf Marek 22 Aug '10

22 Aug '10

Hello Following patch removes unused ide0_enable and sata0_enable entries from SB7xx and SB600. Untested. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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[commit] r5717 - in trunk/src/superio/fintek: . f71863fg
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Tue Aug 17 17:05:05 2010 New Revision: 5717 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5717 Log: Support for Fintek F71863FG. This might need some work on the copyright notices. Getting it into the tree so people can get to it. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/superio/fintek/f71863fg/ - copied from r5716, trunk/src/superio/fintek/f71805f/ trunk/src/superio/fintek/f71863fg/f71863fg.h - copied, changed from r5716, trunk/src/superio/fintek/f71805f/f71805f.h trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c - copied, changed from r5716, trunk/src/superio/fintek/f71805f/f71805f_early_serial.c Deleted: trunk/src/superio/fintek/f71863fg/f71805f.h trunk/src/superio/fintek/f71863fg/f71805f_early_serial.c Modified: trunk/src/superio/fintek/Kconfig trunk/src/superio/fintek/Makefile.inc trunk/src/superio/fintek/f71863fg/Makefile.inc trunk/src/superio/fintek/f71863fg/chip.h trunk/src/superio/fintek/f71863fg/superio.c Modified: trunk/src/superio/fintek/Kconfig ============================================================================== --- trunk/src/superio/fintek/Kconfig Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/superio/fintek/Kconfig Tue Aug 17 17:05:05 2010 (r5717) @@ -1,2 +1,4 @@ config SUPERIO_FINTEK_F71805F bool +config SUPERIO_FINTEK_F71863FG + bool Modified: trunk/src/superio/fintek/Makefile.inc ============================================================================== --- trunk/src/superio/fintek/Makefile.inc Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/superio/fintek/Makefile.inc Tue Aug 17 17:05:05 2010 (r5717) @@ -1 +1,2 @@ subdirs-y += f71805f +subdirs-y += f71863fg Modified: trunk/src/superio/fintek/f71863fg/Makefile.inc ============================================================================== --- trunk/src/superio/fintek/f71805f/Makefile.inc Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/superio/fintek/f71863fg/Makefile.inc Tue Aug 17 17:05:05 2010 (r5717) @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> +## Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h -obj-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.o +obj-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.o + Modified: trunk/src/superio/fintek/f71863fg/chip.h ============================================================================== --- trunk/src/superio/fintek/f71805f/chip.h Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/superio/fintek/f71863fg/chip.h Tue Aug 17 17:05:05 2010 (r5717) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,8 +23,8 @@ /* This chip doesn't have keyboard and mouse support. */ -extern struct chip_operations superio_fintek_f71805f_ops; +extern struct chip_operations superio_fintek_f71863fg_ops; -struct superio_fintek_f71805f_config { +struct superio_fintek_f71863fg_config { struct uart8250 com1, com2; }; Copied and modified: trunk/src/superio/fintek/f71863fg/f71863fg.h (from r5716, trunk/src/superio/fintek/f71805f/f71805f.h) ============================================================================== --- trunk/src/superio/fintek/f71805f/f71805f.h Tue Aug 17 13:32:21 2010 (r5716, copy source) +++ trunk/src/superio/fintek/f71863fg/f71863fg.h Tue Aug 17 17:05:05 2010 (r5717) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,19 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Datasheet: - * - Name: F71805F/FG Super H/W Monitor + LPC IO - * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17 - * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf - * - Revision: V0.25P - */ - /* Logical Device Numbers (LDN). */ -#define F71805F_FDC 0x00 /* Floppy */ -#define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ -#define F71805F_PP 0x03 /* Parallel Port */ -#define F71805F_HWM 0x04 /* Hardware Monitor */ -#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71805F_PME 0x0a /* Power Management Events (PME) */ +#define F71863FG_FDC 0x00 /* Floppy */ +#define F71863FG_SP1 0x01 /* UART1 */ +#define F71863FG_SP2 0x02 /* UART2 */ +#define F71863FG_PP 0x03 /* Parallel Port */ +#define F71863FG_HWM 0x04 /* Hardware Monitor */ +#define F71863FG_KBC 0x05 /* KBC devices */ +#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71863FG_PME 0x0a /* Power Management Events (PME) */ Copied and modified: trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c (from r5716, trunk/src/superio/fintek/f71805f/f71805f_early_serial.c) ============================================================================== --- trunk/src/superio/fintek/f71805f/f71805f_early_serial.c Tue Aug 17 13:32:21 2010 (r5716, copy source) +++ trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c Tue Aug 17 17:05:05 2010 (r5717) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * Copyright (C) 2010 Wang Qing Pei<wangqingpei(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ +/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ #include <arch/romcc_io.h> -#include "f71805f.h" +#include "f71863fg.h" static inline void pnp_enter_conf_state(device_t dev) { @@ -35,7 +35,7 @@ outb(0xaa, port); } -static void f71805f_enable_serial(device_t dev, unsigned int iobase) +static void f71863fg_enable_serial(device_t dev, unsigned int iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/fintek/f71863fg/superio.c ============================================================================== --- trunk/src/superio/fintek/f71805f/superio.c Tue Aug 17 13:32:21 2010 (r5716) +++ trunk/src/superio/fintek/f71863fg/superio.c Tue Aug 17 17:05:05 2010 (r5717) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * Copyright (C) 2010 Wang Qing Pei<wangqingpei(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Datasheet: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf */ #include <arch/io.h> #include <device/device.h> @@ -27,7 +26,7 @@ #include <stdlib.h> #include <uart8250.h> #include "chip.h" -#include "f71805f.h" +#include "f71863fg.h" static void pnp_enter_conf_state(device_t dev) { @@ -39,9 +38,9 @@ outb(0xaa, dev->path.pnp.port); } -static void f71805f_init(device_t dev) +static void f71863fg_init(device_t dev) { - struct superio_fintek_f71805f_config *conf = dev->chip_info; + struct superio_fintek_f71863fg_config *conf = dev->chip_info; struct resource *res0; if (!dev->enabled) @@ -49,32 +48,32 @@ switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ - case F71805F_SP1: + case F71863FG_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case F71805F_SP2: + case F71863FG_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; } } -static void f71805f_pnp_set_resources(device_t dev) +static void f71863fg_pnp_set_resources(device_t dev) { pnp_enter_conf_state(dev); pnp_set_resources(dev); pnp_exit_conf_state(dev); } -static void f71805f_pnp_enable_resources(device_t dev) +static void f71863fg_pnp_enable_resources(device_t dev) { pnp_enter_conf_state(dev); pnp_enable_resources(dev); pnp_exit_conf_state(dev); } -static void f71805f_pnp_enable(device_t dev) +static void f71863fg_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -84,21 +83,21 @@ static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = f71805f_pnp_set_resources, - .enable_resources = f71805f_pnp_enable_resources, - .enable = f71805f_pnp_enable, - .init = f71805f_init, + .set_resources = f71863fg_pnp_set_resources, + .enable_resources = f71863fg_pnp_enable_resources, + .enable = f71863fg_pnp_enable, + .init = f71863fg_init, }; static struct pnp_info pnp_dev_info[] = { /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, - { &ops, F71805F_GPIO, PNP_IRQ0, }, - { &ops, F71805F_PME, }, + { &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F71863FG_GPIO, PNP_IRQ0, }, + { &ops, F71863FG_PME, }, }; static void enable_dev(device_t dev) @@ -106,7 +105,7 @@ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -struct chip_operations superio_fintek_f71805f_ops = { - CHIP_NAME("Fintek F71805F Super I/O") +struct chip_operations superio_fintek_f71863fg_ops = { + CHIP_NAME("Fintek F71863FG Super I/O") .enable_dev = enable_dev };

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[commit] r5737 - trunk/src/superio/fintek/f71863fg
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 22:02:27 2010 New Revision: 5737 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5737 Log: Fix up some copyrights Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/superio/fintek/f71863fg/chip.h trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c trunk/src/superio/fintek/f71863fg/superio.c Modified: trunk/src/superio/fintek/f71863fg/chip.h ============================================================================== --- trunk/src/superio/fintek/f71863fg/chip.h Sun Aug 22 22:00:42 2010 (r5736) +++ trunk/src/superio/fintek/f71863fg/chip.h Sun Aug 22 22:02:27 2010 (r5737) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Wang Qing Pei <wangqingpei(a)gmail.com> + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c ============================================================================== --- trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c Sun Aug 22 22:00:42 2010 (r5736) +++ trunk/src/superio/fintek/f71863fg/f71863fg_early_serial.c Sun Aug 22 22:02:27 2010 (r5737) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Wang Qing Pei<wangqingpei(a)gmail.com> + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: trunk/src/superio/fintek/f71863fg/superio.c ============================================================================== --- trunk/src/superio/fintek/f71863fg/superio.c Sun Aug 22 22:00:42 2010 (r5736) +++ trunk/src/superio/fintek/f71863fg/superio.c Sun Aug 22 22:02:27 2010 (r5737) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Wang Qing Pei<wangqingpei(a)gmail.com> + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by

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[PATCH] ht init and some errata for AMD fam 10 RB_C3
by xdrudis 22 Aug '10

22 Aug '10

Hi. This is the rest of patches to get until fidvid or staring ram stage, apparently at random. In fact once I've cleaned up the other patches a little I can't seem to make it stop at fidvid as it used to, but I guess with a dozen more tries it will... It's including RB-C3 in AMD_FAM10_ALL and adding some patches. It misses constants for new models that should also get some errata treatment. It applies to 5703 with patch.warnerror, patch.serial1, and patch procnames, together with the new m4a77td-pro dir I haven't sent. I know I should split it to smaller pieces, I just haven't had the time yet, and there's some overlap, so I must take care... Signed off by: Xavi Drudis Ferran <xdrudis(a)tinet.cat>

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[commit] r5736 - trunk/src/cpu/amd/model_10xxx
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 22:00:42 2010 New Revision: 5736 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5736 Log: I've checked Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 for errata 351 and it agrees with the comment on setting ForceFullT0= 000b but I believe the code didn't honor the comment. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:59:27 2010 (r5735) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 22:00:42 2010 (r5736) @@ -161,7 +161,7 @@ /* Link Global Extended Control Register */ { 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, - 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b, + 0x00000014, 0x0000E03F }, /* [15:13] ForceFullT0 = 0b, * Set T0Time 14h per BKDG */

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[commit] r5735 - trunk/src/cpu/amd/model_10xxx
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:59:27 2010 New Revision: 5735 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5735 Log: RB_C3 should also apply the workaround for errata 354, according to Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:56:47 2010 (r5734) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:59:27 2010 (r5735) @@ -361,44 +361,44 @@ { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - /* Errata 354 - Fam10 C2 + /* Errata 354 - Fam10 C2 - FIXME at 25.6.2010 affects RB-C2, BL-C2,DA-C2,RB-C3,BL-C3,DA-C3, but BL-C[23] have no constants * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */ - { 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x40, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x41, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x42, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x43, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x44, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x45, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x46, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x47, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x48, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x50, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x51, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x52, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x53, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x54, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x55, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x56, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x57, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, - { 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x58, AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, /* Errata 327 - Fam10 C2/D0

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[commit] r5734 - trunk/src/cpu/amd/model_10xxx
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:56:47 2010 New Revision: 5734 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5734 Log: RB_C3 and HY-D0 should also apply the workaround for errata 344, according to Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 My processor wasn't getting the workaround Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:54:26 2010 (r5733) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:56:47 2010 (r5734) @@ -321,9 +321,9 @@ u32 mask; } fam10_htphy_default[] = { - /* Errata 344 - Fam10 C2/D0 + /* Errata 344 - Fam10 C2/D0 -- FIXME at 25.6.2010 should be for ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */ - { 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, + { 0x60, AMD_DRBH_Cx , AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 }, { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x00000040, 0x00000040 },

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[commit] r5733 - in trunk/src/northbridge/amd/amdmct: mct_ddr3 wrappers
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:54:26 2010 New Revision: 5733 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5733 Log: documented workaround erratum 414, see Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 with patch.erratum414 it stops here (next patches don't make it get further, but they're needed according to documentation, don't break anything for me and I still don't have a solution for booting, so I'm keeping them there in case they fix something. testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffffd2e magic is 4f524243 Found CBFS header at fffffd2e Check fallback/romstage CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @ 0x20000 Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Sun Aug 22 21:51:34 2010 (r5732) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Sun Aug 22 21:54:26 2010 (r5733) @@ -118,6 +118,7 @@ #define TestFail 2 /* func 2, offset 40h-5C, bit 2*/ #define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/ #define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/ +#define PchgPDModeSel 23 /* func 2, offset 84h, bit 23 */ #define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/ #define InitDram 0 /* func 2, offset 90h, bit 0*/ #define BurstLength32 10 /* func 2, offset 90h, bit 10*/ @@ -128,6 +129,7 @@ #define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/ #define RDqsEn 12 /* func 2, offset 94h, bit 12*/ #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ +#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Sun Aug 22 21:51:34 2010 (r5732) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Sun Aug 22 21:54:26 2010 (r5733) @@ -415,6 +415,23 @@ wrmsr(NB_CFG_MSR, msr); } } + +static void vErratum414(struct DCTStatStruc *pDCTstat) +{ + int dct=0; + for(; dct < 2 ; dct++) + { + int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); + int powerDown = dRAMConfigHi && (1 << PowerDownEn ) ; + int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ; + int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); + int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ; + if (powerDown && ddr3 && pchgPDModeSel ) + { + Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); + } + } +} #endif @@ -425,6 +442,7 @@ if (pDCTstatA->LogicalCPUID & AMD_DRBH_Cx) { vErrata350(pMCTstat, pDCTstatA); vErratum372(pDCTstatA); + vErratum414(pDCTstatA); } #endif }

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[commit] r5732 - in trunk/src/northbridge/amd/amdmct: mct_ddr3 wrappers
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:51:34 2010 New Revision: 5732 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5732 Log: documented workaround erratum 372, see Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 with this one it stops here or earlier (as soon as before the patch, sometimes): *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Sun Aug 22 21:49:46 2010 (r5731) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Sun Aug 22 21:51:34 2010 (r5732) @@ -175,6 +175,7 @@ #define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */ #define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */ +#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */ /*============================================================================= SW Initialization ============================================================================*/ Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Sun Aug 22 21:49:46 2010 (r5731) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Sun Aug 22 21:51:34 2010 (r5732) @@ -400,14 +400,31 @@ coreDelay(); } + +static void vErratum372(struct DCTStatStruc *pDCTstat) +{ + msr_t msr = rdmsr(NB_CFG_MSR); + + int nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ; + + // is this the right way to check for NB pstate 1 or DDR3-1333 ? + if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) + &&(!pDCTstat->GangedMode)) { + /* DisableCf8ExtCfg */ + msr.hi &= ~(3 << (51 - 32)); + wrmsr(NB_CFG_MSR, msr); + } +} #endif static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ - if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2 | AMD_DA_C3)) { + /* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */ + if (pDCTstatA->LogicalCPUID & AMD_DRBH_Cx) { vErrata350(pMCTstat, pDCTstatA); + vErratum372(pDCTstatA); } #endif }

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[commit] r5731 - trunk/src/cpu/amd/model_10xxx
by repository service 22 Aug '10

22 Aug '10

Author: stepan Date: Sun Aug 22 21:49:46 2010 New Revision: 5731 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5731 Log: Complete code for errata 343. Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 says to set the register to 1 before CAR and to 0 after. We were setting it to 0 after CAR, but not to 1 before. Signed-off-by: Xavi Drudis Ferran <xdrudis(a)tinet.cat> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/defaults.h Modified: trunk/src/cpu/amd/model_10xxx/defaults.h ============================================================================== --- trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:48:29 2010 (r5730) +++ trunk/src/cpu/amd/model_10xxx/defaults.h Sun Aug 22 21:49:46 2010 (r5731) @@ -88,6 +88,10 @@ { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC, 0x00000000, 1 << (33-32), 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */ + + { BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL, + 0x00000000, 1 << (35-32), + 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram() ) */ };

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coreboot August 2010