Hi.
This is the rest of patches to get until fidvid or staring ram stage, apparently at random. In fact once I've cleaned up the other patches a little I can't seem to make it stop at fidvid as it used to, but I guess with a dozen more tries it will...
It's including RB-C3 in AMD_FAM10_ALL and adding some patches. It misses constants for new models that should also get some errata treatment.
It applies to 5703 with patch.warnerror, patch.serial1, and patch procnames, together with the new m4a77td-pro dir I haven't sent.
I know I should split it to smaller pieces, I just haven't had the time yet, and there's some overlap, so I must take care...
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
On Tue, Aug 17, 2010 at 08:44:10AM +0200, xdrudis wrote:
I know I should split it to smaller pieces, I just haven't had the time yet, and there's some overlap, so I must take care...
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
I splitted the original patch in 8 patches, and I'm now sending them one in each message. They all apply to the 5722 svn revisionwith the patch.serial1 patch attached (at least I tested thus, the patches should apply regardless).
There're some dependences between them. The order I have tried them is the one I'll send them to the list:
patch.rbc3infam10all patch.err351clearForceFullT0 patch.rbc3inErr346 patch.completeErr343 patch.erratum372 patch.erratum414 patch.rbc3inErr344 patch.rbc3inErr354
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
My smallest patch ever
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
On Thu, Aug 19, 2010 at 11:52:22PM +0200, xdrudis wrote:
My smallest patch ever
I've checked Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 for errata 351 and it agrees with the comment on setting ForceFullT0= 000b but I believe the code didn't honor the comment.
apply this after patch.rbc3infam10all
Index: src/cpu/amd/model_10xxx/defaults.h
--- src/cpu/amd/model_10xxx/defaults.h (revision 5719) +++ src/cpu/amd/model_10xxx/defaults.h (working copy) @@ -157,7 +157,7 @@
/* Link Global Extended Control Register */ { 0, 0x16C, AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
0x00000014, 0x0000E03F }, /* [15:13] ForceFullT0 = 0b, * Set T0Time 14h per BKDG */
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
Up to this patch, tests did the same as without the patches, hang after setAMDMSR , but still I think they are useful, since they get closer to documentation and don't make things worse.
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
with this one it stops here or earlier (as soon as before the patch, sometimes):
*** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region:
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
with patch.erratum414 it stops here (next patches don'tmake it get further, but they're needed according to documentation, don't break anything for me and I still don't have a solution for booting, so I'm keeping them there in case they fix something.
testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffffd2e magic is 4f524243 Found CBFS header at fffffd2e Check fallback/romstage CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @ 0x20000
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
My processor wasn't getting the workaround
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
Last one,
Signed off by: Xavi Drudis Ferran xdrudis@tinet.cat
-
Stefan Reinauer -
xdrudis