coreboot February 2010

coreboot@coreboot.org

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310 discussions

#129: Add support for high_tables_base for all chipsets that don't support it yet.
by coreboot 15 Apr '10

15 Apr '10

#129: Add support for high_tables_base for all chipsets that don't support it yet. ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: somebody Type: defect | Status: new Priority: critical | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Without tables in high memory, seabios won't run on your chipset properly. it overwrites your tables in the F segment, as seabios itself lives there. Also, once there is support for high_tables_base everywhere, the code in src/arch/i386/boot/tables.c can be cleaned up and simplified considerably. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/129> coreboot <http://www.coreboot.org/>

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#139: flashrom: -c option should be case insensitive
by coreboot 15 Apr '10

15 Apr '10

#139: flashrom: -c option should be case insensitive ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ flashrom's -c option requires you to enter extact chip names. It should probably be case insensitive for easier usage. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/139> coreboot <http://www.coreboot.org/>

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#148: Component defaults to adlo for new tickets in the tracker
by coreboot 15 Apr '10

15 Apr '10

#148: Component defaults to adlo for new tickets in the tracker ------------------------------------+--------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: wiki/website/tracker | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- Maybe coreboot would be better -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/148> coreboot <http://www.coreboot.org/>

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#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock
by coreboot 15 Apr '10

15 Apr '10

#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock -------------------------------------------+-------------------------------- Reporter: edwin_beasant@… | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -------------------------------------------+-------------------------------- The AMD DB800 board PLL strappings are left open as supplied, and leave the CPU/Memory in the sub-optimal 400MHz CPU,266MHz GLIU configuration. This requires a manual PLL strapping to achieve 500Mhz CPU and 400MHz GLIU as is normally used in the dev-kits (and the commercial GeodeRom). These are the correct (manual) strappings for a DB800: #define PLLMSRhi 0x000005DD #define PLLMSRlo 0x00DE60EE Patch attached. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/150> coreboot <http://www.coreboot.org/>

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#156: Add Layout File capability to v3 and LAR tool
by coreboot 15 Apr '10

15 Apr '10

#156: Add Layout File capability to v3 and LAR tool --------------------------------------------+------------------------------- Reporter: edwin_beasant@… | Owner: stepan@… Type: enhancement | Status: new Priority: major | Milestone: Component: coreboot | Keywords: flashrom lar layout image v3 Dependencies: | Patchstatus: patch needs review --------------------------------------------+------------------------------- This patch adds the ability to specify a layout file within the v3 Kconfig menu system, and then to enable LAR to read and setup a flash image with respect to this layout file. This operates by padding the blank space with '(padding)' images, using a similar method to the zero padding that LAR uses to finalise an image. I have also included the patch to optionally disable fallback booting: this speeds things up a bit on the DB800 board which seems to have RTC byte read/write issues somewhere... The layout file format is the same as current flashrom. It also allows addition/specification of the VSA within the Kconfig setup for Geode targets, which will then be added to the LAR in a sensible place. Example tested layout for 49LF008A device: 00000000:0003ffff fallback 00040000:0004ffff vsa 00050000:0008ffff normal 000f0000:000f0000 bootblock Note that the fallback image is 'below' the normal image: This allows for the fallback image to be 'golden': if you repeatedly flash the only the 'normal' area, you will always have a working accessible VSA and fallback image if the normal flash fails. This does not prevent you from flashing the fallback image (just ba cautious)... This has been tested as working on the Zoom DB800 development platform. Comments and review please! -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/156> coreboot <http://www.coreboot.org/>

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#157: utils/inteltool has outdated pciutils check in Makefile
by coreboot 15 Apr '10

15 Apr '10

#157: utils/inteltool has outdated pciutils check in Makefile --------------------------+------------------------------------------------- Reporter: anonymous | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: misc | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- The current test compile bails out with: undefined reference to `pci_alloc' If i simply remove the test inteltool compiles and runs as expected. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/157> coreboot <http://www.coreboot.org/>

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#103: flashrom: Don't exit() after successful erase operation
by coreboot 12 Apr '10

12 Apr '10

#103: flashrom: Don't exit() after successful erase operation ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase exit | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103> coreboot <http://www.coreboot.org/>

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#119: Winbond W39V040FBPZ is not written correctly by flashrom
by coreboot 12 Apr '10

12 Apr '10

#119: Winbond W39V040FBPZ is not written correctly by flashrom -----------------------------------------+---------------------------------- Reporter: charles.herndon@… | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: W39V040FBPZ | Dependencies: Patchstatus: there is no patch | -----------------------------------------+---------------------------------- Flash device is detected as a Winbond W39V040B device. Flashrom attempts to flash device, but verification fails. No actual writing to the chip appears to be done. Tried changing write and erase in flashchips.c to: jedec, winbond_fwhub and 49lfxxxc. ./flashrom -wv xxxx.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found chip "Winbond W39V040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 Verifying flash... FAILED! Expected=0xc7, Read=0x49 -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/119> coreboot <http://www.coreboot.org/>

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Supermicro H8QME-2+ mct_d fatal exit.
by Knut Kujat 12 Mar '10

12 Mar '10

Hi, I've got this ugly mct_d fatal exit error again on one of my H8QME-2+ boards. Even every single board is absolutely identical 4 Opterons 16G Ram, etc... there are several boards booting and working without any problem with coreboot and others don't even start and mct_d fatal exit :(. Has someone an idea what the problem could be ? Thanks any comment would be appreciated. Knut Kujat

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[PATCH]: Disable ExtINT in ioapic.c
by Bao, Zheng 09 Mar '10

09 Mar '10

If ExtINT is enabled, my board will hang when linux boots. log: ....... Checking if this processor honours the WP bit even in supervisor mode...Ok. SLUB: Genslabs=13, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Hierarchical RCU implementation. NR_IRQS:512 Console: colour dummy device 80x25 console [ttyS0] enabled spurious APIC interrupt on CPU#0, should never happen. Fast TSC calibration using PIT Detected 2100.411 MHz processor. Calibrating delay loop (skipped), value calculated using timer frequency.. 4200.82 BogoMIPS (lpj=2100411) Mount-cache hash table entries: 512 Initializing cgroup subsys ns Initializing cgroup subsys cpuacct Initializing cgroup subsys freezer CPU: Physical Processor ID: 0 CPU: Processor Core ID: 0 mce: CPU supports 5 MCE banks using C1E aware idle routine Performance Events: AMD PMU driver. ... version: 0 ... bit width: 48 ... generic registers: 4 ... value mask: 0000ffffffffffff ... max period: 00007fffffffffff ... fixed-purpose events: 0 ... event mask: 000000000000000f Checking 'hlt' instruction... end of log. I believe the ExtINT don't have to be enable in BIOS stage. It will be done when the kernel boots. Plus, it is the way my proprietary BIOS does. It is tested on dbm690t. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/arch/i386/smp/ioapic.c =================================================================== --- src/arch/i386/smp/ioapic.c (revision 5073) +++ src/arch/i386/smp/ioapic.c (working copy) @@ -110,7 +110,7 @@ #endif /* Enable Virtual Wire Mode */ - low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + low = DISABLED; high = bsp_lapicid << (56 - 32); io_apic_write(ioapic_base, 0x10, low);

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coreboot February 2010