coreboot December 2010

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mcp55_fadt patch to fix Microsoft Windows BSOD 0x000000A5 (0x00000011, 0x00000006 ....)
by David Robinson 10 Dec '10

10 Dec '10

Hi, The attached patch fixes a problem preventing Windows XP / 7 from booting with bug check error A5 (0x00000011, 0x00000006) on the Gigabyte GA-M57SLI- S4 board. Microsoft documentation states that this bug check occurs because, "SCI_EN never becomes set in PM1 Control Register". This patch sets the SCI_EN bit. The patch applies to any board featuring the MCP55 south bridge. Signed-off-by: David Robinson <drobinson(a)bluechiptechnology.co.uk> Blue Chip Technology Limited. Chowley Oak Lane, Tattenhall, Chester, Cheshire CH3 9EX Tel: 01829 772000 Registered in England 3110403 Vat No: GB 618 374134

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[commit] r6160 - in trunk/src/mainboard: getac/p470 nvidia/l1_2pvv
by repository service 10 Dec '10

10 Dec '10

Author: uwe Date: Fri Dec 10 13:52:50 2010 New Revision: 6160 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6160 Log: Two hda_verb.h files: Add more comments. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/getac/p470/hda_verb.h trunk/src/mainboard/nvidia/l1_2pvv/hda_verb.h Modified: trunk/src/mainboard/getac/p470/hda_verb.h ============================================================================== --- trunk/src/mainboard/getac/p470/hda_verb.h Fri Dec 10 10:02:50 2010 (r6159) +++ trunk/src/mainboard/getac/p470/hda_verb.h Fri Dec 10 13:52:50 2010 (r6160) @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,17 +14,16 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0262, // Codec Vendor ID / Device ID + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 0x10714700, // Subsystem ID 0x0000000d, // Number of jacks - /* HDA Codec Subsystem ID Verb Table: 0x10ec0000 */ + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0000 */ 0x00172000, 0x00172100, 0x001722EC, @@ -33,68 +31,79 @@ /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x12) */ + /* Pin Complex (NID 0x12), DMIC */ 0x01271CF0, 0x01271D11, 0x01271E11, 0x01271F41, - /* Pin Complex (NID 0x14) */ + + /* Pin Complex (NID 0x14), LINE_OUT (port D) */ 0x01471C10, 0x01471D01, 0x01471E13, 0x01471F99, - /* Pin Complex (NID 0x15) */ + + /* Pin Complex (NID 0x15), HP_OUT (port A) */ 0x01571C20, 0x01571D40, 0x01571E21, 0x01571F01, - /* Pin Complex (NID 0x16) */ + + /* Pin Complex (NID 0x16), MONO-OUT */ 0x01671CF0, 0x01671D11, 0x01671E11, 0x01671F41, - /* Pin Complex (NID 0x18) */ + + /* Pin Complex (NID 0x18), MIC1 (port B) */ 0x01871C30, 0x01871D98, 0x01871EA1, 0x01871F01, - /* Pin Complex (NID 0x19) */ + + /* Pin Complex (NID 0x19), MIC2 (port F) */ 0x01971C31, 0x01971D09, 0x01971EA3, 0x01971F99, - /* Pin Complex (NID 0x1A) */ + + /* Pin Complex (NID 0x1A), LINE1 (port C) */ 0x01A71C3F, 0x01A71D98, 0x01A71EA1, 0x01A71F02, - /* Pin Complex (NID 0x1B) */ + + /* Pin Complex (NID 0x1B), LINE2 (port E) */ 0x01B71C1F, 0x01B71D40, 0x01B71E21, 0x01B71F02, - /* Pin Complex (NID 0x1C) */ + + /* Pin Complex (NID 0x1C), CD_IN */ 0x01C71CF0, 0x01C71D11, 0x01C71E11, 0x01C71F41, - /* Pin Complex (NID 0x1D) */ + + /* Pin Complex (NID 0x1D), PCBEEP */ 0x01D71CF0, 0x01D71D11, 0x01D71E11, 0x01D71F41, - /* Pin Complex (NID 0x1E) */ + + /* Pin Complex (NID 0x1E), S/PDIF-OUT */ 0x01E71CF0, 0x01E71D11, 0x01E71E11, 0x01E71F41, - /* Pin Complex (NID 0x1F) */ + + /* Pin Complex (NID 0x1F), S/PDIF-IN */ 0x01F71CF0, 0x01F71D11, 0x01F71E11, 0x01F71F41, }; -extern const u32 * cim_verb_data; +extern const u32 *cim_verb_data; extern u32 cim_verb_data_size; Modified: trunk/src/mainboard/nvidia/l1_2pvv/hda_verb.h ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/hda_verb.h Fri Dec 10 10:02:50 2010 (r6159) +++ trunk/src/mainboard/nvidia/l1_2pvv/hda_verb.h Fri Dec 10 13:52:50 2010 (r6160) @@ -7,8 +7,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,83 +16,94 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor ID / Device ID + 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks - /* HDA Codec Subsystem ID Verb Table: 0x0000e601 */ + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ 0x00172001, 0x001721e6, 0x00172200, 0x00172300, + /* NID 0x14, FRONT-OUT-L/R */ 0x01471c10, 0x01471d44, 0x01471e01, 0x01471f01, - // 1 + + /* NID 0x15, SURR-OUT-L/R */ 0x01571c12, 0x01571d14, 0x01571e01, 0x01571f01, - // 2 + + /* NID 0x16, CEN/LFE-OUT */ 0x01671c11, 0x01671d60, 0x01671e01, 0x01671f01, - // 3 + + /* NID 0x17, SIDE-SURR-L/R */ 0x01771c14, 0x01771d20, 0x01771e01, 0x01771f01, - // 4 + + /* NID 0x18, MIC1-L/R, VREFO */ 0x01871c30, 0x01871d9c, 0x01871ea1, 0x01871f01, - // 5 + + /* NID 0x19, MIC2-L/R, VREFO */ 0x01971c40, 0x01971d9c, 0x01971ea1, 0x01971f02, - // 6 + + /* NID 0x1a, LINE1-L/R, VREFO */ 0x01a71c31, 0x01a71d34, 0x01a71e81, 0x01a71f01, - // 7 + + /* NID 0x1b, LINE2-L/R, VREFO */ 0x01b71c1f, 0x01b71d44, 0x01b71e21, 0x01b71f02, - // 8 + + /* NID 0x1c, CD-L/R / GND */ 0x01c71cf0, 0x01c71d11, 0x01c71e11, 0x01c71f41, - // 9 + + /* NID 0x1d, PCBEEP */ 0x01d71c3e, 0x01d71d01, 0x01d71e83, 0x01d71f99, - // 10 + + /* NID 0x1e, S/PDIF-OUT */ 0x01e71c20, 0x01e71d41, 0x01e71e45, 0x01e71f01, - // 11 + + /* NID 0x1f, S/PDIF-IN */ 0x01f71c50, 0x01f71d91, 0x01f71ec5, 0x01f71f01, }; -extern u32 * cim_verb_data; +extern u32 *cim_verb_data; extern u32 cim_verb_data_size;

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[PATCH] Deduplicate various ACPI .asl files
by Uwe Hermann 10 Dec '10

10 Dec '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[PATCH] Add TINY_BOOTBLOCK support for AMD SB700
by Uwe Hermann 10 Dec '10

10 Dec '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r6159 - in trunk/src: mainboard/amd/mahogany_fam10 mainboard/amd/tilapia_fam10 mainboard/asus/m4a78-em mainboard/asus/m4a785-m mainboard/gigabyte/ma785gmt mainboard/gigabyte/ma78gm mainboa...
by repository service 10 Dec '10

10 Dec '10

Author: uwe Date: Fri Dec 10 10:02:50 2010 New Revision: 6159 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6159 Log: Add TINY_BOOTBLOCK support for AMD SB700. Factor out the ROM decode enable functionality into bootblock.c and handle it via the usual TINY_BOOTBLOCK mechanism. Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/southbridge/amd/sb700/bootblock.c Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig trunk/src/mainboard/amd/tilapia_fam10/Kconfig trunk/src/mainboard/asus/m4a78-em/Kconfig trunk/src/mainboard/asus/m4a785-m/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/Kconfig trunk/src/mainboard/gigabyte/ma78gm/Kconfig trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig trunk/src/mainboard/jetway/pa78vm5/Kconfig trunk/src/southbridge/amd/sb700/Kconfig trunk/src/southbridge/amd/sb700/early_setup.c Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -25,7 +25,6 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -25,7 +25,6 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a78-em/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/asus/m4a78-em/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -23,7 +23,6 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/asus/m4a785-m/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -24,7 +24,6 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -24,7 +24,6 @@ select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -24,7 +24,6 @@ select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -25,7 +25,6 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select QRANK_DIMM_SUPPORT Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/mainboard/jetway/pa78vm5/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -25,7 +25,6 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID - select TINY_BOOTBLOCK select GFXUMA select QRANK_DIMM_SUPPORT Modified: trunk/src/southbridge/amd/sb700/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb700/Kconfig Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/southbridge/amd/sb700/Kconfig Fri Dec 10 10:02:50 2010 (r6159) @@ -21,6 +21,7 @@ bool select IOAPIC select HAVE_USBDEBUG + select TINY_BOOTBLOCK config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool Added: trunk/src/southbridge/amd/sb700/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sb700/bootblock.c Fri Dec 10 10:02:50 2010 (r6159) @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* + * Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The SB700 power-on default is to map 256K ROM space. + * + * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00, + * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. + */ +static void sb700_enable_rom(void) +{ + u8 reg8; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB700_LPC), 0); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + */ + pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */ + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(dev, 0x6e, 0xffff); +} + +static void bootblock_southbridge_init(void) +{ + sb700_enable_rom(); +} Modified: trunk/src/southbridge/amd/sb700/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/early_setup.c Thu Dec 9 19:09:14 2010 (r6158) +++ trunk/src/southbridge/amd/sb700/early_setup.c Fri Dec 10 10:02:50 2010 (r6159) @@ -92,7 +92,6 @@ * Serial port 0 * KBC Port * ACPI Micro-controller port -* LPC ROM size * This function does not change port 0x80 decoding. * Console output through any port besides 0x3f8 is unsupported. * If you use FWH ROMs, you have to setup IDSEL. @@ -134,27 +133,13 @@ reg8 |= 1 << 0; pci_write_config8(dev, 0xbb, reg8); - /* SuperIO, LPC ROM */ + /* Super I/O, RTC */ reg8 = pci_read_config8(dev, 0x48); /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ reg8 |= (1 << 1) | (1 << 0); - /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */ - reg8 |= (1 << 3) | (1 << 4); /* Decode port 0x70-0x73 (RTC) */ - reg8 |= 1 << 6; + reg8 |= (1 << 6); pci_write_config8(dev, 0x48, reg8); - - /* hardware should enable LPC ROM by pin straps */ - /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */ - /* See detail in 43366_sb700_bdg_nda_1.01.pdf page 17. */ - /* enable LPC ROM range mirroring start 0x000e(0000) */ - pci_write_config16(dev, 0x68, 0x000e); - /* enable LPC ROM range mirroring end 0x000f(ffff) */ - pci_write_config16(dev, 0x6a, 0x000f); - /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB */ - pci_write_config16(dev, 0x6c, 0xfff0); - /* enable LPC ROM range end at 0xffff(ffff) */ - pci_write_config16(dev, 0x6e, 0xffff); } /* what is its usage? */ @@ -403,13 +388,12 @@ pci_write_config8(dev, 0x46, 0xC3); pci_write_config8(dev, 0x47, 0xFF); + // TODO: This has already been done(?) /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), - * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). - * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/ + * Alternate Super I/O Configuration Port (4e/4f), Wide Generic IO Port (64/65). */ byte = pci_read_config8(dev, 0x48); byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */ byte |= 1 << 6; /* enable for RTC I/O range */ pci_write_config8(dev, 0x48, byte); pci_write_config8(dev, 0x49, 0xFF); @@ -418,12 +402,6 @@ byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ pci_write_config8(dev, 0x4A, byte); - /* Set LPC ROM size, it has been done in sb700_lpc_init(). - * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; - * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB - * pci_write_config16(dev, 0x68, 0x000e) - * pci_write_config16(dev, 0x6c, 0xfff0);*/ - /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_write_config8(dev, 0x7C, 0x05);

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Re: [coreboot] Buying a new mainboard. Which vendors support coreboot?
by Niklas Cholmkvist 10 Dec '10

10 Dec '10

Hi again,. Jonathan wrote: > What makes you think the open source ATI drivers aren't > any good? I'm not saying they are not good. If I didn't have an appreciation for free libre or open source software I would have another idea of what 'good' means for me. What bothers me(although I'm not sure if you understand why) though is some graphics microcode that AMD or ATI doesn't want to release, possibly because it will spoil some Digital Rights Management(DRM) technology that they have. Maybe I am mistaken and they have released some of the "microcode" for some of their integrated graphics cards?(if you know please tell) I don't know if you consider "secret microcode" an issue. Also I just read about that this "microcode" has not been released and I found the reference on an AMD/ATI forum. I'm not 100% that Intel has released the "microcode" for their G43 chipset. So you can supply arguments(if you wish to help me with this) that microcode isn't an important issue or find a reference that Intel doesn't release their G43 graphics "microcode" either. > AFAICT they're doing pretty well these days. Any specific card? If yes, compare it to integrated Intel GMA G43("X4500") Regards, Niklas --

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[PATCH] FILO: added support for Linux boot protocol v2.10
by Mathias Krause 10 Dec '10

10 Dec '10

Hello list, the current version of FILO is only aware of the Linux boot protocol up to the version 2.03. This makes it impossible to, e.g., load newer kernels compiled with CONFIG_RELOCATABLE=y because they require the boot loader to at least support version 2.05 of the Linux boot loader protocol. Otherwise the kernel will just panic while trying to uncompress (because it thinks the load address is NULL). The attached patch fixes this problem by enhancing the current implementation to cover the newer protocol versions and respect the new members, specifically "relocatable_kernel" and "kernel_alignment". Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com>

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[FILO] r139 - trunk/filo/i386
by repository service 10 Dec '10

10 Dec '10

Author: stuge Date: Fri Dec 10 05:09:57 2010 New Revision: 139 URL: http://tracker.coreboot.org/trac/filo/changeset/139 Log: Support Linux boot protocol v2.10 The current version of FILO is only aware of the Linux boot protocol up to the version 2.03. This makes it impossible to, e.g., load newer kernels compiled with CONFIG_RELOCATABLE=y because they require the boot loader to at least support version 2.05 of the Linux boot loader protocol. Otherwise the kernel will just panic while trying to uncompress (because it thinks the load address is NULL). The attached patch fixes this problem by enhancing the current implementation to cover the newer protocol versions and respect the new members, specifically "relocatable_kernel" and "kernel_alignment". Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/filo/i386/linux_load.c Modified: trunk/filo/i386/linux_load.c ============================================================================== --- trunk/filo/i386/linux_load.c Tue Aug 31 22:26:34 2010 (r138) +++ trunk/filo/i386/linux_load.c Fri Dec 10 05:09:57 2010 (r139) @@ -57,7 +57,8 @@ u8 reserved1[0x1f1]; /* 0x000 */ u8 setup_sects; /* 0x1f1 */ u16 root_flags; /* 0x1f2 */ - u8 reserved2[6]; /* 0x1f4 */ + u32 syssize; /* 0x1f4 (2.04+) */ + u8 reserved2[2]; /* 0x1f8 */ u16 vid_mode; /* 0x1fa */ u16 root_dev; /* 0x1fc */ u16 boot_sector_magic; /* 0x1fe */ @@ -82,6 +83,24 @@ u32 cmd_line_ptr; /* 0x228 */ /* 2.03+ */ u32 initrd_addr_max; /* 0x22c */ + /* 2.05+ */ + u32 kernel_alignment; /* 0x230 */ + u8 relocatable_kernel; /* 0x234 */ + u8 min_alignment; /* 0x235 (2.10+) */ + u8 reserved6[2]; /* 0x236 */ + /* 2.06+ */ + u32 cmdline_size; /* 0x238 */ + /* 2.07+ */ + u32 hardware_subarch; /* 0x23c */ + u64 hardware_subarch_data;/* 0x240 */ + /* 2.08+ */ + u32 payload_offset; /* 0x248 */ + u32 payload_length; /* 0x24c */ + /* 2.09+ */ + u64 setup_data; /* 0x250 */ + /* 2.10+ */ + u64 pref_address; /* 0x258 */ + u32 init_size; /* 0x260 */ } __attribute__ ((packed)); /* Paramters passed to 32-bit part of Linux @@ -160,7 +179,10 @@ u32 initrd_size; /* 0x21c */ u8 reserved12_5[8]; /* 0x220 */ u32 cmd_line_ptr; /* 0x228 */ - u8 reserved13[164]; /* 0x22c */ + u32 initrd_addr_max; /* 0x22c */ + u32 kernel_alignment; /* 0x230 */ + u8 relocatable_kernel; /* 0x234 */ + u8 reserved13[155]; /* 0x22c */ struct e820entry e820_map[E820MAX]; /* 0x2d0 */ u8 reserved16[688]; /* 0x550 */ #define COMMAND_LINE_SIZE 256 @@ -176,8 +198,8 @@ /* Load the first part the file and check if it's Linux */ static u32 load_linux_header(struct linux_header *hdr) { + u32 kern_addr = 0; int load_high; - u32 kern_addr; if (file_read(hdr, sizeof *hdr) != sizeof *hdr) { printf("Can't read Linux header\n"); @@ -221,12 +243,28 @@ debug(" (loadflags %#x)", hdr->loadflags); load_high = hdr->loadflags & 1; } + + /* determine kernel load address */ + if (hdr->protocol_version >= 0x20a) { + if (hdr->pref_address >> 32) { + debug(" (ignoring 64bit pref_address)"); + } else { + kern_addr = hdr->pref_address; + } + } + + if (hdr->protocol_version >= 0x205 && hdr->relocatable_kernel) { + printf(" relocatable"); + } + if (load_high) { printf(" bzImage"); - kern_addr = 0x100000; + if (kern_addr == 0) + kern_addr = 0x100000; } else { printf(" zImage or Image"); - kern_addr = 0x1000; + if (kern_addr == 0) + kern_addr = 0x1000; } printf(".\n"); @@ -257,6 +295,12 @@ params->orig_video_points = 16; params->loader_type = 0xff; /* Unregistered Linux loader */ + + /* copy alignment fields for relocatable kernels */ + if (hdr->protocol_version >= 0x205) { + params->relocatable_kernel = hdr->relocatable_kernel; + params->kernel_alignment = hdr->kernel_alignment; + } } /* Memory map */ @@ -676,6 +720,9 @@ /* Entry point */ ctx->eip = kern_addr; + /* set this field in any case to support relocatable kernels */ + params->kernel_start = kern_addr; + debug("EIP=%#x\n", kern_addr); printf("Jumping to entry point...\n");

1 0

SerialICE
by Jonas Bülow 10 Dec '10

10 Dec '10

Hi, SerialICE sounds interesting. Is the project still alive? Regards, Jonas

3 2

[commit] r6158 - in trunk/src/southbridge: amd/amd8111 amd/sb600 broadcom/bcm5785 intel/i82371eb nvidia/ck804 nvidia/mcp55
by repository service 09 Dec '10

09 Dec '10

Author: uwe Date: Thu Dec 9 19:09:14 2010 New Revision: 6158 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6158 Log: Merge enable_rom.c files into bootblock.c files. All southbridges using TINY_BOOTBLOCK have a bootblock.c files which simply includes an enable_rom.c files. As discussed on the mailing list, drop the enable_rom.c file by merging it into bootblock.c. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/southbridge/amd/amd8111/enable_rom.c trunk/src/southbridge/amd/sb600/enable_rom.c trunk/src/southbridge/broadcom/bcm5785/enable_rom.c trunk/src/southbridge/intel/i82371eb/enable_rom.c trunk/src/southbridge/nvidia/ck804/enable_rom.c trunk/src/southbridge/nvidia/mcp55/enable_rom.c Modified: trunk/src/southbridge/amd/amd8111/bootblock.c trunk/src/southbridge/amd/sb600/bootblock.c trunk/src/southbridge/broadcom/bcm5785/bootblock.c trunk/src/southbridge/intel/i82371eb/bootblock.c trunk/src/southbridge/nvidia/ck804/bootblock.c trunk/src/southbridge/nvidia/mcp55/bootblock.c Modified: trunk/src/southbridge/amd/amd8111/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/bootblock.c Thu Dec 9 14:10:57 2010 (r6157) +++ trunk/src/southbridge/amd/amd8111/bootblock.c Thu Dec 9 19:09:14 2010 (r6158) @@ -1,4 +1,45 @@ -#include "southbridge/amd/amd8111/enable_rom.c" +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ +static void amd8111_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8111_ISA), 0); + + /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ + + /* Set the 5MB enable bits. */ + byte = pci_io_read_config8(dev, 0x43); + byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ + byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ + pci_io_write_config8(dev, 0x43, byte); +} static void bootblock_southbridge_init(void) { Modified: trunk/src/southbridge/amd/sb600/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/sb600/bootblock.c Thu Dec 9 14:10:57 2010 (r6157) +++ trunk/src/southbridge/amd/sb600/bootblock.c Thu Dec 9 19:09:14 2010 (r6158) @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -18,7 +17,52 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/amd/sb600/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The SB600 power-on default is to map 256K ROM space. + * + * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. + */ +static void sb600_enable_rom(void) +{ + u8 reg8; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB600_LPC), 0); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(dev, 0x6e, 0xffff); +} static void bootblock_southbridge_init(void) { Modified: trunk/src/southbridge/broadcom/bcm5785/bootblock.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bootblock.c Thu Dec 9 14:10:57 2010 (r6157) +++ trunk/src/southbridge/broadcom/bcm5785/bootblock.c Thu Dec 9 19:09:14 2010 (r6158) @@ -18,7 +18,25 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ +static void bcm5785_enable_rom(void) +{ + u8 byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, + PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); + + /* Set the 4MB enable bits. */ + byte = pci_read_config8(dev, 0x41); + byte |= 0x0e; + pci_write_config8(dev, 0x41, byte); +} static void bootblock_southbridge_init(void) { Modified: trunk/src/southbridge/intel/i82371eb/bootblock.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/bootblock.c Thu Dec 9 14:10:57 2010 (r6157) +++ trunk/src/southbridge/intel/i82371eb/bootblock.c Thu Dec 9 19:09:14 2010 (r6158) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +18,35 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/intel/i82371eb/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> +#include "i82371eb.h" + +static void i82371eb_enable_rom(void) +{ + u16 reg16; + device_t dev; + + /* + * Note: The Intel 82371AB/EB/MB ISA device can be on different + * PCI bus:device.function locations on different boards. + * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0. + * But scanning for the PCI IDs (instead of hardcoding + * bus/device/function numbers) works on all boards. + */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); + + /* Enable access to the whole ROM, disable ROM write access. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= LOWER_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ + pci_write_config16(dev, XBCS, reg16); +} static void bootblock_southbridge_init(void) { Modified: trunk/src/southbridge/nvidia/ck804/bootblock.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/bootblock.c Thu Dec 9 14:10:57 2010 (r6157) +++ trunk/src/southbridge/nvidia/ck804/bootblock.c Thu Dec 9 19:09:14 2010 (r6158) @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Jonathan Kollasch <jakllsch(a)kollasch.net> + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +21,26 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#include "southbridge/nvidia/ck804/enable_rom.c" +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +static void ck804_enable_rom(void) +{ + unsigned char byte; + device_t addr; + + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ + /* Locate the ck804 LPC. */ + addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); + + /* Set the 4MB enable bit. */ + byte = pci_read_config8(addr, 0x88); + byte |= 0x80; + pci_write_config8(addr, 0x88, byte); +} static void bootblock_southbridge_init(void) { Modified: trunk/src/southbridge/nvidia/mcp55/bootblock.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/bootblock.c Thu Dec 9 14:10:57 2010 (r6157) +++ trunk/src/southbridge/nvidia/mcp55/bootblock.c Thu Dec 9 19:09:14 2010 (r6158) @@ -1,7 +1,10 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +21,37 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "southbridge/nvidia/mcp55/enable_rom.c" +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "mcp55.h" + +static void mcp55_enable_rom(void) +{ + uint8_t byte; + uint16_t word; + device_t addr; + + /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ +#if 0 + /* default MCP55 LPC single */ + addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); +#else +// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0); +#endif + + /* Set the 4MB enable bit bit */ + byte = pci_read_config8(addr, 0x88); + byte |= 0xff; //256K + pci_write_config8(addr, 0x88, byte); + byte = pci_read_config8(addr, 0x8c); + byte |= 0xff; //1M + pci_write_config8(addr, 0x8c, byte); + word = pci_read_config16(addr, 0x90); + word |= 0x7fff; //15M + pci_write_config16(addr, 0x90, word); +} static void bootblock_southbridge_init(void) {

4 3

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coreboot December 2010