coreboot December 2010

coreboot@coreboot.org

52 participants
262 discussions

S3(Suspend to RAM) on board ASUS M2V_MX -SE
by Fengwei Zhang 05 Dec '10

05 Dec '10

Hi all, From previous emails, I have learned that S3 works at ASUS M2V_MX_SE after patching by Rudolf. However,I was trying to test S3 on board Asus M2V_MX_SE, and I have following situation, which I don't quite understand. Testing S3 on my board M2V_MX_SE: m2v_mx_se + coreboot: after suspend to ram, it cannot wake up(no GUI on monitor) m2v_mx_se + external video card + manufacture BIOS: S3 works m2v_mx_se + manufacture BIOS: S3 doesn't work m2v_mx_se + external video card + coreboot: for Ubunut 10.4, I got kernel panic error; for CentOS 5.5, I got ACPI system tables error. I would appreciate if someone could give me some suggestions. Best, Fengwei

3 5

[commit] r6139 - trunk/util/acpi
by repository service 04 Dec '10

04 Dec '10

Author: stepan Date: Sat Dec 4 21:50:39 2010 New Revision: 6139 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6139 Log: ACPI table dumping wrapper script Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Added: trunk/util/acpi/ trunk/util/acpi/acpidump-all (contents, props changed) Added: trunk/util/acpi/acpidump-all ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/acpi/acpidump-all Sat Dec 4 21:50:39 2010 (r6139) @@ -0,0 +1,50 @@ +#!/bin/bash +# +# Copyright (C) 2007-2010 by coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA +# + +rm -rf out +mkdir out + +# walk through all ACPI tables with their addresses +# example: +# RSDT @ 0xcf6794ba +# we can not just dump the tables by their names because some +# machines have double ACPI tables + +acpidump | grep "@ 0x" | while read line +do + NAME=$( echo `echo $line|cut -f1 -d@` ) + FNAME=$( echo $NAME | sed s/\ /_/g |sed s/\!/b/g ) + ADDR=$( echo `echo $line|cut -f2 -d@` ) + if [ "${!FNAME}" == "" ]; then + eval $FNAME=0 + else + eval $FNAME=$(( ${!FNAME} + 1 )) + fi + printf "Processing table \"$NAME\" at $ADDR ... " + printf "${!FNAME} tables of that kind found before.\n" + + # acpidump -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.txt + acpidump -b -s ${!FNAME} --table "$NAME" > out/$FNAME-$ADDR-${!FNAME}.bin + if [ "`file -b out/$FNAME-$ADDR-${!FNAME}.bin`" != "ASCII text" ]; then + iasl -d out/$FNAME-$ADDR-${!FNAME}.bin &>/dev/null + else + printf "Skipping $NAME because it was not dumped correctly.\n\n" + fi + +done +

1 0

[patch] update crossgcc
by Marc Jones 04 Dec '10

04 Dec '10

Update coreboot crossgcc toolchain, GDB 4.5.1, MPFR 3.0.0, GDB 7.2. Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin. Add GDB patch to handle #pragma pack in the i386-elf gcc target. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Tested on IEI Kino Fam10 mainboard. Can someone test that this works on some other mainboards, maybe Intel or Via based? Marc -- http://se-eng.com

7 9

[PATCH] 939a785gmh ACPI diet
by Rudolf Marek 04 Dec '10

04 Dec '10

Hello, Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

2 2

[commit] r6138 - in trunk/src/mainboard/asrock/939a785gmh: . acpi
by repository service 04 Dec '10

04 Dec '10

Author: ruik Date: Sat Dec 4 11:08:55 2010 New Revision: 6138 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6138 Log: Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl Fri Dec 3 01:45:56 2010 (r6137) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl Sat Dec 4 11:08:55 2010 (r6138) @@ -1,198 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - DefinitionBlock ( - "DSDT.AML", - "DSDT", - 0x01, - "XXXXXX", - "XXXXXXXX", - 0x00010001 - ) - { - #include "debug.asl" - } -*/ - -/* -* 0x80: POST_BASE -* 0x3F8: DEBCOM_BASE -* X80: POST_REGION -* P80: PORT80 -* -* CREG: DEBCOM_REGION -* CUAR: DEBCOM_UART -* CDAT: DEBCOM_DATA -* CDLM: DEBCOM_DLM -* DLCR: DEBCOM_LCR -* CMCR: DEBCOM_MCR -* CLSR: DEBCOM_LSR -* -* DEBUG_INIT DINI -*/ - -OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) -{ - P80, 8 -} - -OperationRegion(CREG, SystemIO, 0x3F8, 8) - Field(CREG, ByteAcc, NoLock, Preserve) -{ - CDAT, 8, - CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8 -} - -/* -* DINI -* Initialize the COM port to 115,200 8-N-1 -*/ -Method(DINI) -{ - store(0x83, DLCR) - store(0x01, CDAT) /* 115200 baud (low) */ - store(0x00, CDLM) /* 115200 baud (high) */ - store(0x03, DLCR) /* word=8 stop=1 parity=none */ - store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */ - store(0x00, CDLM) /* turn off interrupts */ -} - -/* -* THRE -* Wait for COM port transmitter holding register to go empty -*/ -Method(THRE) -{ - and(CLSR, 0x20, local0) - while (Lequal(local0, Zero)) { - and(CLSR, 0x20, local0) - } -} - -/* -* OUTX -* Send a single raw character -*/ -Method(OUTX, 1) -{ - THRE() - store(Arg0, CDAT) -} - -/* -* OUTC -* Send a single character, expanding LF into CR/LF -*/ -Method(OUTC, 1) -{ - if (LEqual(Arg0, 0x0a)) { - OUTX(0x0d) - } - OUTX(Arg0) -} - -/* -* DBGN -* Send a single hex nibble -*/ -Method(DBGN, 1) -{ - and(Arg0, 0x0f, Local0) - if (LLess(Local0, 10)) { - add(Local0, 0x30, Local0) - } else { - add(Local0, 0x37, Local0) - } - OUTC(Local0) -} - -/* -* DBGB -* Send a hex byte -*/ -Method(DBGB, 1) -{ - ShiftRight(Arg0, 4, Local0) - DBGN(Local0) - DBGN(Arg0) -} - -/* -* DBGW -* Send a hex word -*/ -Method(DBGW, 1) -{ - ShiftRight(Arg0, 8, Local0) - DBGB(Local0) - DBGB(Arg0) -} - -/* -* DBGD -* Send a hex Dword -*/ -Method(DBGD, 1) -{ - ShiftRight(Arg0, 16, Local0) - DBGW(Local0) - DBGW(Arg0) -} - -/* -* DBGO -* Send either a string or an integer -*/ -Method(DBGO, 1) -{ - /* DINI() */ - if (LEqual(ObjectType(Arg0), 1)) { - if (LGreater(Arg0, 0xffff)) { - DBGD(Arg0) - } else { - if (LGreater(Arg0, 0xff)) { - DBGW(Arg0) - } else { - DBGB(Arg0) - } - } - } else { - Name(BDBG, Buffer(80) {}) - store(Arg0, BDBG) - store(0, Local1) - while (One) { - store(GETC(BDBG, Local1), Local0) - if (LEqual(Local0, 0)) { - return (0) - } - OUTC(Local0) - Increment(Local1) - } - } - return (0) -} - -/* Get a char from a string */ -Method(GETC, 2) -{ - CreateByteField(Arg0, Arg1, DBGC) - return (DBGC) -} Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl Fri Dec 3 01:45:56 2010 (r6137) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl Sat Dec 4 11:08:55 2010 (r6138) @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "ide.asl" - } - } -} -*/ - -/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ -}) - -Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ -}) - -Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ -}) - -/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ -}) - -Name(PORT, Package(){ - 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ -}) - -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) -{ - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ -} - -Method(GTTM, 1) /* get total time*/ -{ - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ - Increment(Local0) - Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ - Increment(Local1) - Return(Multiply(30, Add(Local0, Local1))) -} - -Device(PRID) -{ - Name (_ADR, Zero) - Method(_GTM, 0) - { - NAME(OTBF, Buffer(20) { /* out buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ - CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ - - /* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ - Return(OTBF) - } - - /* Always tell them independent timing available and IOChannelReady used on both drives */ - Or(BFFG, 0x1A, BFFG) - - Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ - Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ - - If(And(PDCR, 0x01)) { /* It's under UDMA mode */ - Or(BFFG, 0x01, BFFG) - Store(DerefOf(Index(UDTT, PDMM)), DSD0) - } - Else { - Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ - } - - If(And(PDCR, 0x02)) { /* It's under UDMA mode */ - Or(BFFG, 0x04, BFFG) - Store(DerefOf(Index(UDTT, PDSM)), DSD1) - } - Else { - Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ - } - - Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ - - Method(_STM, 3, NotSerialized) - { - NAME(INBF, Buffer(20) { /* in buffer */ - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 - }) - - CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ - CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ - CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ - CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ - CreateDwordField(INBF, 16, BFFG) /*buffer flag */ - - Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ - Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ - - Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ - Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ - - If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) - Divide(Local0, 7, PDMM,) - Or(PDCR, 0x01, PDCR) - } - Else { - If(LNotEqual(DSD0, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTM) - } - } - - If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ - Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) - Divide(Local0, 7, PDSM,) - Or(PDCR, 0x02, PDCR) - } - Else { - If(LNotEqual(DSD1, 0xFFFFFFFF)) { - Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) - Store(DerefOf(Index(MDRT, Local0)), PMTS) - } - } - /* Return(INBF) */ - } /*End Method(_STM) */ - Device(MST) - { - Name(_ADR, 0) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xA0, CMDA) - Store(0xA0, CMDB) - Store(0xA0, CMDC) - - Or(PPMM, 0x08, POMD) - - If(And(PDCR, 0x01)) { - Or(PDMM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(MST) */ - - Device(SLAV) - { - Name(_ADR, 1) - Method(_GTF) { - Name(CMBF, Buffer(21) { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 - }) - CreateByteField(CMBF, 1, POMD) - CreateByteField(CMBF, 8, DMMD) - CreateByteField(CMBF, 5, CMDA) - CreateByteField(CMBF, 12, CMDB) - CreateByteField(CMBF, 19, CMDC) - - Store(0xB0, CMDA) - Store(0xB0, CMDB) - Store(0xB0, CMDC) - - Or(PPSM, 0x08, POMD) - - If(And(PDCR, 0x02)) { - Or(PDSM, 0x40, DMMD) - } - Else { - Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) - If(LLess(Local0, 3)) { - Or(0x20, Local0, DMMD) - } - } - Return(CMBF) - } - } /* End Device(SLAV) */ -} Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl Fri Dec 3 01:45:56 2010 (r6137) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl Sat Dec 4 11:08:55 2010 (r6138) @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* simple name description */ - -/* -Scope (_SB) { - Device(PCI0) { - Device(SATA) { - Name(_ADR, 0x00120000) - #include "sata.asl" - } - } -} -*/ - -Name(STTM, Buffer(20) { - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, - 0x1f, 0x00, 0x00, 0x00 -}) - -/* Start by clearing the PhyRdyChg bits */ -Method(_INI) { - \_GPE._L1F() -} - -Device(PMRY) -{ - Name(_ADR, 0) - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(PMST) { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P0IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - }/* end of PMST */ - - Device(PSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P1IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of PSLA */ -} /* end of PMRY */ - - -Device(SEDY) -{ - Name(_ADR, 1) /* IDE Scondary Channel */ - Method(_GTM, 0x0, NotSerialized) { - Return(STTM) - } - Method(_STM, 0x3, NotSerialized) {} - - Device(SMST) - { - Name(_ADR, 0) - Method(_STA,0) { - if (LGreater(P2IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SMST */ - - Device(SSLA) - { - Name(_ADR, 1) - Method(_STA,0) { - if (LGreater(P3IS,0)) { - return (0x0F) /* sata is visible */ - } - else { - return (0x00) /* sata is missing */ - } - } - } /* end of SSLA */ -} /* end of SEDY */ - -/* SATA Hot Plug Support */ -Scope(\_GPE) { - Method(_L1F,0x0,NotSerialized) { - if (\_SB.P0PR) { - if (LGreater(\_SB.P0IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P0PR) - } - - if (\_SB.P1PR) { - if (LGreater(\_SB.P1IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P1PR) - } - - if (\_SB.P2PR) { - if (LGreater(\_SB.P2IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P2PR) - } - - if (\_SB.P3PR) { - if (LGreater(\_SB.P3IS,0)) { - sleep(32) - } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ - store(one, \_SB.P3PR) - } - } -} Modified: trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl Fri Dec 3 01:45:56 2010 (r6137) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl Sat Dec 4 11:08:55 2010 (r6138) @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* simple name description */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "usb.asl" - } -*/ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - UCOC() - if(LEqual(GPB0,PLC0)) { - Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) - } - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - UCOC() - if (LEqual(GPB1,PLC1)) { - Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) - } - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - UCOC() - if (LEqual(GPB2,PLC2)) { - Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) - } - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - UCOC() - if (LEqual(GPB3,PLC3)) { - Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) - } - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - UCOC() - if (LEqual(GPB4,PLC4)) { - Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) - } - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - UCOC() - if (LEqual(GPB5,PLC5)) { - Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) - } - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - UCOC() - if (LEqual(GPB6,PLC6)) { - Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) - } - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - UCOC() - if (LEqual(GPB7,PLC7)) { - Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) - } - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - if (LEqual(G8IS,PLC8)) { - Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) - } - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) - } - } - } -} Modified: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Fri Dec 3 01:45:56 2010 (r6137) +++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Sat Dec 4 11:08:55 2010 (r6138) @@ -28,34 +28,12 @@ ) { /* Start of ASL file */ /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */ + #include "northbridge/amd/amdk8/amdk8_util.asl" - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ - /* USB overcurrent mapping pins. */ - Name(UOM0, 0) - Name(UOM1, 2) - Name(UOM2, 0) - Name(UOM3, 7) - Name(UOM4, 2) - Name(UOM5, 2) - Name(UOM6, 6) - Name(UOM7, 2) - Name(UOM8, 6) - Name(UOM9, 6) - - /* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ /* PIC IRQ mapping registers, C00h-C01h */ @@ -80,320 +58,10 @@ PINH, 0x00000008, /* Index C */ } - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, - } - - Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - #include "acpi/routing.asl" Scope(\_SB) { - Method(CkOT, 0){ - - if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ - - if(CondRefOf(\_OSI,Local1)) - { - Store(1, OSTP) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSTP) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSTP) /* Linux */ - } Else { - Store(4, OSTP) /* Gotta be WinCE */ - } - } - Return(OSTP) - } - Method(_PIC, 0x01, NotSerialized) { If (Arg0) @@ -402,6 +70,7 @@ } Store(Arg0, PMOD) } + Method(CIRQ, 0x00, NotSerialized){ Store(0, PINA) Store(0, PINB) @@ -786,333 +455,8 @@ Name(CSMS, 0) /* Current System State */ /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, PWST) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW (Arg0) - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" + Name(WKST,Package(){Zero, Zero}) /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ @@ -1121,8 +465,7 @@ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ Device(PCI0) { - External (TOM1) - External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ + Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1193,87 +536,6 @@ } } - /* Describe the Southbridge devices */ - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - Device(UOH1) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH1 */ - - Device(UOH2) { - Name(_ADR, 0x00130001) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH2 */ - - Device(UOH3) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH3 */ - - Device(UOH4) { - Name(_ADR, 0x00130003) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH4 */ - - Device(UOH5) { - Name(_ADR, 0x00130004) - Name(_PRW, Package() {0x0B, 3}) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00130005) - Name(_PRW, Package() {0x0B, 3}) - } /* end UEH1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ - Store(zero, NSEN) - Store(one, NSDO) - Store(one, NSDI) - } - } - } /* end AZHD */ - Device(LIBR) { Name(_ADR, 0x00140003) /* Method(_INI) { @@ -1354,413 +616,45 @@ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ } /* end LIBR */ - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) - Device(ACAD) { - Name(_ADR, 0x00140005) - } /* end Ac97audio */ - - Device(ACMD) { - Name(_ADR, 0x00140006) - } /* end Ac97modem */ - - /* ITE8718 Support */ - OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ - Field (IOID, ByteAcc, NoLock, Preserve) - { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ - } - - IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + Method (_CRS, 0, NotSerialized) { - Offset (0x07), - LDN, 8, /* Logical Device Number */ - Offset (0x20), - CID1, 8, /* Chip ID Byte 1, 0x87 */ - CID2, 8, /* Chip ID Byte 2, 0x12 */ - Offset (0x30), - ACTR, 8, /* Function activate */ - Offset (0xF0), - APC0, 8, /* APC/PME Event Enable Register */ - APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ - APC3, 8, /* Environment Controller Special Configuration Register */ - APC4, 8 /* APC/PME Control Register 2 */ - } - - /* Enter the 8718 MB PnP Mode */ - Method (EPNP) - { - Store(0x87, SIOI) - Store(0x01, SIOI) - Store(0x55, SIOI) - Store(0x55, SIOI) /* 8718 magic number */ - } - /* Exit the 8718 MB PnP Mode */ - Method (XPNP) - { - Store (0x02, SIOI) - Store (0x02, SIOD) - } - /* - * Keyboard PME is routed to SB600 Gevent3. We can wake - * up the system by pressing the key. - */ - Method (SIOS, 1) - { - /* We only enable KBD PME for S5. */ - If (LLess (Arg0, 0x05)) - { - EPNP() - /* DBGO("8718F\n") */ - - Store (0x4, LDN) - Store (One, ACTR) /* Enable EC */ - /* - Store (0x4, LDN) - Store (0x04, APC4) - */ /* falling edge. which mode? Not sure. */ - - Store (0x4, LDN) - Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ - Store (0x4, LDN) - Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ - - XPNP() - } - } - Method (SIOW, 1) - { - EPNP() - Store (0x4, LDN) - Store (Zero, APC0) /* disable keyboard PME */ - Store (0x4, LDN) - Store (0xFF, APC1) /* clear keyboard PME status */ - XPNP() - } - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ - - /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - - CreateDWordField(CRES, ^EMM1._BAS, EM1B) - CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) - - If(LGreater(LOMH, 0xC0000)){ - Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ - Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ - } - - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - CkOT() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ } /* End Device(PCI0) */ - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } } /* End \_SB scope */ - - Scope(\_SI) { - Method(_SST, 1) { - /* DBGO("\\_SI\\_SST\n") */ - /* DBGO(" New Indicator state: ") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - } - } /* End Scope SI */ - - /* SMBUS Support */ - Mutex (SBX0, 0x00) - OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) - Field (SMB0, ByteAcc, NoLock, Preserve) { - HSTS, 8, /* SMBUS status */ - SSTS, 8, /* SMBUS slave status */ - HCNT, 8, /* SMBUS control */ - HCMD, 8, /* SMBUS host cmd */ - HADD, 8, /* SMBUS address */ - DAT0, 8, /* SMBUS data0 */ - DAT1, 8, /* SMBUS data1 */ - BLKD, 8, /* SMBUS block data */ - SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shaow cmd */ - SEVT, 8, /* SMBUS slave event */ - SDAT, 8 /* SMBUS slave data */ - } - - Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ - Store (0x1E, HSTS) - Store (0xFA, Local0) - While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { - Stall (0x64) - Decrement (Local0) - } - - Return (Local0) - } - - Method (SWTC, 1, NotSerialized) { - Store (Arg0, Local0) - Store (0x07, Local2) - Store (One, Local1) - While (LEqual (Local1, One)) { - Store (And (HSTS, 0x1E), Local3) - If (LNotEqual (Local3, Zero)) { /* read sucess */ - If (LEqual (Local3, 0x02)) { - Store (Zero, Local2) - } - - Store (Zero, Local1) - } - Else { - If (LLess (Local0, 0x0A)) { /* read failure */ - Store (0x10, Local2) - Store (Zero, Local1) - } - Else { - Sleep (0x0A) /* 10 ms, try again */ - Subtract (Local0, 0x0A, Local0) - } - } - } - - Return (Local2) - } - - Method (SMBR, 3, NotSerialized) { - Store (0x07, Local0) - If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { - Store (WCLR (), Local0) /* clear SMBUS status register before read data */ - If (LEqual (Local0, Zero)) { - Release (SBX0) - Return (0x0) - } - - Store (0x1F, HSTS) - Store (Or (ShiftLeft (Arg1, One), One), HADD) - Store (Arg2, HCMD) - If (LEqual (Arg0, 0x07)) { - Store (0x48, HCNT) /* read byte */ - } - - Store (SWTC (0x03E8), Local1) /* 1000 ms */ - If (LEqual (Local1, Zero)) { - If (LEqual (Arg0, 0x07)) { - Store (DAT0, Local0) - } - } - Else { - Store (Local1, Local0) - } - - Release (SBX0) - } - - /* DBGO("the value of SMBusData0 register ") */ - /* DBGO(Arg2) */ - /* DBGO(" is ") */ - /* DBGO(Local0) */ - /* DBGO("\n") */ - - Return (Local0) - } - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } } /* End of ASL file */

1 0

[patch] add missing code for rs780 lane reversal
by Bao, Zheng 03 Dec '10

03 Dec '10

Before lane reversal, De-asserts STRAP_BIF_all_valid for PCIE-GFX core. After lane reversal, Asserts STRAP_BIF_all_valid for PCIE-GFX core. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/southbridge/amd/rs780/rs780_gfx.c =================================================================== --- src/southbridge/amd/rs780/rs780_gfx.c (revision 6137) +++ src/southbridge/amd/rs780/rs780_gfx.c (working copy) @@ -1302,8 +1302,10 @@ if(is_dev3_present()){ /* step 1, lane reversal (only need if CMOS option is enabled) */ if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); } printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ @@ -1317,10 +1319,11 @@ }else{ if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); } printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); if((dev->path.pci.devfn >> 3) == 2) single_port_configuration(nb_dev, dev);

2 1

[commit] r6137 - in trunk: payloads/libpayload/bin util/crossgcc
by repository service 03 Dec '10

03 Dec '10

Author: mjones Date: Fri Dec 3 01:45:56 2010 New Revision: 6137 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6137 Log: Update coreboot crossgcc toolchain, GCC 4.5.1, MPFR 3.0.0, GDB 7.2. Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin. Add GDB patch to handle #pragma pack in the i386-elf gcc target. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/payloads/libpayload/bin/lpgcc trunk/util/crossgcc/buildgcc Modified: trunk/payloads/libpayload/bin/lpgcc ============================================================================== --- trunk/payloads/libpayload/bin/lpgcc Thu Dec 2 02:50:38 2010 (r6136) +++ trunk/payloads/libpayload/bin/lpgcc Fri Dec 3 01:45:56 2010 (r6137) @@ -30,6 +30,8 @@ # let's not recurse. # This is a hack, I know, but it makes sure that really simple user errors # don't fork-bomb your machine. +echo "CC = $CC" + b=`basename $CC` if [ "$b" = "lpgcc" ]; then CC="" Modified: trunk/util/crossgcc/buildgcc ============================================================================== --- trunk/util/crossgcc/buildgcc Thu Dec 2 02:50:38 2010 (r6136) +++ trunk/util/crossgcc/buildgcc Fri Dec 3 01:45:56 2010 (r6137) @@ -18,8 +18,8 @@ # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA # -CROSSGCC_DATE="May 18th, 2010" -CROSSGCC_VERSION="1.01" +CROSSGCC_DATE="November 16th, 2010" +CROSSGCC_VERSION="1.02" # default settings TARGETDIR=`pwd`/xgcc @@ -28,15 +28,13 @@ # version numbers GMP_VERSION=5.0.1 -MPFR_VERSION=2.4.2 +MPFR_VERSION=3.0.0 MPC_VERSION=0.8.2 LIBELF_VERSION=0.8.13 -# GCC 4.5.0 is broken on some AMD boards: -# GCC_VERSION=4.5.0 # enable for Link Time Optimization & Co -GCC_VERSION=4.4.4 +GCC_VERSION=4.5.1 BINUTILS_VERSION=2.20.1 -GDB_VERSION=7.1 -W32API_VERSION=3.14 +GDB_VERSION=7.2 +W32API_VERSION=3.15 MINGWRT_VERSION=3.18 # archive locations @@ -47,8 +45,8 @@ GCC_ARCHIVE="ftp://ftp.gwdg.de/pub/gnu/ftp/gnu/gcc/gcc-${GCC_VERSION}/gcc-core-${GCC_VERSION}.tar.bz2" BINUTILS_ARCHIVE="http://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" GDB_ARCHIVE="http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2" -W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windo…" -MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20Runtime/mingwrt-${MI…" +W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibr…" +MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW/BaseSystem/RuntimeLibr…" GMP_DIR="gmp-${GMP_VERSION}" MPFR_DIR="mpfr-${MPFR_VERSION}" @@ -356,7 +354,7 @@ cd build-libelf rm -f .failed echo "$HOSTCFLAGS" - CFLAGS="$HOSTCFLAGS" ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \ + CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed

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[PATCH]Allow relocated .config location
by Patrick Georgi 03 Dec '10

03 Dec '10

Hi, right now, the build system assumes that .config is in $(top). abuild stores each board's .config by copying it into the build directory after the fact, while clobbering any existing files. With the attached patch, it's possible to define a new location for .config, using the DOTCONFIG variable, and abuild makes use of that. It still messes around with .xcompile and the various .config copies, so this is only the second step of many (I already started on that topic a while ago, with a minor change to Makefile), but it's a start, and should be self contained. == Allow user to relocate .config by using the DOTCONFIG variable. Make abuild use that. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

2 1

[PATCH] ASUS P2B ACPI sleep preparations
by Tobias Diedrich 02 Dec '10

02 Dec '10

Add acpi_is_wakeup_early to i82371eb and P2B. Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Other chipsets so far only ever set acpi_slp_type to 0 and 3. Abuild-tested. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: coreboot-svn-p2b/src/mainboard/asus/p2b/romstage.c =================================================================== --- coreboot-svn-p2b.orig/src/mainboard/asus/p2b/romstage.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/mainboard/asus/p2b/romstage.c 2010-11-27 11:55:12.000000000 +0100 @@ -36,6 +36,8 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void enable_pm(void); +int acpi_is_wakeup_early(void); void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); @@ -46,14 +48,23 @@ void main(unsigned long bist) { + u16 boot_mode; + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); + enable_pm(); + boot_mode = acpi_is_wakeup_early(); + enable_smbus(); dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); + if (boot_mode == 5 || boot_mode == 0) { + /* should't be needed on warm boot (boot_mode 0), + * but can't hurt... */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + } } Index: coreboot-svn-p2b/src/arch/i386/boot/acpi.c =================================================================== --- coreboot-svn-p2b.orig/src/arch/i386/boot/acpi.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/arch/i386/boot/acpi.c 2010-11-27 11:48:41.000000000 +0100 @@ -481,7 +481,7 @@ static int acpi_is_wakeup(void) { - return (acpi_slp_type == 3); + return (acpi_slp_type == 3 || acpi_slp_type == 2); } static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) @@ -567,9 +567,11 @@ return wake_vec; } +#if CONFIG_SMP == 1 extern char *lowmem_backup; extern char *lowmem_backup_ptr; extern int lowmem_backup_size; +#endif #define WAKEUP_BASE 0x600 @@ -588,12 +590,14 @@ return; } +#if CONFIG_SMP == 1 // FIXME: This should go into the ACPI backup memory, too. No pork saussages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. */ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); +#endif /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); Index: coreboot-svn-p2b/src/southbridge/intel/i82371eb/Kconfig =================================================================== --- coreboot-svn-p2b.orig/src/southbridge/intel/i82371eb/Kconfig 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/southbridge/intel/i82371eb/Kconfig 2010-11-27 11:48:41.000000000 +0100 @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES config BOOTBLOCK_SOUTHBRIDGE_INIT string Index: coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- coreboot-svn-p2b.orig/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-11-27 11:51:16.000000000 +0100 @@ -31,6 +31,10 @@ #include "i82371eb.h" #include "i82371eb_smbus.h" +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif + static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -87,6 +91,24 @@ outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); +#if CONFIG_HAVE_ACPI_RESUME == 1 + reg = (inw(DEFAULT_PMBASE + PMCNTRL) >> 10) & 7; + switch (reg) { + case 1: + acpi_slp_type = 3; + break; + case 2: + case 3: + acpi_slp_type = 2; + break; + default: + acpi_slp_type = 5; + break; + } + printk(BIOS_INFO, + "%s: acpi_slp_type=%d!\n", __func__, acpi_slp_type); +#endif + /* set pmcntrl default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } Index: coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c =================================================================== --- coreboot-svn-p2b.orig/src/southbridge/intel/i82371eb/i82371eb_early_pm.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c 2010-11-27 11:48:41.000000000 +0100 @@ -51,3 +51,48 @@ reg8 |= PMIOSE; pci_write_config8(dev, PMREGMISC, reg8); } + +int acpi_is_wakeup_early(void); + +/* + * Intel i82371eb (piix4e) datasheet, section 7.2.3, page 142: + * + * 000b / 0x0: soft off/suspend to disk (soff/std) S5 + * 001b / 0x1: suspend to ram (str) S3 + * 010b / 0x2: powered on suspend, context lost (poscl) S2 + * Note: 'context lost' menas the cpu restarts at the reset vector + * 011b / 0x3: powered on suspend, cpu context lost (posccl) S1 + * Note: Looks like 'cpu context lost' does _not_ mean the cpu + * restarts at the reset vector. Most likely only caches + * are lost, so both 0x3 and 0x4 map to acpi S1 + * 100b / 0x4: powered on suspend, context maintained (pos) S1 + * 101b / 0x5: working (clock control) S0 + * 110b / 0x6: reserved + * 111b / 0x7: reserved + */ +static const u8 acpi_sus_to_slp_typ[8] = { + 5, 3, 2, 1, 1, 0, 0, 0 +}; + +int acpi_is_wakeup_early(void) +{ + u16 tmp, result; + + print_debug(__func__); + print_debug("\n"); + + tmp = inw(DEFAULT_PMBASE + PMCNTRL); + print_debug(" pmcntrl="); + print_debug_hex16(tmp); + print_debug("\n"); + + result = 5; /* S5, system came out of power-off */ + tmp = (tmp >> 10) & 7; + result = acpi_sus_to_slp_typ[tmp]; + + print_debug(" boot_mode="); + print_debug_hex8(result); + print_debug("\n"); + + return result; +}

4 9

iWill mainboards???
by Joseph Smith 02 Dec '10

02 Dec '10

Hello, I was just looking a iWill DK8S2 Opteron board but can not find the iWill website on the web. Anyone know what happened to them? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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coreboot December 2010