coreboot December 2010

coreboot@coreboot.org

52 participants
262 discussions

Buying CPU and memory for board M2V-MX_SE with S3 support
by Fengwei Zhang 06 Dec '10

06 Dec '10

Hi all, I am going to buy CPU and memory for board M2V-MX_SE with S3 support. According to Ruldof, the CPU with core stepping BH-G1, DH-G2 and BH-G2 might support S3. I am considering to buy AMD Sempron 64 LE-1300, and its core stepping is DH-G2. How do you think? Following is the link of this CPU http://www.cpu-world.com/CPUs/K8/AMD-Sempron%2064%20LE-1300%20-%20SDH1300IA… Another question is about the RAM. What is size of RAM that you would suggest to use? The goal is to make sure S3 would work. I would appreciate any precious suggestions and comments. Best, Fengwei

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[commit] r6144 - in trunk/src/mainboard/supermicro: x6dhe_g x6dhe_g2 x6dhr_ig x6dhr_ig2
by repository service 06 Dec '10

06 Dec '10

Author: uwe Date: Mon Dec 6 19:20:48 2010 New Revision: 6144 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6144 Log: Get rid of some useless/empty *_fixups.c files. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c trunk/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c trunk/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c trunk/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Dec 6 19:17:01 2010 (r6143) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Dec 6 19:20:48 2010 (r6144) @@ -16,7 +16,6 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "x6dhe_g_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -35,6 +34,10 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) +static void mch_reset(void) {} +static void mainboard_set_e7520_pll(unsigned bits) {} +static void mainboard_set_e7520_leds(void) {} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Mon Dec 6 19:17:01 2010 (r6143) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Mon Dec 6 19:20:48 2010 (r6144) @@ -14,7 +14,6 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "x6dhe_g2_fixups.c" #include "superio/nsc/pc87427/pc87427_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -32,6 +31,10 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) +static void mch_reset(void) {} +static void mainboard_set_e7520_pll(unsigned bits) {} +static void mainboard_set_e7520_leds(void) {} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Dec 6 19:17:01 2010 (r6143) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Dec 6 19:20:48 2010 (r6144) @@ -14,7 +14,6 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "x6dhr_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -34,6 +33,10 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) +static void mch_reset(void) {} +static void mainboard_set_e7520_pll(unsigned bits) {} +static void mainboard_set_e7520_leds(void) {} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Dec 6 19:17:01 2010 (r6143) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Dec 6 19:20:48 2010 (r6144) @@ -14,7 +14,6 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "x6dhr2_fixups.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" @@ -34,6 +33,10 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) +static void mch_reset(void) {} +static void mainboard_set_e7520_pll(unsigned bits) {} +static void mainboard_set_e7520_leds(void) {} + static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address);

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[commit] r6143 - in trunk/src/mainboard: msi/ms6178 supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_fam10 supermicro/h8qme_fam10 supermicro/x6dai_g supermicro/x6dhe_g supermicro/x6dhr_ig supermi...
by repository service 06 Dec '10

06 Dec '10

Author: uwe Date: Mon Dec 6 19:17:01 2010 New Revision: 6143 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6143 Log: Winbond W83627HF: Use existing functions instead of open-coding. Use w83627hf_set_clksel_48() where needed instead or open-coding the same functionality, and also use w83627hf_enable_serial() instead of w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the enter/exit config mode functions). Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/msi/ms6178/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-n/romstage.c Modified: trunk/src/mainboard/msi/ms6178/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms6178/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/msi/ms6178/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -33,18 +33,15 @@ #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); void main(unsigned long bist) { - /* FIXME */ - outb(0x87, 0x2e); - outb(0x87, 0x2e); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); + w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - outb(0x87, 0xaa); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -48,6 +48,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -193,10 +194,8 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -51,6 +51,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -122,10 +123,8 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -50,6 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +126,8 @@ post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -50,6 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -176,10 +177,8 @@ post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -16,13 +16,14 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -63,11 +64,8 @@ skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -17,13 +17,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhe_g_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -60,11 +61,8 @@ skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -15,13 +15,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhr_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D0F0 | \ @@ -59,11 +60,8 @@ skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -15,13 +15,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhr2_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D0F0 | \ @@ -59,11 +60,8 @@ skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/via/epia-m700/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -46,6 +46,7 @@ #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) /* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: @@ -384,7 +385,7 @@ */ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ - w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_set_clksel_48(DUMMY_DEV); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); /* enable_vx800_serial(); */ Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Mon Dec 6 09:19:38 2010 (r6142) +++ trunk/src/mainboard/via/epia-n/romstage.c Mon Dec 6 19:17:01 2010 (r6143) @@ -38,6 +38,7 @@ #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static const struct mem_controller ctrl = { .d0f0 = 0x0000, @@ -109,7 +110,7 @@ /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_set_clksel_48(DUMMY_DEV); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();

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Trac reminder: list of new ticket(s)
by coreboot tracker 06 Dec '10

06 Dec '10

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FLASHROM: Add support for M25P80.RES
by Sven Schnelle 06 Dec '10

06 Dec '10

Hi List, i've tried using flashrom for reading the SPI Flash of my Thinkpad X60s. It seems like it is using the (yet) unsupported M25P80.RES. I've added the few lines required to get it working, and at least reading the NVM works. Haven't tried writing the Flash (yes, i know about the risk regarding EC and friends) ;-) /sven Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Index: flashchips.c =================================================================== --- flashchips.c (revision 1246) +++ flashchips.c (working copy) @@ -6162,6 +6162,31 @@ .write = spi_chip_write_256, .read = spi_chip_read, }, + { + .vendor = "ST", + .name = "M25P80.RES", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = 0, /* Not used */ + .model_id = ST_M25P80_RES, + .total_size = 1024, + .page_size = 256, + .tested = TEST_OK_PR, + .probe = probe_spi_res1, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, { .vendor = "ST", Index: flashchips.h =================================================================== --- flashchips.h (revision 1246) +++ flashchips.h (working copy) @@ -527,6 +527,7 @@ #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12 #define ST_M25P80 0x2014 +#define ST_M25P80_RES 0x14 #define ST_M25P16 0x2015 #define ST_M25P32 0x2016 #define ST_M25P64 0x2017

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[commit] r6142 - trunk/src/southbridge/amd/rs780
by repository service 06 Dec '10

06 Dec '10

Author: zbao Date: Mon Dec 6 09:19:38 2010 New Revision: 6142 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6142 Log: Before lane reversal, De-asserts STRAP_BIF_all_valid for PCIE-GFX core. After lane reversal, Asserts STRAP_BIF_all_valid for PCIE-GFX core. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: QingPei Wang <wangqingpei(a)gmail.com> Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Mon Dec 6 02:11:12 2010 (r6141) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Mon Dec 6 09:19:38 2010 (r6142) @@ -1302,8 +1302,10 @@ if(is_dev3_present()){ /* step 1, lane reversal (only need if CMOS option is enabled) */ if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); } printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ @@ -1317,10 +1319,11 @@ }else{ if (cfg->gfx_lane_reversal) { + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31); set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2); + set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31); } printk(BIOS_DEBUG, "rs780_gfx_init step1.\n"); - printk(BIOS_DEBUG, "rs780_gfx_init step2.\n"); if((dev->path.pci.devfn >> 3) == 2) single_port_configuration(nb_dev, dev);

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[PATCH] Support for Asus M4A78-EM mainboard
by Juhana Helovuo 06 Dec '10

06 Dec '10

Hello, Here is a patch to get Asus M4A78-EM supported and booting Linux. Files attached are: * Boot log with the patches applied. * Board-specific patch for SVN 6139 * Resend of Myles Watson's patch for AMD Northbridge, because the original did not work for me without manual editing. It is also needed for booting Linux. Before applying the patch, the board directory should be created with % svn cp src/mainboard/asus/m4a785-m src/mainboard/asus/m4a78-em Signed-off-by: Juhana Helovuo <juhe(a)iki.fi> Best regards, Juhana Helovuo

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[commit] r6141 - in trunk/src/mainboard/asus: . m4a78-em m4a785-m
by repository service 06 Dec '10

06 Dec '10

Author: uwe Date: Mon Dec 6 02:11:12 2010 New Revision: 6141 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6141 Log: Add initial support for the ASUS M4A78-EM. Signed-off-by: Juhana Helovuo <juhe(a)iki.fi> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/mainboard/asus/m4a78-em/ - copied from r6139, trunk/src/mainboard/asus/m4a785-m/ Modified: trunk/src/mainboard/asus/Kconfig trunk/src/mainboard/asus/m4a78-em/Kconfig trunk/src/mainboard/asus/m4a78-em/devicetree.cb trunk/src/mainboard/asus/m4a78-em/irq_tables.c trunk/src/mainboard/asus/m4a78-em/mainboard.c trunk/src/mainboard/asus/m4a78-em/mptable.c trunk/src/mainboard/asus/m4a785-m/irq_tables.c trunk/src/mainboard/asus/m4a785-m/mainboard.c Modified: trunk/src/mainboard/asus/Kconfig ============================================================================== --- trunk/src/mainboard/asus/Kconfig Sun Dec 5 23:36:14 2010 (r6140) +++ trunk/src/mainboard/asus/Kconfig Mon Dec 6 02:11:12 2010 (r6141) @@ -33,6 +33,8 @@ bool "M2V-MX SE" config BOARD_ASUS_M4A785M bool "M4A785-M" +config BOARD_ASUS_M4A78_EM + bool "M4A78-EM" config BOARD_ASUS_MEW_AM bool "MEW-AM" config BOARD_ASUS_MEW_VM @@ -58,6 +60,7 @@ source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" +source "src/mainboard/asus/m4a78-em/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" source "src/mainboard/asus/mew-vm/Kconfig" source "src/mainboard/asus/p2b/Kconfig" Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/Kconfig Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/m4a78-em/Kconfig Mon Dec 6 02:11:12 2010 (r6141) @@ -1,4 +1,4 @@ -if BOARD_ASUS_M4A785M +if BOARD_ASUS_M4A78_EM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -8,7 +8,6 @@ select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 - select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select BOARD_HAS_FADT select HAVE_BUS_CONFIG @@ -31,7 +30,7 @@ config MAINBOARD_DIR string - default asus/m4a785-m + default asus/m4a78-em config APIC_ID_OFFSET hex @@ -39,7 +38,7 @@ config MAINBOARD_PART_NUMBER string - default "M4A785-M" + default "M4A78-EM" config MAX_CPUS int @@ -67,7 +66,7 @@ config IRQ_SLOT_COUNT int - default 19 + default 18 config AMD_UCODE_PATCH_FILE string @@ -83,7 +82,7 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x83a2 + default 0x83f1 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex Modified: trunk/src/mainboard/asus/m4a78-em/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/m4a78-em/devicetree.cb Mon Dec 6 02:11:12 2010 (r6141) @@ -10,15 +10,15 @@ chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606 device pci 7.0 off end # PCIE P2P bridge 0x9607 device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + device pci 9.0 on end # + device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet register "gppsb_configuration" = "1" # Configuration B register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" Modified: trunk/src/mainboard/asus/m4a78-em/irq_tables.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/irq_tables.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/m4a78-em/irq_tables.c Mon Dec 6 02:11:12 2010 (r6141) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 200x TODO <TODO@TODO> + * Copyright (C) 2010 Juhana Helovuo <juhe(a)iki.fi> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * 19, /* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x14 << 3) | 0x3, /* Interrupt router dev */ 0, /* IRQs devoted exclusively to PCI usage */ @@ -31,7 +31,7 @@ 0x439d, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x8, /* Checksum (has to be set to some value that + 0xca, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). */ @@ -53,9 +53,8 @@ {0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0}, {0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, {0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, - {0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0}, - {0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0}, + {0x03, (0x06 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xd, 0x0}, + {0x03, (0x07 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xe, 0x0}, } }; Modified: trunk/src/mainboard/asus/m4a78-em/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/mainboard.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/m4a78-em/mainboard.c Mon Dec 6 02:11:12 2010 (r6141) @@ -27,19 +27,11 @@ #include <southbridge/amd/sb700/sb700.h> #include "chip.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) #define SMBUS_IO_BASE 0x6000 @@ -132,7 +124,7 @@ /* * justify the dev3 is exist or not * NOTE: This just copied from AMD Tilapia code. - * It is completly unknown it it will work at all for Asus M4A785-A + * It is completly unknown if it will work at all for this board. */ u8 is_dev3_present(void) { @@ -159,77 +151,14 @@ } } -/* - * set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - device_t sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ -} /************************************************* -* enable the dedicated function in m4a785m board. +* enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void m4a785m_enable(device_t dev) +static void m4a78em_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard M4A785M Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -272,10 +201,10 @@ set_pcie_dereset(); /* get_ide_dma66(); */ - set_thermal_config(); + /* set_thermal_config(); */ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD M4A785M Mainboard") - .enable_dev = m4a785m_enable, + CHIP_NAME("ASUS M4A78-EM Mainboard") + .enable_dev = m4a78em_enable, }; Modified: trunk/src/mainboard/asus/m4a78-em/mptable.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/mptable.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/m4a78-em/mptable.c Mon Dec 6 02:11:12 2010 (r6141) @@ -40,7 +40,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, "M4A785-M ", LAPIC_ADDR); + mptable_init(mc, "M4A78-EM ", LAPIC_ADDR); smp_write_processors(mc); Modified: trunk/src/mainboard/asus/m4a785-m/irq_tables.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/irq_tables.c Sun Dec 5 23:36:14 2010 (r6140) +++ trunk/src/mainboard/asus/m4a785-m/irq_tables.c Mon Dec 6 02:11:12 2010 (r6141) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 200x TODO <TODO@TODO> + * Copyright (C) 2010 Juhana Helovuo <juhe(a)iki.fi> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * 19, /* Max. number of devices on the bus */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ 0x00, /* Interrupt router bus */ (0x14 << 3) | 0x3, /* Interrupt router dev */ 0, /* IRQs devoted exclusively to PCI usage */ Modified: trunk/src/mainboard/asus/m4a785-m/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/mainboard.c Sun Dec 5 23:36:14 2010 (r6140) +++ trunk/src/mainboard/asus/m4a785-m/mainboard.c Mon Dec 6 02:11:12 2010 (r6141) @@ -132,7 +132,7 @@ /* * justify the dev3 is exist or not * NOTE: This just copied from AMD Tilapia code. - * It is completly unknown it it will work at all for Asus M4A785-A + * It is completly unknown it it will work at all for ASUS M4A785-M. */ u8 is_dev3_present(void) { @@ -224,12 +224,12 @@ } /************************************************* -* enable the dedicated function in m4a785m board. +* enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ static void m4a785m_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard M4A785M Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; @@ -276,6 +276,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD M4A785M Mainboard") + CHIP_NAME("ASUS M4A785-M Mainboard") .enable_dev = m4a785m_enable, };

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[PATCH] W83627DHG/W83627EHG fixups for virtual LDNs
by Uwe Hermann 05 Dec '10

05 Dec '10

This is abuild-tested. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r6140 - in trunk/src: include/device mainboard/asrock/939a785gmh mainboard/asus/a8v-e_deluxe mainboard/asus/a8v-e_se mainboard/ibase/mb899 mainboard/kontron/kt690 mainboard/msi/ms7260 main...
by repository service 05 Dec '10

05 Dec '10

Author: uwe Date: Sun Dec 5 23:36:14 2010 New Revision: 6140 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6140 Log: W83627DHG/W83627EHG fixups for virtual LDNs. W83627DHG: - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those that don't have their "enable" bit in bit 0 of the 0x30 register). - Fix various I/O masks in the pnp_dev_info[] array as per datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN. W83627EHG: - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was mostly implemented already, though). - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN. Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt for the virtual LDNs. include/device/pnp.h: Add comment that 'function' (which refers to the LDN and should probably be renamed later) has to be at least 16 bits wide. In theory LDNs could use u8, but due to the virtual LDN info being encoded in the "high byte" of 'function' it must be at least u16. asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV. ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial port 1 in this case) to avoid confusion. The global registers manipulated there are accessible from any LDN. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/include/device/pnp.h trunk/src/mainboard/asrock/939a785gmh/devicetree.cb trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c trunk/src/mainboard/asus/a8v-e_se/devicetree.cb trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/ibase/mb899/devicetree.cb trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/msi/ms7260/devicetree.cb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb trunk/src/superio/winbond/w83627dhg/superio.c trunk/src/superio/winbond/w83627dhg/w83627dhg.h trunk/src/superio/winbond/w83627ehg/superio.c trunk/src/superio/winbond/w83627ehg/w83627ehg.h Modified: trunk/src/include/device/pnp.h ============================================================================== --- trunk/src/include/device/pnp.h Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/include/device/pnp.h Sun Dec 5 23:36:14 2010 (r6140) @@ -31,7 +31,7 @@ struct pnp_info { struct device_operations *ops; - unsigned int function; + unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */ unsigned int flags; #define PNP_IO0 0x001 #define PNP_IO1 0x002 Modified: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -85,7 +85,7 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Dec 5 23:36:14 2010 (r6140) @@ -49,8 +49,7 @@ #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6) -#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345) +#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } Modified: trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/a8v-e_deluxe/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -49,9 +49,9 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # PS/2 keyboard (off) + device pnp 2e.5 off # PS/2 keyboard & mouse (off) end - device pnp 2e.106 off # Serial flash + device pnp 2e.106 off # Serial flash interface (SFI) io 0x60 = 0x100 end device pnp 2e.007 off # GPIO 1 @@ -65,15 +65,15 @@ end device pnp 2e.307 off # GPIO 6 end - device pnp 2e.8 off # WDTO_PLED + device pnp 2e.8 off # WDTO#, PLED end - device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup + device pnp 2e.009 on # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO5 + device pnp 2e.309 on # GPIO 5 end device pnp 2e.a off # ACPI end Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Dec 5 23:36:14 2010 (r6140) @@ -49,7 +49,7 @@ #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) static void memreset(int controllers, const struct mem_controller *ctrl) { } Modified: trunk/src/mainboard/asus/a8v-e_se/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/a8v-e_se/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -49,9 +49,9 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 off # PS/2 keyboard (off) + device pnp 2e.5 off # PS/2 keyboard & mouse (off) end - device pnp 2e.106 off # Serial flash + device pnp 2e.106 off # Serial flash interface (SFI) io 0x60 = 0x100 end device pnp 2e.007 off # GPIO 1 @@ -65,15 +65,15 @@ end device pnp 2e.307 off # GPIO 6 end - device pnp 2e.8 off # WDTO_PLED + device pnp 2e.8 off # WDTO#, PLED end - device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup + device pnp 2e.009 on # GPIO 2 end device pnp 2e.109 off # GPIO 3 end device pnp 2e.209 off # GPIO 4 end - device pnp 2e.309 on # GPIO5 + device pnp 2e.309 on # GPIO 5 end device pnp 2e.a off # ACPI end Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Dec 5 23:36:14 2010 (r6140) @@ -49,7 +49,7 @@ #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) static void memreset(int controllers, const struct mem_controller *ctrl) { } Modified: trunk/src/mainboard/ibase/mb899/devicetree.cb ============================================================================== --- trunk/src/mainboard/ibase/mb899/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/ibase/mb899/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -63,29 +63,38 @@ irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq end - device pnp 4e.5 on # Keyboard+Mouse + device pnp 4e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 irq 0xf0 = 0x82 # HW accel A20. end - device pnp 4e.7 on # GPIO1, GAME, MIDI - io 0x62 = 0x330 + device pnp 4e.106 off end # Serial flash interface (SFI) + device pnp 4e.007 off end # GPIO 1 + device pnp 4e.107 off end # Game port + device pnp 4e.207 on # MIDI + io 0x62 = 0x330 irq 0x70 = 9 end - device pnp 4e.8 on # GPIO2 - # all default + device pnp 4e.307 off end # GPIO 6 + device pnp 4e.8 off end # WDTO#, PLED + device pnp 4e.009 on # GPIO 2 + # All default end - device pnp 4e.9 on # GPIO3/4 - irq 0x30 = 0x03 # does this work? + device pnp 4e.109 on # GPIO 3 irq 0xf0 = 0xfb # set inputs/outputs irq 0xf1 = 0x66 end + device pnp 4e.209 on # GPIO 4 + end + device pnp 4e.309 off # GPIO 5 + end device pnp 4e.a on # ACPI + # TODO: IRQ end device pnp 4e.b on # HWM - io 0x60 = 0x290 + io 0x60 = 0x290 irq 0x70 = 0 end Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/ibase/mb899/romstage.c Sun Dec 5 23:36:14 2010 (r6140) @@ -38,6 +38,7 @@ #include "southbridge/intel/i82801gx/i82801gx.h" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +#define DUMMY_DEV PNP_DEV(0x4e, 0) void enable_smbus(void); @@ -79,7 +80,7 @@ { device_t dev; - dev=PNP_DEV(0x4e, W83627EHG_SP1); + dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x24, 0xc4); // PNPCSV Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb ============================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -83,11 +83,17 @@ end #device pnp 2e.6 off # SPI #end - device pnp 2e.7 off # GPIO + device pnp 2e.307 off # GPIO 1 end device pnp 2e.8 on # WDTO#, PLED end - device pnp 2e.9 off # GPIO + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 end device pnp 2e.a off # ACPI end Modified: trunk/src/mainboard/msi/ms7260/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7260/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/msi/ms7260/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -28,28 +28,41 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.5 on # PS/2 keyboard + device pnp 4e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 # PS/2 keyboard IRQ irq 0x72 = 12 # PS/2 mouse IRQ end - device pnp 4e.6 off # Serial flash interface + device pnp 4e.106 off # Serial flash interface (SFI) # io 0x62 = 0x100 end - device pnp 4e.7 off # GPIO1/6, game port, MIDI port + device pnp 4e.007 off # GPIO 1 + end + device pnp 4e.107 off # Game port # io 0x60 = 0x220 # Datasheet: 0x201 + end + device pnp 4e.207 off # MIDI # io 0x62 = 0x300 # Datasheet: 0x330 # irq 0x70 = 9 end + device pnp 4e.307 off # GPIO 6 + end device pnp 4e.8 off # WDTO#, PLED end - device pnp 4e.9 off # GPIO2/3/4/5, SUSLED + device pnp 4e.009 off # GPIO 2 + end + device pnp 4e.109 off # GPIO 3 + end + device pnp 4e.209 off # GPIO 4 + end + device pnp 4e.309 off # GPIO 5 end device pnp 4e.a off # ACPI end - device pnp 4e.b on # HWM (for lm-sensors) + device pnp 4e.b on # Hardware monitor io 0x60 = 0xa10 + # TODO: IRQ? end end end Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -28,22 +28,35 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Serial flash + device pnp 2e.106 off # Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.7 off # Game port, MIDI, GPIO1 + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5 + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off end # WDTO#, PLED + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 Modified: trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -51,34 +51,41 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # Serial flash + device pnp 2e.106 off # Serial flash interface (SFI) io 0x60 = 0x100 end - device pnp 2e.7 off # Game port, MIDI, GPIO1 + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5 + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 irq 0x70 = 5 end - device pnp 2e.106 off # Serial flash - io 0x60 = 0x100 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end end end device pci 1.1 on # SM 0 Modified: trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb Sun Dec 5 23:36:14 2010 (r6140) @@ -28,22 +28,36 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard + device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 end - device pnp 2e.7 off # GPIO, Game port, MIDI + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end device pnp 2e.a off end # ACPI device pnp 2e.b on # Hardware monitor io 0x60 = 0x290 Modified: trunk/src/superio/winbond/w83627dhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627dhg/superio.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/superio/winbond/w83627dhg/superio.c Sun Dec 5 23:36:14 2010 (r6140) @@ -94,18 +94,21 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, - { &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, - { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, - { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, - { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, /* the next line makes coreboot hang in pnp_enable_devices() */ - /* { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, */ + /* { &ops, W83627DHG_SPI, PNP_IO1, { 0x7f8, 0 }, }, */ { &ops, W83627DHG_GPIO6, }, { &ops, W83627DHG_WDTO_PLED, }, - { &ops, W83627DHG_GPIO2345, }, - { &ops, W83627DHG_ACPI, }, - { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, }, + { &ops, W83627DHG_GPIO2, }, + { &ops, W83627DHG_GPIO3, }, + { &ops, W83627DHG_GPIO4, }, + { &ops, W83627DHG_GPIO5, }, + { &ops, W83627DHG_ACPI, PNP_IRQ0, }, + { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, }, { &ops, W83627DHG_PECI_SST, }, }; Modified: trunk/src/superio/winbond/w83627dhg/w83627dhg.h ============================================================================== --- trunk/src/superio/winbond/w83627dhg/w83627dhg.h Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/superio/winbond/w83627dhg/w83627dhg.h Sun Dec 5 23:36:14 2010 (r6140) @@ -25,13 +25,30 @@ #define W83627DHG_PP 1 /* Parallel port */ #define W83627DHG_SP1 2 /* Com1 */ #define W83627DHG_SP2 3 /* Com2 */ -#define W83627DHG_KBC 5 /* PS/2 keyboard + mouse */ +#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ #define W83627DHG_SPI 6 /* Serial peripheral interface */ -#define W83627DHG_GPIO6 7 /* GPIO6 */ #define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ -#define W83627DHG_GPIO2345 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */ #define W83627DHG_ACPI 10 /* ACPI */ #define W83627DHG_HWM 11 /* Hardware monitor */ #define W83627DHG_PECI_SST 12 /* PECI, SST */ +/* The following are handled using "virtual LDNs" (hence the _V suffix). */ +#define W83627DHG_GPIO6_V 7 /* GPIO6 */ +#define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */ + +/* + * Virtual devices sharing the enables are encoded as follows: + * VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN + */ + +/* GPIO6 has bit 3 as enable (instead of bit 0 as usual). */ +#define W83627DHG_GPIO6 ((3 << 8) | W83627DHG_GPIO6_V) + +#define W83627DHG_GPIO2 ((0 << 8) | W83627DHG_GPIO2345_V) +#define W83627DHG_GPIO3 ((1 << 8) | W83627DHG_GPIO2345_V) +#define W83627DHG_GPIO4 ((2 << 8) | W83627DHG_GPIO2345_V) +#define W83627DHG_GPIO5 ((3 << 8) | W83627DHG_GPIO2345_V) + +/* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ + #endif Modified: trunk/src/superio/winbond/w83627ehg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/superio/winbond/w83627ehg/superio.c Sun Dec 5 23:36:14 2010 (r6140) @@ -178,17 +178,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, - { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_WDTO_PLED, }, - { &ops, W83627EHG_ACPI, }, - { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83627EHG_ACPI, PNP_IRQ0, }, + { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, }, + { &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, }, - { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, + { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, }, { &ops, W83627EHG_GPIO1, }, { &ops, W83627EHG_GPIO2, }, { &ops, W83627EHG_GPIO3, }, Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg.h ============================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg.h Sat Dec 4 21:50:39 2010 (r6139) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg.h Sun Dec 5 23:36:14 2010 (r6140) @@ -27,27 +27,32 @@ #define W83627EHG_SP1 2 /* Com1 */ #define W83627EHG_SP2 3 /* Com2 */ #define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */ -#define W83627EHG_GPIO_GAME_MIDI 7 /* GPIO1, GPIO6, Game port, MIDI port */ -#define W83627EHG_WDTO_PLED 8 /* TODO */ -#define W83627EHG_GPIO_SUSLED 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */ +#define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */ #define W83627EHG_ACPI 10 /* ACPI */ #define W83627EHG_HWM 11 /* Hardware monitor */ +/* The following are handled using "virtual LDNs" (hence the _V suffix). */ +#define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */ +#define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */ +#define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */ + /* * Virtual devices sharing the enables are encoded as follows: * VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN */ -#define W83627EHG_SFI ((1 << 8) | 6) /* Flash has bit1 as enable */ -#define W83627EHG_GPIO1 W83627EHG_GPIO_GAME_MIDI /* GPIO1: LDN 7, bit 0 */ -#define W83627EHG_GAME ((1 << 8) | 7) -#define W83627EHG_MIDI ((2 << 8) | 7) -#define W83627EHG_GPIO6 ((3 << 8) | 7) - -#define W83627EHG_GPIO2 W83627EHG_GPIO_SUSLED /* GPIO2: LDN 9, bit 0 */ -#define W83627EHG_GPIO3 ((1 << 8) | 9) -#define W83627EHG_GPIO4 ((2 << 8) | 9) -#define W83627EHG_GPIO5 ((3 << 8) | 9) +/* SFI has bit 1 as enable (instead of bit 0 as usual). */ +#define W83627EHG_SFI ((1 << 8) | W83627EHG_SFI_V) + +#define W83627EHG_GPIO1 ((0 << 8) | W83627EHG_GPIO_GAME_MIDI_V) +#define W83627EHG_GAME ((1 << 8) | W83627EHG_GPIO_GAME_MIDI_V) +#define W83627EHG_MIDI ((2 << 8) | W83627EHG_GPIO_GAME_MIDI_V) +#define W83627EHG_GPIO6 ((3 << 8) | W83627EHG_GPIO_GAME_MIDI_V) + +#define W83627EHG_GPIO2 ((0 << 8) | W83627EHG_GPIO_SUSLED_V) +#define W83627EHG_GPIO3 ((1 << 8) | W83627EHG_GPIO_SUSLED_V) +#define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) +#define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) #if defined(__PRE_RAM__) && !defined(__ROMCC__) void w83627ehg_enable_dev(device_t dev, u16 iobase);

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coreboot December 2010