coreboot December 2010

coreboot@coreboot.org

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[commit] r6168 - trunk/src/cpu/intel/model_106cx
by repository service 12 Dec '10

12 Dec '10

Author: stepan Date: Sun Dec 12 01:37:41 2010 New Revision: 6168 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6168 Log: fix model 106cx Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/cpu/intel/model_106cx/model_106cx_init.c Modified: trunk/src/cpu/intel/model_106cx/model_106cx_init.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sun Dec 12 00:28:17 2010 (r6167) +++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sun Dec 12 01:37:41 2010 (r6168) @@ -97,14 +97,16 @@ // TODO Do we want Deep C4 and Dynamic L2 shrinking? wrmsr(PMG_CST_CONFIG_CONTROL, msr); - // set P_BLK address - msr = rdmsr(PMG_IO_BASE_ADDR); - msr.lo = (PMB0 + 4) | (PMB1 << 16); + /* Set Processor MWAIT IO BASE (P_BLK) */ + msr.hi = 0; + // TODO Do we want PM1_BASE? Needs SMM? + //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); + msr.lo = ((PMB0_BASE + 4) & 0xffff); wrmsr(PMG_IO_BASE_ADDR, msr); - // set C_LVL controls - msr = rdmsr(PMG_IO_CAPTURE_ADDR); - msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted + /* set C_LVL controls */ + msr.hi = 0; + msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(PMG_IO_CAPTURE_ADDR, msr); }

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build service results for r6167
by repository service 12 Dec '10

12 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6167 to the coreboot repository. This caused the following changes: Change Log: Fix the build failure. We have now common fadt.c. [PATCH] SB700 common FADT was not applied to this board because it was in the meanwhile added. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Build Log: Compilation of asus:m4a78-em has been fixed Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6167&device=d945gclf&vendo… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6166
by repository service 12 Dec '10

12 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6166 to the coreboot repository. This caused the following changes: Change Log: I was bitten by the rename, this is part of r6165. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asus:m4a78-em is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6166&device=m4a78-em&vendo… Compilation of asus:m4a785-m has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of iei:kino-780am2-fam10 has been fixed Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6166&device=d945gclf&vendo… Compilation of jetway:pa78vm5 has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6165
by repository service 12 Dec '10

12 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6165 to the coreboot repository. This caused the following changes: Change Log: Following patch makes just one fadt.c file. For SB700. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=mahogany&vendo… Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=mahogany_fam10… Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=tilapia_fam10&… Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=939a785gmh&ven… Compilation of asus:m4a78-em has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=m4a78-em&vendo… Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=m4a785-m&vendo… Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=ma785gmt&vendo… Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=ma78gm&vendor=… Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=kino-780am2-fa… Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=d945gclf&vendo… Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6165&device=pa78vm5&vendor… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6167 - trunk/src/mainboard/asus/m4a78-em
by repository service 12 Dec '10

12 Dec '10

Author: ruik Date: Sun Dec 12 00:28:17 2010 New Revision: 6167 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6167 Log: Fix the build failure. We have now common fadt.c. [PATCH] SB700 common FADT was not applied to this board because it was in the meanwhile added. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Deleted: trunk/src/mainboard/asus/m4a78-em/fadt.c Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig Modified: trunk/src/mainboard/asus/m4a78-em/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a78-em/Kconfig Sat Dec 11 23:41:31 2010 (r6166) +++ trunk/src/mainboard/asus/m4a78-em/Kconfig Sun Dec 12 00:28:17 2010 (r6167) @@ -9,7 +9,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8712F - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE

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build service results for r6164
by repository service 12 Dec '10

12 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6164 to the coreboot repository. This caused the following changes: Change Log: factor out cpu power management base into a separate file. And fix a bug in model_1067x Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6164&device=d945gclf&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6166 - trunk/src/southbridge/amd/sb700
by repository service 11 Dec '10

11 Dec '10

Author: ruik Date: Sat Dec 11 23:41:31 2010 New Revision: 6166 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6166 Log: I was bitten by the rename, this is part of r6165. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/southbridge/amd/sb700/fadt.c Modified: trunk/src/southbridge/amd/sb700/Makefile.inc Modified: trunk/src/southbridge/amd/sb700/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/sb700/Makefile.inc Sat Dec 11 23:26:10 2010 (r6165) +++ trunk/src/southbridge/amd/sb700/Makefile.inc Sat Dec 11 23:41:31 2010 (r6166) @@ -6,6 +6,6 @@ driver-y += sata.c driver-y += hda.c driver-y += pci.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sb700_fadt.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-y += enable_usbdebug.c Added: trunk/src/southbridge/amd/sb700/fadt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sb700/fadt.c Sat Dec 11 23:41:31 2010 (r6166) @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include "sb700.h" + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB700_ACPI_IO_BASE); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pm_iowrite(0x26, ACPI_CPU_CONTROL & 0xFF); + pm_iowrite(0x27, ACPI_CPU_CONTROL >> 8); + + pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); + + pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 20-2B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +}

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[PATCH] SB700 common FADT
by Rudolf Marek 11 Dec '10

11 Dec '10

Following patch makes just one fadt.c file. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> svn remove src/./asus/m4a785-m/fadt.c svn remove src/./amd/mahogany/fadt.c svn remove src/./amd/mahogany_fam10/fadt.c svn remove src/./amd/tilapia_fam10/fadt.c svn remove src/./gigabyte/ma78gm/fadt.c svn remove src/./gigabyte/ma785gmt/fadt.c svn remove src/./jetway/pa78vm5/fadt.c svn remove src/./asrock/939a785gmh/fadt.c svn remove src/./iei/kino-780am2-fam10/fadt.c I think the init of IO can be moved more early so we can use it for suspend/resune. As well the IO should be reserved. Maybe next patch. Similar patch should be done for SB600. This patch is only compile tested I can test this on asrock next week. Thanks, Rudolf

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[commit] r6165 - in trunk/src: include mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh mainboard/asus/m4a785-m mainboard/gigabyte/ma785gm...
by repository service 11 Dec '10

11 Dec '10

Author: ruik Date: Sat Dec 11 23:26:10 2010 New Revision: 6165 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6165 Log: Following patch makes just one fadt.c file. For SB700. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/mainboard/amd/mahogany/fadt.c trunk/src/mainboard/amd/mahogany_fam10/fadt.c trunk/src/mainboard/amd/tilapia_fam10/fadt.c trunk/src/mainboard/asrock/939a785gmh/fadt.c trunk/src/mainboard/asus/m4a785-m/fadt.c trunk/src/mainboard/gigabyte/ma785gmt/fadt.c trunk/src/mainboard/gigabyte/ma78gm/fadt.c trunk/src/mainboard/iei/kino-780am2-fam10/fadt.c trunk/src/mainboard/jetway/pa78vm5/fadt.c Modified: trunk/src/include/cbmem.h trunk/src/mainboard/amd/mahogany/Kconfig trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany_fam10/Kconfig trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c trunk/src/mainboard/amd/tilapia_fam10/Kconfig trunk/src/mainboard/asrock/939a785gmh/Kconfig trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/asus/m4a785-m/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/Kconfig trunk/src/mainboard/gigabyte/ma78gm/Kconfig trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig trunk/src/mainboard/jetway/pa78vm5/Kconfig trunk/src/southbridge/amd/sb700/Makefile.inc trunk/src/southbridge/amd/sb700/sb700.h Modified: trunk/src/include/cbmem.h ============================================================================== --- trunk/src/include/cbmem.h Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/include/cbmem.h Sat Dec 11 23:26:10 2010 (r6165) @@ -48,6 +48,8 @@ void cbmem_list(void); void cbmem_arch_init(void); +#ifndef __PRE_RAM__ struct cbmem_entry *get_cbmem_toc(void); void set_cbmem_toc(struct cbmem_entry *); #endif +#endif Modified: trunk/src/mainboard/amd/mahogany/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/amd/mahogany/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F - select BOARD_HAS_FADT select HAVE_ACPI_TABLES select HAVE_MP_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Sat Dec 11 23:26:10 2010 (r6165) @@ -29,8 +29,7 @@ #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> - -extern u16 pm_base; +#include <southbridge/amd/sb700/sb700.h> #define DUMP_ACPI_TABLES 0 @@ -100,7 +99,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); return (unsigned long) (acpigen_get_current()); } Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Sat Dec 11 23:26:10 2010 (r6165) @@ -26,7 +26,6 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> - #include "mb_sysconf.h" #define DUMP_ACPI_TABLES 0 Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_WINBOND_W83627DHG - select BOARD_HAS_FADT select HAVE_ACPI_TABLES select HAVE_MP_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Sat Dec 11 23:26:10 2010 (r6165) @@ -29,8 +29,7 @@ #include "northbridge/amd/amdk8/acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> - -extern u16 pm_base; +#include <southbridge/amd/sb700/sb700.h> #define DUMP_ACPI_TABLES 0 @@ -100,7 +99,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); - amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); return (unsigned long) (acpigen_get_current()); } Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/asus/m4a785-m/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_SB700 select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_FINTEK_F71859 - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/Kconfig Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/mainboard/jetway/pa78vm5/Kconfig Sat Dec 11 23:26:10 2010 (r6165) @@ -10,7 +10,6 @@ select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_FINTEK_F71863FG - select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/southbridge/amd/sb700/Makefile.inc ============================================================================== --- trunk/src/southbridge/amd/sb700/Makefile.inc Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/southbridge/amd/sb700/Makefile.inc Sat Dec 11 23:26:10 2010 (r6165) @@ -6,5 +6,6 @@ driver-y += sata.c driver-y += hda.c driver-y += pci.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += sb700_fadt.c ramstage-y += reset.c romstage-y += enable_usbdebug.c Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Sat Dec 11 23:14:44 2010 (r6164) +++ trunk/src/southbridge/amd/sb700/sb700.h Sat Dec 11 23:26:10 2010 (r6165) @@ -29,6 +29,15 @@ #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 +#define SB700_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */ + extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); extern void pm2_iowrite(u8 reg, u8 value);

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[commit] r6164 - in trunk/src: cpu/intel/model_1067x cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/intel/speedstep include/cpu/intel
by repository service 11 Dec '10

11 Dec '10

Author: stepan Date: Sat Dec 11 23:14:44 2010 New Revision: 6164 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6164 Log: factor out cpu power management base into a separate file. And fix a bug in model_1067x Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Added: trunk/src/include/cpu/intel/speedstep.h Modified: trunk/src/cpu/intel/model_1067x/model_1067x_init.c trunk/src/cpu/intel/model_106cx/model_106cx_init.c trunk/src/cpu/intel/model_6ex/model_6ex_init.c trunk/src/cpu/intel/model_6fx/model_6fx_init.c trunk/src/cpu/intel/speedstep/acpi.c Modified: trunk/src/cpu/intel/model_1067x/model_1067x_init.c ============================================================================== --- trunk/src/cpu/intel/model_1067x/model_1067x_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_1067x/model_1067x_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -28,6 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -98,8 +99,6 @@ #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0_BASE 0x580 -#define PMB1_BASE 0x800 #define CST_RANGE 2 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/model_106cx/model_106cx_init.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -26,6 +26,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -82,9 +83,7 @@ #define PMG_CST_CONFIG_CONTROL 0xe2 #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */ -#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state. - See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */ + #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/model_6ex/model_6ex_init.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/model_6ex_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_6ex/model_6ex_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -29,6 +29,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -80,15 +81,6 @@ #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -/* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. - */ -#define PMB0_BASE 0x510 - -/* PMB1: I/O port that triggers SMI once cores are in the same state. - * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] - */ -#define PMB1_BASE 0x800 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/model_6fx/model_6fx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6fx/model_6fx_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_6fx/model_6fx_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -28,6 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -94,15 +95,6 @@ #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -/* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. - */ -#define PMB0_BASE 0x510 - -/* PMB1: I/O port that triggers SMI once cores are in the same state. - * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] - */ -#define PMB1_BASE 0x800 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/speedstep/acpi.c ============================================================================== --- trunk/src/cpu/intel/speedstep/acpi.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/speedstep/acpi.c Sat Dec 11 23:14:44 2010 (r6164) @@ -26,6 +26,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/acpi.h> +#include <cpu/intel/speedstep.h> #include <device/device.h> // XXX: PSS table values for power consumption are for Merom only @@ -64,7 +65,7 @@ void generate_cpu_entries(void) { int len_pr, len_ps; - int coreID, cpuID, pcontrol_blk=0x510, plen=6; + int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; msr_t msr; int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; Added: trunk/src/include/cpu/intel/speedstep.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/intel/speedstep.h Sat Dec 11 23:14:44 2010 (r6164) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 +

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coreboot December 2010