coreboot December 2010

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[commit] r6180 - in trunk/src/mainboard: gigabyte/m57sli msi/ms7260 msi/ms9282 msi/ms9652_fam10 supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_fam10 supermicro/h8qme_fam10 tyan/s2912 tyan/s2912...
by repository service 15 Dec '10

15 Dec '10

Author: uwe Date: Wed Dec 15 09:56:19 2010 New Revision: 6180 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6180 Log: Cleanup up HD audio codec / hda_verb.h files. Most of the current hda_verb.h files are identical (same MD5 sum) and are intended for a specific MCP55 board with the Realtek ALC880 audio codec, which has the vendor/device ID of 0x10ec0880. They were splitted out from the MCP55 southbridge code and put into board dirs a long time ago (which is correct, as those settings are indeed board-specific), but they were never adapted to those boards. Here's the table of which codec is soldered onto which board, based on checking the vendor website board spec pages, and the board manuals: - GIGABYTE GA-M57SLI-S4: Realtek ALC883 - MSI MS-7260: Realtek ALC883 - MSI MS-9652: Realtek ALC888 - MSI MS-9282: Server board, doesn't have audio at all - Tyan S2912: Server board, doesn't have audio at all - All Supermicro boards: Server boards, don't have audio at all - NVIDIA l1_2pvv: No public info to be found, but I assume this was the original MCP55 eval board for the port and it's probably has the Realtek ALC880 codec used in the original hda_verb.h. These are the codec vendor device/IDs involved: Realtek ALC880: 0x10ec0880 Realtek ALC883: 0x10ec0883 Realtek ALC888: 0x10ec0888 The following files are marked as incorrect / TODO, as the ID of the codec doesn't match and thus will never get actually used (you'll see "HDA: no verb!" or similar in the coreboot logs). Even if the ID matched, the rest of the table would be incorrect anyway because the values are highly board-specific. ./src/mainboard/gigabyte/m57sli/hda_verb.h ./src/mainboard/msi/ms9652_fam10/hda_verb.h ./src/mainboard/msi/ms9282/hda_verb.h The following files can be safely dropped as these are server boards and don't have HD audio (or other audio) at all: ./src/mainboard/supermicro/h8dmr/hda_verb.h ./src/mainboard/supermicro/h8qme_fam10/hda_verb.h ./src/mainboard/supermicro/h8dme/hda_verb.h ./src/mainboard/supermicro/h8dmr_fam10/hda_verb.h ./src/mainboard/tyan/s2912/hda_verb.h ./src/mainboard/tyan/s2912_fam10/hda_verb.h The following two are correct and can stay: ./src/mainboard/nvidia/l1_2pvv/hda_verb.h ./src/mainboard/getac/p470/hda_verb.h Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Deleted: trunk/src/mainboard/msi/ms7260/hda_verb.h trunk/src/mainboard/supermicro/h8dme/hda_verb.h trunk/src/mainboard/supermicro/h8dmr/hda_verb.h trunk/src/mainboard/supermicro/h8dmr_fam10/hda_verb.h trunk/src/mainboard/supermicro/h8qme_fam10/hda_verb.h trunk/src/mainboard/tyan/s2912/hda_verb.h trunk/src/mainboard/tyan/s2912_fam10/hda_verb.h Modified: trunk/src/mainboard/gigabyte/m57sli/hda_verb.h trunk/src/mainboard/msi/ms7260/mainboard.c trunk/src/mainboard/msi/ms9282/hda_verb.h trunk/src/mainboard/msi/ms9652_fam10/hda_verb.h trunk/src/mainboard/supermicro/h8dme/mainboard.c trunk/src/mainboard/supermicro/h8dmr/mainboard.c trunk/src/mainboard/supermicro/h8dmr_fam10/mainboard.c trunk/src/mainboard/supermicro/h8qme_fam10/mainboard.c trunk/src/mainboard/tyan/s2912/mainboard.c trunk/src/mainboard/tyan/s2912_fam10/mainboard.c Modified: trunk/src/mainboard/gigabyte/m57sli/hda_verb.h ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/hda_verb.h Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/gigabyte/m57sli/hda_verb.h Wed Dec 15 09:56:19 2010 (r6180) @@ -7,8 +7,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,83 +16,99 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * FIXME: This file is currently unused and incorrect for this board. + * Someone who owns the board should replace it with a correct one. */ static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor ID / Device ID + 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks - /* HDA Codec Subsystem ID Verb Table: 0x0000e601 */ + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ 0x00172001, 0x001721e6, 0x00172200, 0x00172300, + /* NID 0x14, FRONT-OUT-L/R */ 0x01471c10, 0x01471d44, 0x01471e01, 0x01471f01, - // 1 + + /* NID 0x15, SURR-OUT-L/R */ 0x01571c12, 0x01571d14, 0x01571e01, 0x01571f01, - // 2 + + /* NID 0x16, CEN/LFE-OUT */ 0x01671c11, 0x01671d60, 0x01671e01, 0x01671f01, - // 3 + + /* NID 0x17, SIDE-SURR-L/R */ 0x01771c14, 0x01771d20, 0x01771e01, 0x01771f01, - // 4 + + /* NID 0x18, MIC1-L/R, VREFO */ 0x01871c30, 0x01871d9c, 0x01871ea1, 0x01871f01, - // 5 + + /* NID 0x19, MIC2-L/R, VREFO */ 0x01971c40, 0x01971d9c, 0x01971ea1, 0x01971f02, - // 6 + + /* NID 0x1a, LINE1-L/R, VREFO */ 0x01a71c31, 0x01a71d34, 0x01a71e81, 0x01a71f01, - // 7 + + /* NID 0x1b, LINE2-L/R, VREFO */ 0x01b71c1f, 0x01b71d44, 0x01b71e21, 0x01b71f02, - // 8 + + /* NID 0x1c, CD-L/R / GND */ 0x01c71cf0, 0x01c71d11, 0x01c71e11, 0x01c71f41, - // 9 + + /* NID 0x1d, PCBEEP */ 0x01d71c3e, 0x01d71d01, 0x01d71e83, 0x01d71f99, - // 10 + + /* NID 0x1e, S/PDIF-OUT */ 0x01e71c20, 0x01e71d41, 0x01e71e45, 0x01e71f01, - // 11 + + /* NID 0x1f, S/PDIF-IN */ 0x01f71c50, 0x01f71d91, 0x01f71ec5, 0x01f71f01, }; -extern u32 * cim_verb_data; +extern u32 *cim_verb_data; extern u32 cim_verb_data_size; Modified: trunk/src/mainboard/msi/ms7260/mainboard.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/msi/ms7260/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -24,16 +24,15 @@ static void verb_setup(void) { - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); + // cim_verb_data = mainboard_cim_verb_data; + // cim_verb_data_size = sizeof(mainboard_cim_verb_data); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(device_t dev) { - verb_setup(); + // verb_setup(); } - struct chip_operations mainboard_ops = { CHIP_NAME("MSI K9N Neo (MS-7260) Mainboard") .enable_dev = mainboard_enable, Modified: trunk/src/mainboard/msi/ms9282/hda_verb.h ============================================================================== --- trunk/src/mainboard/msi/ms9282/hda_verb.h Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/msi/ms9282/hda_verb.h Wed Dec 15 09:56:19 2010 (r6180) @@ -7,8 +7,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,83 +16,99 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * FIXME: This file is currently unused and incorrect for this board. + * Someone who owns the board should replace it with a correct one. */ static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor ID / Device ID + 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks - /* HDA Codec Subsystem ID Verb Table: 0x0000e601 */ + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ 0x00172001, 0x001721e6, 0x00172200, 0x00172300, + /* NID 0x14, FRONT-OUT-L/R */ 0x01471c10, 0x01471d44, 0x01471e01, 0x01471f01, - // 1 + + /* NID 0x15, SURR-OUT-L/R */ 0x01571c12, 0x01571d14, 0x01571e01, 0x01571f01, - // 2 + + /* NID 0x16, CEN/LFE-OUT */ 0x01671c11, 0x01671d60, 0x01671e01, 0x01671f01, - // 3 + + /* NID 0x17, SIDE-SURR-L/R */ 0x01771c14, 0x01771d20, 0x01771e01, 0x01771f01, - // 4 + + /* NID 0x18, MIC1-L/R, VREFO */ 0x01871c30, 0x01871d9c, 0x01871ea1, 0x01871f01, - // 5 + + /* NID 0x19, MIC2-L/R, VREFO */ 0x01971c40, 0x01971d9c, 0x01971ea1, 0x01971f02, - // 6 + + /* NID 0x1a, LINE1-L/R, VREFO */ 0x01a71c31, 0x01a71d34, 0x01a71e81, 0x01a71f01, - // 7 + + /* NID 0x1b, LINE2-L/R, VREFO */ 0x01b71c1f, 0x01b71d44, 0x01b71e21, 0x01b71f02, - // 8 + + /* NID 0x1c, CD-L/R / GND */ 0x01c71cf0, 0x01c71d11, 0x01c71e11, 0x01c71f41, - // 9 + + /* NID 0x1d, PCBEEP */ 0x01d71c3e, 0x01d71d01, 0x01d71e83, 0x01d71f99, - // 10 + + /* NID 0x1e, S/PDIF-OUT */ 0x01e71c20, 0x01e71d41, 0x01e71e45, 0x01e71f01, - // 11 + + /* NID 0x1f, S/PDIF-IN */ 0x01f71c50, 0x01f71d91, 0x01f71ec5, 0x01f71f01, }; -extern u32 * cim_verb_data; +extern u32 *cim_verb_data; extern u32 cim_verb_data_size; Modified: trunk/src/mainboard/msi/ms9652_fam10/hda_verb.h ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/hda_verb.h Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/msi/ms9652_fam10/hda_verb.h Wed Dec 15 09:56:19 2010 (r6180) @@ -7,8 +7,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -17,83 +16,99 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * FIXME: This file is currently unused and incorrect for this board. + * Someone who owns the board should replace it with a correct one. */ static u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0880, // Codec Vendor ID / Device ID + 0x10ec0880, // Codec Vendor / Device ID: Realtek ALC880 0x00000000, // Subsystem ID 0x0000000d, // Number of jacks - /* HDA Codec Subsystem ID Verb Table: 0x0000e601 */ + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x0000e601 */ 0x00172001, 0x001721e6, 0x00172200, 0x00172300, + /* NID 0x14, FRONT-OUT-L/R */ 0x01471c10, 0x01471d44, 0x01471e01, 0x01471f01, - // 1 + + /* NID 0x15, SURR-OUT-L/R */ 0x01571c12, 0x01571d14, 0x01571e01, 0x01571f01, - // 2 + + /* NID 0x16, CEN/LFE-OUT */ 0x01671c11, 0x01671d60, 0x01671e01, 0x01671f01, - // 3 + + /* NID 0x17, SIDE-SURR-L/R */ 0x01771c14, 0x01771d20, 0x01771e01, 0x01771f01, - // 4 + + /* NID 0x18, MIC1-L/R, VREFO */ 0x01871c30, 0x01871d9c, 0x01871ea1, 0x01871f01, - // 5 + + /* NID 0x19, MIC2-L/R, VREFO */ 0x01971c40, 0x01971d9c, 0x01971ea1, 0x01971f02, - // 6 + + /* NID 0x1a, LINE1-L/R, VREFO */ 0x01a71c31, 0x01a71d34, 0x01a71e81, 0x01a71f01, - // 7 + + /* NID 0x1b, LINE2-L/R, VREFO */ 0x01b71c1f, 0x01b71d44, 0x01b71e21, 0x01b71f02, - // 8 + + /* NID 0x1c, CD-L/R / GND */ 0x01c71cf0, 0x01c71d11, 0x01c71e11, 0x01c71f41, - // 9 + + /* NID 0x1d, PCBEEP */ 0x01d71c3e, 0x01d71d01, 0x01d71e83, 0x01d71f99, - // 10 + + /* NID 0x1e, S/PDIF-OUT */ 0x01e71c20, 0x01e71d41, 0x01e71e45, 0x01e71f01, - // 11 + + /* NID 0x1f, S/PDIF-IN */ 0x01f71c50, 0x01f71d91, 0x01f71ec5, 0x01f71f01, }; -extern u32 * cim_verb_data; +extern u32 *cim_verb_data; extern u32 cim_verb_data_size; Modified: trunk/src/mainboard/supermicro/h8dme/mainboard.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/supermicro/h8dme/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -19,22 +19,8 @@ */ #include <device/device.h> -#include "hda_verb.h" #include "chip.h" -static void verb_setup(void) -{ - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); -} - -static void mainboard_enable(device_t dev) -{ - verb_setup(); -} - struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DME Mainboard") - .enable_dev = mainboard_enable, }; - Modified: trunk/src/mainboard/supermicro/h8dmr/mainboard.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/supermicro/h8dmr/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -19,26 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "hda_verb.h" #include "chip.h" -static void verb_setup(void) -{ - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); -} - -static void mainboard_enable(device_t dev) -{ - verb_setup(); -} - struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DMR Mainboard") - .enable_dev = mainboard_enable, }; Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -19,26 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "hda_verb.h" #include "chip.h" -static void verb_setup(void) -{ - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); -} - -static void mainboard_enable(device_t dev) -{ - verb_setup(); -} - struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DMR Mainboard (Family 10)") - .enable_dev = mainboard_enable, }; Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/supermicro/h8qme_fam10/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -19,26 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "hda_verb.h" #include "chip.h" -static void verb_setup(void) -{ - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); -} - -static void mainboard_enable(device_t dev) -{ - verb_setup(); -} - struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)") - .enable_dev = mainboard_enable, }; Modified: trunk/src/mainboard/tyan/s2912/mainboard.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/tyan/s2912/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -19,26 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "hda_verb.h" #include "chip.h" -static void verb_setup(void) -{ - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); -} - -static void mainboard_enable(device_t dev) -{ - verb_setup(); -} - struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2912 Mainboard") - .enable_dev = mainboard_enable, }; Modified: trunk/src/mainboard/tyan/s2912_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/mainboard.c Tue Dec 14 03:02:34 2010 (r6179) +++ trunk/src/mainboard/tyan/s2912_fam10/mainboard.c Wed Dec 15 09:56:19 2010 (r6180) @@ -19,26 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "hda_verb.h" #include "chip.h" -static void verb_setup(void) -{ - cim_verb_data = mainboard_cim_verb_data; - cim_verb_data_size = sizeof(mainboard_cim_verb_data); -} - -static void mainboard_enable(device_t dev) -{ - verb_setup(); -} - struct chip_operations mainboard_ops = { CHIP_NAME("Tyan S2912 Mainboard (Family 10)") - .enable_dev = mainboard_enable, };

1 0

[PATCH] exit from self-refresh on AMD K8 CPUs (pre revF)
by Rudolf Marek 14 Dec '10

14 Dec '10

Hello, Following patch adds support to bring out the memory out of self refresh when doing resume. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> The patch is based on my 2008 patch. Thanks, Rudolf

3 4

[patch 0/3] ASUS P2B S2/S3 sleep support
by Tobias Diedrich 14 Dec '10

14 Dec '10

Add support for S2/S3 sleep (resume from reset vector). Part1 adds the get_acpi_sleep_type() function to read the sleep type and sets acpi_slp_type. Part2 adds generic infrastructure to save a pointer to cbmem_toc in the ACPI memory area. This could also replace the vt8237 solution of using special nvram (which the I82371EB chipset doesn't have). Part3 adds the necessary code to save the memory area overwritten by ramstage into the reserved backup memory space. All three patches are abuild-tested and should be applied after the ssdt cpu generation patch (http://www.coreboot.org/pipermail/coreboot/2010-December/062229.html). I tested the complete stack on both the P2B board which I wrote it for and the amd am2 base M2V board to check that it doesn't break anything there. Keith: It should probably be rather simple to enable this on P2B-LS/P3B-F too if you'd like to test. Here is the serial log (cold boot, s3, poweroff). Note: While S5 poweroff works and does poweroff the power supply, S3 seems to still need some magic to really power off, even though we tell the chipset to go to S3 sleep. However investigating this will have to wait since I won't have access to these boards, starting tomorrow, for the next month or so. coreboot-4.0-r6132M Wed Dec 1 21:51:49 CET 2010 starting... Wakeup from ACPI sleep type S5 (PMCNTRL=0000) v_esp=000cffc8 testx = 5a5a5a5a resume_backup_memory=00000000 Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a After cache as ram disabled resume_backup_memory=00000000 Clearing initial memory region: Done Loading image. Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (212992 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r6132M Wed Dec 1 21:51:49 CET 2010 booting... clocks_per_usec: 502 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7190] ops PCI: 00:00.0 [8086/7190] enabled PCI: 00:01.0 [8086/7191] enabled PCI: 00:04.0 [8086/7110] bus ops PCI: 00:04.0 [8086/7110] enabled PCI: 00:04.1 [8086/7111] ops PCI: 00:04.1 [8086/7111] enabled PCI: 00:04.2 [8086/7112] ops PCI: 00:04.2 [8086/7112] enabled PCI: 00:04.3 [8086/7113] bus ops Wakeup from ACPI sleep type S5 (PMCNTRL=0000) PCI: 00:04.3 [8086/7113] enabled PCI: 00:09.0 [10ec/8169] enabled PCI: 00:0c.0 [102b/0519] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:04.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.9 enabled PNP: 03f0.a enabled PNP: 03f0.6 enabled scan_static_bus for PCI: 00:04.0 done scan_static_bus for PCI: 00:04.3 scan_static_bus for PCI: 00:04.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:0c.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:04.0 read_resources bus 0 link: 0 PNP: 03f0.8 missing read_resources PNP: 03f0.9 missing read_resources PCI: 00:04.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:0c.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 1200 index 14 PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:04.2 20 * [0x400 - 0x41f] io PCI: 00:04.1 20 * [0x420 - 0x42f] io PCI_DOMAIN: 0000 compute_resources_io: base: 430 size: 430 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:0c.0 14 * [0x10000000 - 0x107fffff] prefmem PCI: 00:09.0 30 * [0x10800000 - 0x1081ffff] mem PCI: 00:0c.0 30 * [0x10820000 - 0x1082ffff] mem PCI: 00:0c.0 10 * [0x10830000 - 0x10833fff] mem PCI: 00:09.0 14 * [0x10834000 - 0x108340ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 10834100 size: 10834100 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:04.0 constrain_resources: PNP: 03f0.0 constrain_resources: PNP: 03f0.1 constrain_resources: PNP: 03f0.2 constrain_resources: PNP: 03f0.3 constrain_resources: PNP: 03f0.5 constrain_resources: PNP: 03f0.7 constrain_resources: PNP: 03f0.8 constrain_resources: PNP: 03f0.9 constrain_resources: PNP: 03f0.a constrain_resources: PNP: 03f0.6 constrain_resources: PCI: 00:04.1 constrain_resources: PCI: 00:04.2 constrain_resources: PCI: 00:04.3 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0c.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit ff7fffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:430 align:8 gran:0 limit:e3ff Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:04.2 20 * [0x1400 - 0x141f] io Assigned: PCI: 00:04.1 20 * [0x1420 - 0x142f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1430 size: 430 align: 8 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:e3ff size:0 align:12 gran:12 limit:e3ff PCI: 00:01.0 allocate_resources_io: next_base: e3ff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10834100 align:28 gran:0 limit:ff7fffff Assigned: PCI: 00:00.0 10 * [0xe0000000 - 0xefffffff] prefmem Assigned: PCI: 00:0c.0 14 * [0xf0000000 - 0xf07fffff] prefmem Assigned: PCI: 00:09.0 30 * [0xf0800000 - 0xf081ffff] mem Assigned: PCI: 00:0c.0 30 * [0xf0820000 - 0xf082ffff] mem Assigned: PCI: 00:0c.0 10 * [0xf0830000 - 0xf0833fff] mem Assigned: PCI: 00:09.0 14 * [0xf0834000 - 0xf08340ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0834100 size: 10834100 align: 28 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_prefmem: next_base: ff7fffff size: 0 align: 20 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:ff7fffff size:0 align:20 gran:20 limit:ff7fffff PCI: 00:01.0 allocate_resources_mem: next_base: ff7fffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 Setting RAM size to 512 MB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000e3ff - 0x000000e3fe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00ff7fffff - 0x00ff7ffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:04.0 assign_resources, bus 0 link: 0 PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.1 74 drq size: 0x0000000001 not assigned PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq ERROR: PNP: 03f0.7 60 io size: 0x0000000001 not assigned ERROR: PNP: 03f0.7 62 io size: 0x0000000002 not assigned ERROR: PNP: 03f0.7 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.a 70 irq size: 0x0000000001 not assigned ERROR: PNP: 03f0.6 60 io size: 0x0000000008 not assigned ERROR: PNP: 03f0.6 70 irq size: 0x0000000001 not assigned PCI: 00:04.0 assign_resources, bus 0 link: 0 PCI: 00:04.1 20 <- [0x0000001420 - 0x000000142f] size 0x00000010 gran 0x04 io PCI: 00:04.2 20 <- [0x0000001400 - 0x000000141f] size 0x00000020 gran 0x05 io PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00f0834000 - 0x00f08340ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00f0800000 - 0x00f081ffff] size 0x00020000 gran 0x11 romem PCI: 00:0c.0 10 <- [0x00f0830000 - 0x00f0833fff] size 0x00004000 gran 0x0e mem PCI: 00:0c.0 14 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem PCI: 00:0c.0 30 <- [0x00f0820000 - 0x00f082ffff] size 0x00010000 gran 0x10 romem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 430 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base e0000000 size 10834100 align 28 gran 0 limit ff7fffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 28 gran 28 limit ff7fffff flags 60001200 index 10 PCI: 00:01.0 PCI: 00:01.0 resource base e3ff size 0 align 12 gran 12 limit e3ff flags 60080102 index 1c PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60081202 index 24 PCI: 00:01.0 resource base ff7fffff size 0 align 20 gran 20 limit ff7fffff flags 60080202 index 20 PCI: 00:04.0 child on link 0 PNP: 03f0.0 PCI: 00:04.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:04.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PNP: 03f0.0 PNP: 03f0.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 03f0.1 PNP: 03f0.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 03f0.2 PNP: 03f0.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.3 PNP: 03f0.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 03f0.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 PNP: 03f0.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 03f0.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 03f0.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 03f0.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 03f0.7 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 03f0.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 PNP: 03f0.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.8 PNP: 03f0.9 PNP: 03f0.a PNP: 03f0.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 03f0.6 PNP: 03f0.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 03f0.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PCI: 00:04.1 PCI: 00:04.1 resource base 1420 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:04.2 PCI: 00:04.2 resource base 1400 size 20 align 5 gran 5 limit e3ff flags 60000100 index 20 PCI: 00:04.3 PCI: 00:04.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:04.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:09.0 resource base f0834000 size 100 align 8 gran 8 limit ff7fffff flags 60000200 index 14 PCI: 00:09.0 resource base f0800000 size 20000 align 17 gran 17 limit ff7fffff flags 60002200 index 30 PCI: 00:0c.0 PCI: 00:0c.0 resource base f0830000 size 4000 align 14 gran 14 limit ff7fffff flags 60000200 index 10 PCI: 00:0c.0 resource base f0000000 size 800000 align 23 gran 23 limit ff7fffff flags 60001200 index 14 PCI: 00:0c.0 resource base f0820000 size 10000 align 16 gran 16 limit ff7fffff flags 60002200 index 30 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0083 PCI: 00:01.0 cmd <- 00 PCI: 00:04.0 cmd <- 07 PCI: 00:04.1 cmd <- 01 PCI: 00:04.2 cmd <- 01 PCI: 00:04.3 cmd <- 01 PCI: 00:09.0 cmd <- 03 PCI: 00:0c.0 cmd <- 83 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Intel device 672 CPU: family 06, model 07, stepping 02 microcode_info: sig = 0x00000672 pf=0x00000001 rev = 0x00000000 microcode updated to revision: 00000010 from revision 00000000 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 initialized PCI: 00:00.0 init Northbridge Init PCI: 00:04.0 init RTC Init PCI: 00:04.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: on IDE: Primary IDE interface, drive 0: UDMA/33: off IDE: Primary IDE interface, drive 1: UDMA/33: off IDE: Secondary IDE interface, drive 0: UDMA/33: off IDE: Secondary IDE interface, drive 1: UDMA/33: off PCI: 00:04.2 init PCI: 00:09.0 init PCI: 00:0c.0 init PNP: 03f0.0 init PNP: 03f0.1 init PNP: 03f0.2 init PNP: 03f0.3 init PNP: 03f0.5 init Keyboard init... Keyboard selftest failed ACK: 0xaa PNP: 03f0.7 init PNP: 03f0.a init PNP: 03f0.6 init Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:04.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.9: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:04.1: enabled 1 PCI: 00:04.2: enabled 1 PCI: 00:04.3: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0c.0: enabled 1 PNP: 03f0.6: enabled 1 CPU: 00: enabled 1 Initializing CBMEM area to 0x1feefc00 (1115136 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1feefe00...ok High Tables Base is 1feefc00. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1fef0000... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 3 ACPI: Writing ACPI tables at 1fef1000... ACPI: Writing cbmem_toc pointer at 1fef1024... ACPI: * FACS ACPI: * DSDT @ 1fef1140 Length 683 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * MADT ACPI: * SSDT Found 1 CPU(s). ACPI: added table 2/32, length now 44 ACPI: done. ACPI tables: 2354 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum 13ef New low_table_end: 0x00000518 Now going to write high coreboot table at 0x1fefcc00 rom_table_end = 0x1fefcc00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x1fefcc00 to 0x1ff00000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001feefbff: RAM 3. 000000001feefc00-000000001fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 1fefcc00 - 1fefcdbc checksum ad8c coreboot table: 444 bytes. Adding CBMEM entry as no. 5 Multiboot Information structure has been written. 0. FREE SPACE 1fffec00 00001400 1. GDT 1feefe00 00000200 2. IRQ TABLE 1fef0000 00001000 3. ACPI 1fef1000 0000bc00 4. COREBOOT 1fefcc00 00002000 5. ACPI RESUME1fefec00 00100000 Check CBFS header at fffffc9e magic is 4f524243 Found CBFS header at fffffc9e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 3699 + align -> fffc3700 Check fallback/coreboot_ram CBFS: follow chain: fffc3700 + 38 + 148bf + align -> fffd8000 Check fallback/payload Got a payload Loading segment from rom address 0xfffd8038 data (compression=1) New segment dstaddr 0xe9368 memsize 0x16c98 srcaddr 0xfffd8070 filesize 0xb69e (cleaned up) New segment addr 0xe9368 size 0x16c98 offset 0xfffd8070 filesize 0xb69e Loading segment from rom address 0xfffd8054 Entry Point 0x000fc9ef Loading Segment: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e lb: [0x0000000000100000, 0x0000000000134000) Post relocation: addr: 0x00000000000e9368 memsz: 0x0000000000016c98 filesz: 0x000000000000b69e using LZMA [ 0x000e9368, 00100000, 0x00100000) <- fffd8070 dest 000e9368, end 00100000, bouncebuffer 1fe87c00 Loaded segments Jumping to boot code at fc9ef entry = 0x000fc9ef lb_start = 0x00100000 lb_size = 0x00034000 adjust = 0x1fdbbc00 buffer = 0x1fe87c00 elf_boot_notes = 0x00124aa0 adjusted_boot_notes = 0x1fee06a0 Start bios (version pre-0.6.2-20101129_001420-nukunuku) Found mainboard ASUS P2B Found CBFS header at 0xfffffc9e Ram Size=0x1feefc00 (0x0000000000000000 high) Relocating init from 0x000e9800 to 0x1fed6500 (size 38360) CPU Mhz=501 No apic - only the main cpu is present. Copying PIR from 0x1fef0000 to 0x000fdc70 Copying ACPI RSDP from 0x1fef1000 to 0x000fdc50 SMBIOS ptr=0x000fdc30 table=0x1feefaf0 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version pre-0.6.2-20101129_001420-nukunuku) UHCI init on dev 00:04.2 (io=1400) Found 1 lpt ports Found 2 serial ports ATA controller 0 at 1f0/3f4/0 (irq 14 dev 21) ATA controller 1 at 170/374/0 (irq 15 dev 21) ata0-0: WDC WD1200JB-00DUA0 ATA-6 Hard-Disk (111 GiBytes) drive 0x000fdbe0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 ebda moved from 9fc00 to 9f800 USB mouse initialized Got ps2 nak (status=51) All threads complete. Scan for option roms Press F12 for boot menu. Returned 57344 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009f800 = 1 1: 000000000009f800 - 00000000000a0000 = 2 2: 00000000000f0000 - 0000000000100000 = 2 3: 0000000000100000 - 000000001feedc00 = 1 4: 000000001feedc00 - 0000000020000000 = 2 5: 00000000ff800000 - 0000000100000000 = 2 enter handle_19: NULL Booting from Floppy... Boot failed: could not read the boot disk enter handle_18: NULL Booting from DVD/CD... Boot failed: Could not read from CDROM (code 0001) enter handle_18: NULL Booting from Hard Disk... Booting from 0000:7c00 [ 0.000000] Linux version 2.6.35.8-netboot (ranma@nukunuku) (gcc version 4.4.5 (Debian 4.4.5-6) ) #55 Thu Nov 25 16:34:16 CET 2010 [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f800 (usable) [ 0.000000] BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000001feedc00 (usable) [ 0.000000] BIOS-e820: 000000001feedc00 - 0000000020000000 (reserved) [ 0.000000] BIOS-e820: 00000000ff800000 - 0000000100000000 (reserved) [ 0.000000] Notice: NX (Execute Disable) protection missing in CPU or disabled in BIOS! [ 0.000000] DMI 2.4 present. [ 0.000000] last_pfn = 0x1feed max_arch_pfn = 0x1000000 [ 0.000000] PAT not supported by CPU. [ 0.000000] get_mtrr(0): base hi=00000000 lo=00000006, mask hi=0000000f lo=e0000800 [ 0.000000] init_memory_mapping: 0000000000000000-000000001feed000 [ 0.000000] ACPI: RSDP 000fdc50 00014 (v00 CORE ) [ 0.000000] ACPI: RSDT 1fef102c 0002C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: FACP 1fef17c3 000F4 (v01 CORE COREBOOT 00000000 CORE 0000002A) [ 0.000000] ACPI: DSDT 1fef1140 00683 (v02 CORE COREBOOT 00000001 INTL 20100528) [ 0.000000] ACPI: FACS 1fef1100 00040 [ 0.000000] ACPI: SSDT 1fef18b7 0007B (v02 CORE DYNADATA 0000002A CORE 0000002A) [ 0.000000] 0MB HIGHMEM available. [ 0.000000] 510MB LOWMEM available. [ 0.000000] mapped low ram: 0 - 1feed000 [ 0.000000] low ram: 0 - 1feed000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000001 -> 0x00001000 [ 0.000000] Normal 0x00001000 -> 0x0001feed [ 0.000000] HighMem empty [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000001 -> 0x0000009f [ 0.000000] 0: 0x00000100 -> 0x0001feed [ 0.000000] Using APIC driver default [ 0.000000] ACPI: PM-Timer IO Port: 0xe408 [ 0.000000] Local APIC disabled by BIOS -- you can enable it with "lapic" [ 0.000000] APIC: disable apic facility [ 0.000000] APIC: switched to apic NOOP [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 [ 0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 [ 0.000000] Allocating PCI resources starting at 20000000 (gap: 20000000:df800000) [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 129677 [ 0.000000] Kernel command line: console=tty0 vga=ext root=/dev/sda2 ro radeon.modeset=1 console=ttyS0,115200 no_console_suspend video=matroxfb:off [ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Enabling fast FPU save and restore... done. [ 0.000000] Enabling unmasked SIMD FPU exception support... done. [ 0.000000] Initializing CPU#0 [ 0.000000] Subtract (24 early reservations) [ 0.000000] #0 [0001000000 - 00018314f4] TEXT DATA BSS [ 0.000000] #1 [000009f800 - 0000100000] BIOS reserved [ 0.000000] #2 [0001832000 - 0001840049] BRK [ 0.000000] #3 [0000001000 - 0000005000] ACPI WAKEUP [ 0.000000] #4 [0000007000 - 0000008000] PGTABLE [ 0.000000] #5 [0001841000 - 0001842000] BOOTMEM [ 0.000000] #6 [0001842000 - 0001c42000] BOOTMEM [ 0.000000] #7 [0001831500 - 0001831504] BOOTMEM [ 0.000000] #8 [0001831540 - 00018315c0] BOOTMEM [ 0.000000] #9 [00018315c0 - 00018315f0] BOOTMEM [ 0.000000] #10 [0001c42000 - 0001c43000] BOOTMEM [ 0.000000] #11 [0001831600 - 00018316fc] BOOTMEM [ 0.000000] #12 [0001831700 - 0001831740] BOOTMEM [ 0.000000] #13 [0001831740 - 0001831780] BOOTMEM [ 0.000000] #14 [0001831780 - 00018317c0] BOOTMEM [ 0.000000] #15 [00018317c0 - 0001831800] BOOTMEM [ 0.000000] #16 [0001831800 - 0001831840] BOOTMEM [ 0.000000] #17 [0001831840 - 0001831880] BOOTMEM [ 0.000000] #18 [0001831880 - 0001831890] BOOTMEM [ 0.000000] #19 [00018318c0 - 0001831933] BOOTMEM [ 0.000000] #20 [0001831940 - 00018319b3] BOOTMEM [ 0.000000] #21 [0001c43000 - 0001c45000] BOOTMEM [ 0.000000] #22 [0001c45000 - 0001c85000] BOOTMEM [ 0.000000] #23 [0001c85000 - 0001ca5000] BOOTMEM [ 0.000000] Initializing HighMem for node 0 (00000000:00000000) [ 0.000000] Memory: 509828k/523188k available (5091k kernel code, 12968k reserved, 2440k data, 356k init, 0k highmem) [ 0.000000] virtual kernel memory layout: [ 0.000000] fixmap : 0xfffa3000 - 0xfffff000 ( 368 kB) [ 0.000000] pkmap : 0xffc00000 - 0xffe00000 (2048 kB) [ 0.000000] vmalloc : 0xe06ed000 - 0xffbfe000 ( 501 MB) [ 0.000000] lowmem : 0xc0000000 - 0xdfeed000 ( 510 MB) [ 0.000000] .init : 0xc175c000 - 0xc17b5000 ( 356 kB) [ 0.000000] .data : 0xc14f8e35 - 0xc175afe4 (2440 kB) [ 0.000000] .text : 0xc1000000 - 0xc14f8e35 (5091 kB) [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU-based detection of stalled CPUs is disabled. [ 0.000000] Verbose stalled-CPUs detection is disabled. [ 0.000000] NR_IRQS:288 [ 0.000000] Console: colour VGA+ 80x50 [ 0.000000] console [tty0] enabled [ 0.000000] console [ttyS0] enabled [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 501.221 MHz processor. [ 0.020014] Calibrating delay loop (skipped), value calculated using timer frequency.. 1002.44 BogoMIPS (lpj=5012210) [ 0.033010] pid_max: default: 32768 minimum: 301 [ 0.040245] Mount-cache hash table entries: 512 [ 0.045477] CPU serial number disabled. [ 0.050037] mce: CPU supports 5 MCE banks [ 0.054251] Performance Events: [ 0.057342] no APIC, boot with the "lapic" boot parameter to force-enable it. [ 0.060024] no hardware sampling interrupt available. [ 0.070021] p6 PMU driver. [ 0.072926] ... version: 0 [ 0.077129] ... bit width: 32 [ 0.080022] ... generic registers: 2 [ 0.084244] ... value mask: 00000000ffffffff [ 0.090021] ... max period: 000000007fffffff [ 0.095478] ... fixed-purpose events: 0 [ 0.100020] ... event mask: 0000000000000003 [ 0.105533] CPU: Intel Pentium III (Katmai) stepping 02 [ 0.114924] ACPI: Core revision 20100428 [ 0.125968] ACPI: setting ELCR to 0200 (from 0000) [ 0.130032] ACPI: FADT smi_command is not set, mode transitions not supported. [ 0.137646] ACPI: SCI_EN status: 1 [ 0.140024] ACPI: FADT smi_command is not set, mode transitions not supported. [ 0.147644] ACPI: SCI_EN status: 1 [ 0.150841] devtmpfs: initialized [ 0.155904] NET: Registered protocol family 16 [ 0.163413] ACPI: bus type pci registered [ 0.171702] PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=1 [ 0.178271] PCI: Using configuration type 1 for base access [ 0.276065] bio: create slab <bio-0> at 0 [ 0.289230] ACPI: Interpreter enabled [ 0.290147] ACPI: (supports S0 S1 S2 S3 S5) [ 0.295061] ACPI: Using PIC for interrupt routing [ 0.319114] ACPI: No dock devices found. [ 0.320114] PCI: DMI: pci_use_crs=1 pci_probe=0000000b [ 0.325407] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.331781] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.343577] pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] [ 0.350113] pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] [ 0.360038] pci_root PNP0A03:00: host bridge window [mem 0x20000000-0xffffffff] [ 0.370566] * Found PM-Timer Bug on the chipset. Due to workarounds for a bug, [ 0.370574] * this clock source is slow. Consider trying other clock sources [ 0.380096] pci 0000:00:04.3: quirk: [io 0xe400-0xe43f] claimed by PIIX4 ACPI [ 0.390036] pci 0000:00:04.3: quirk: [io 0x0f00-0x0f0f] claimed by PIIX4 SMB [ 0.400527] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.417502] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.425108] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.435050] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.445057] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 12) *0, disabled. [ 0.455640] vgaarb: device added: PCI:0000:00:0c.0,decodes=io+mem,owns=io+mem,locks=none [ 0.460096] vgaarb: loaded [ 0.464385] SCSI subsystem initialized [ 0.472061] usbcore: registered new interface driver usbfs [ 0.480474] usbcore: registered new interface driver hub [ 0.486473] usbcore: registered new device driver usb [ 0.492657] Advanced Linux Sound Architecture Driver Version 1.0.23. [ 0.500422] PCI: Using ACPI for IRQ routing [ 0.506809] cfg80211: Calling CRDA to update world regulatory domain [ 0.510567] Switching to clocksource tsc [ 0.520250] pnp: PnP ACPI init [ 0.523568] ACPI: bus type pnp registered [ 0.530439] ERROR: Unable to locate IOAPIC for GSI 1 [ 0.536605] ERROR: Unable to locate IOAPIC for GSI 12 [ 0.542893] ERROR: Unable to locate IOAPIC for GSI 6 [ 0.550609] pnp: PnP ACPI: found 5 devices [ 0.554863] ACPI: ACPI bus type pnp unregistered [ 0.559822] system 00:04: [io 0xe400-0xe43f] has been reserved [ 0.565953] system 00:04: [io 0x0f00-0x0f0f] has been reserved [ 0.572157] system 00:04: [mem 0xff800000-0xffffffff] has been reserved [ 0.653284] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.658730] pci 0000:00:01.0: bridge window [io disabled] [ 0.664639] pci 0000:00:01.0: bridge window [mem disabled] [ 0.670550] pci 0000:00:01.0: bridge window [mem pref disabled] [ 0.677091] NET: Registered protocol family 2 [ 0.681913] IP route cache hash table entries: 4096 (order: 2, 16384 bytes) [ 0.689638] TCP established hash table entries: 16384 (order: 5, 131072 bytes) [ 0.697862] TCP bind hash table entries: 16384 (order: 4, 65536 bytes) [ 0.704980] TCP: Hash tables configured (established 16384 bind 16384) [ 0.711710] TCP reno registered [ 0.715075] UDP hash table entries: 256 (order: 0, 4096 bytes) [ 0.721180] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) [ 0.727928] NET: Registered protocol family 1 [ 0.732959] RPC: Registered udp transport module. [ 0.737875] RPC: Registered tcp transport module. [ 0.742935] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.749649] pci 0000:00:00.0: Limiting direct PCI/PCI transfers [ 0.756186] kvm: no hardware support [ 0.760076] has_svm: not amd [ 0.763161] kvm: no hardware support [ 0.768562] platform rtc_cmos: registered platform RTC device (no PNP device found) [ 0.783023] VFS: Disk quotas dquot_6.5.2 [ 0.787238] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.795198] fuse init (API version 7.14) [ 0.800786] Btrfs loaded [ 0.803572] msgmni has been set to 995 [ 0.809702] io scheduler noop registered [ 0.813838] io scheduler deadline registered [ 0.818385] io scheduler cfq registered (default) [ 0.827368] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0 [ 0.835241] ACPI: Power Button [PWRF] [ 1.387649] lp: driver loaded but no devices found [ 1.392977] Linux agpgart interface v0.103 [ 1.397556] agpgart-intel 0000:00:00.0: Intel 440BX Chipset [ 1.421908] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xe0000000 [ 1.430195] [drm] Initialized drm 1.1.0 20060810 [ 1.435404] [drm] radeon kernel modesetting enabled. [ 1.441523] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 1.448620] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 1.456233] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A [ 1.469916] parport0: PC-style at 0x378 (0x778) [PCSPP,TRISTATE,EPP] [ 1.477276] parport0: irq 7 detected [ 1.560065] lp0: using parport0 (polling). [ 1.573877] loop: module loaded [ 1.580950] scsi0 : ata_piix [ 1.585086] scsi1 : ata_piix [ 1.588981] ata1: PATA max UDMA/33 cmd 0x1f0 ctl 0x3f6 bmdma 0x1420 irq 14 [ 1.596158] ata2: PATA max UDMA/33 cmd 0x170 ctl 0x376 bmdma 0x1428 irq 15 [ 1.609413] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k6-NAPI [ 1.616678] e1000: Copyright (c) 1999-2006 Intel Corporation. [ 1.623186] e1000e: Intel(R) PRO/1000 Network Driver - 1.0.2-k4 [ 1.629395] e1000e: Copyright (c) 1999 - 2009 Intel Corporation. [ 1.637221] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI [ 1.643612] e100: Copyright(c) 1999-2006 Intel Corporation [ 1.654073] tun: Universal TUN/TAP device driver, 1.6 [ 1.659458] tun: (C) 1999-2004 Max Krasnyansky <maxk(a)qualcomm.com> [ 1.666843] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 1.674388] ACPI: PCI Interrupt Link [LNKD] enabled at IRQ 11 [ 1.689610] r8169 0000:00:09.0: PCI INT A -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11 [ 1.698168] r8169 0000:00:09.0: (unregistered net_device): no PCI Express capability [ 1.707107] r8169 0000:00:09.0: eth0: RTL8110s at 0xe0704000, 00:08:54:38:a1:44, XID 04000000 IRQ 11 [ 1.722213] console [netcon0] enabled [ 1.726084] netconsole: network logging started [ 1.730926] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.738046] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.744970] uhci_hcd: USB Universal Host Controller Interface driver [ 1.751812] uhci_hcd 0000:00:04.2: PCI INT D -> Link[LNKD] -> GSI 11 (level, low) -> IRQ 11 [ 1.760657] uhci_hcd 0000:00:04.2: UHCI Host Controller [ 1.766160] uhci_hcd 0000:00:04.2: new USB bus registered, assigned bus number 1 [ 1.774070] uhci_hcd 0000:00:04.2: irq 11, io base 0x00001400 [ 1.782234] hub 1-0:1.0: USB hub found [ 1.786230] hub 1-0:1.0: 2 ports detected [ 1.791224] Initializing USB Mass Storage driver... [ 1.796765] usbcore: registered new interface driver usb-storage [ 1.803095] USB Mass Storage support registered. [ 1.809199] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 [ 1.817389] ata1.00: ATA-6: WDC WD1200JB-00DUA0, 65.13G65, max UDMA/100 [ 1.824264] ata1.00: 234441648 sectors, multi 0: LBA48 [ 1.832453] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.837625] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.845732] mice: PS/2 mouse device common for all mice [ 1.853133] input: PC Speaker as /devices/platform/pcspkr/input/input1 [ 1.860802] rtc_cmos rtc_cmos: RTC can wake from S4 [ 1.866788] rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0 [ 1.873560] rtc0: alarms up to one month, 114 bytes nvram [ 1.879842] i2c /dev entries driver [ 1.883982] ata1.00: configured for UDMA/33 [ 1.889217] scsi 0:0:0:0: Direct-Access ATA WDC WD1200JB-00D 65.1 PQ: 0 ANSI: 5 [ 1.901906] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/111 GiB) [ 1.911646] piix4_smbus 0000:00:04.3: SMBus Host Controller at 0xf00, revision 0 [ 1.919817] input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input2 [ 1.928927] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 1.935157] sd 0:0:0:0: [sda] Write Protect is off [ 1.941860] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 1.955158] coretemp: CPU (model=0x7) has no thermal sensor. [ 1.961398] sda: sda1 sda2 sda3 < sda5 > sda4 [ 2.024169] sd 0:0:0:0: [sda] Attached SCSI disk [ 2.110100] usb 1-1: new low speed USB device using uhci_hcd and address 2 [ 2.342160] Software Watchdog Timer: 0.07 initialized. soft_noboot=0 soft_margin=60 sec (nowayout= 0) [ 2.351723] md: raid1 personality registered for level 1 [ 2.358459] device-mapper: ioctl: 4.17.0-ioctl (2010-03-05) initialised: dm-devel(a)redhat.com [ 2.367679] cpuidle: using governor ladder [ 2.372082] cpuidle: using governor menu [ 2.409011] input: Microsoft Microsoft 5-Button Mouse with IntelliEye(TM) as /devices/pci0000:00/0000:00:04.2/usb1/1-1/1-1:1.0/input/input3 [ 2.422751] generic-usb 0003:045E:0047.0001: input: USB HID v1.10 Mouse [Microsoft Microsoft 5-Button Mouse with IntelliEye(TM)] on usb-0000:00:04.2-1/input0 [ 2.437597] usbcore: registered new interface driver usbhid [ 2.443477] usbhid: USB HID core driver [ 2.447528] ramzswap: num_devices not specified. Using default: 1 [ 2.453864] ramzswap: Creating 1 devices ... [ 2.462241] ALSA device list: [ 2.465365] No soundcards found. [ 2.468987] u32 classifier [ 2.471991] Actions configured [ 2.475612] Netfilter messages via NETLINK v0.30. [ 2.480650] nf_conntrack version 0.5.0 (7966 buckets, 31864 max) [ 2.487494] ctnetlink v0.93: registering with nfnetlink. [ 2.493259] IPv4 over IPv4 tunneling driver [ 2.498974] ip_tables: (C) 2000-2006 Netfilter Core Team [ 2.504777] TCP bic registered [ 2.507995] TCP cubic registered [ 2.511487] TCP westwood registered [ 2.515183] TCP vegas registered [ 2.518837] NET: Registered protocol family 10 [ 2.525549] ip6_tables: (C) 2000-2006 Netfilter Core Team [ 2.531403] IPv6 over IPv4 tunneling driver [ 2.537852] NET: Registered protocol family 17 [ 2.542668] lib80211: common routines for IEEE802.11 drivers [ 2.548627] Using IPI Shortcut mode [ 2.555356] rtc_cmos rtc_cmos: setting system clock to 2010-12-01 21:56:43 UTC (1291240603) [ 2.564577] md: Waiting for all devices to be available before autodetect [ 2.571727] md: If you don't use raid, use raid=noautodetect [ 2.578890] md: Autodetecting RAID arrays. [ 2.583339] md: Scanned 0 and added 0 devices. [ 2.588039] md: autorun ... [ 2.591107] md: ... autorun DONE. [ 2.623263] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null) [ 2.631628] VFS: Mounted root (ext2 filesystem) readonly on device 8:2. [ 2.655607] devtmpfs: mounted [ 2.658915] Freeing unused kernel memory: 356k freed [ 2.666126] Write protecting the kernel text: 5092k [ 2.671612] Write protecting the kernel read-only data: 1896k INIT: version 2.88 booting booting... Starting the hotplug events dispatcher: udevd[ 4.537857] udev[1260]: starting version 163

6 15

IDE and Compact Flash handling in AMD Geode LX800 and CS5536
by Darmawan Salihun 14 Dec '10

14 Dec '10

Hi, I'm working on an AMD LX800-CS5536 board. The IRQ is now working properly. However, it's impossible to install an operating system through the IDE interface or the Compact Flash (CF) interface. Booting to the OS installation works just fine (Ubuntu Hardy Heron Linux and FreeBSD 8.0 and 8.1). However, when the OS arrived at the HDD partitioning. it always failed. There's a CF interface and an IDE interface on the board. My question is: how those interfaces usually connected to CS5536 southbridge? Are they multiplexed? Thanks in advance, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

3 4

[PATCH] Set the register based on the ROMSIZE
by Bao, Zheng 14 Dec '10

14 Dec '10

Set the register based on the ROMSIZE. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/southbridge/amd/sb600/Kconfig =================================================================== --- src/southbridge/amd/sb600/Kconfig (revision 6159) +++ src/southbridge/amd/sb600/Kconfig (working copy) @@ -23,6 +23,11 @@ select HAVE_USBDEBUG select TINY_BOOTBLOCK +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb600/bootblock.c" + depends on SOUTHBRIDGE_AMD_SB600 + config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 Index: src/southbridge/amd/sb600/bootblock.c =================================================================== --- src/southbridge/amd/sb600/bootblock.c (revision 6159) +++ src/southbridge/amd/sb600/bootblock.c (working copy) @@ -59,7 +59,15 @@ * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ + #if CONFIG_COREBOOT_ROMSIZE_KB_512 || CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128 + pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */ + #elif CONFIG_COREBOOT_ROMSIZE_KB_1024 + pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */ + #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 + pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */ + #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + #endif /* Enable LPC ROM range end at 0xffff(ffff). */ pci_write_config16(dev, 0x6e, 0xffff); } Index: src/southbridge/amd/sb700/Kconfig =================================================================== --- src/southbridge/amd/sb700/Kconfig (revision 6159) +++ src/southbridge/amd/sb700/Kconfig (working copy) @@ -23,6 +23,11 @@ select HAVE_USBDEBUG select TINY_BOOTBLOCK +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb700/bootblock.c" + depends on SOUTHBRIDGE_AMD_SB700 + config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n Index: src/southbridge/amd/sb700/bootblock.c =================================================================== --- src/southbridge/amd/sb700/bootblock.c (revision 6159) +++ src/southbridge/amd/sb700/bootblock.c (working copy) @@ -28,7 +28,7 @@ * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * - * The SB700 power-on default is to map 256K ROM space. + * The SB700 power-on default is to map 512K ROM space. * * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00, * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. @@ -57,8 +57,18 @@ * Enable LPC ROM range start at: * 0xfff8(0000): 512KB * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB */ + #if CONFIG_COREBOOT_ROMSIZE_KB_512 || CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128 + pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */ + #elif CONFIG_COREBOOT_ROMSIZE_KB_1024 pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */ + #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 + pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */ + #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + #endif /* Enable LPC ROM range end at 0xffff(ffff). */ pci_write_config16(dev, 0x6e, 0xffff); }

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[commit] r6179 - trunk/util/superiotool
by repository service 14 Dec '10

14 Dec '10

Author: zbao Date: Tue Dec 14 03:02:34 2010 New Revision: 6179 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6179 Log: Add dump support for the Winbond/Nuvoton W83527HG. The datasheet is available on nuvoton's website. http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx? tp_GUID=cf73485c-9e0a-4218-9bee-89dfe9a7bb87 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/winbond.c Modified: trunk/util/superiotool/winbond.c ============================================================================== --- trunk/util/superiotool/winbond.c Tue Dec 14 02:47:18 2010 (r6178) +++ trunk/util/superiotool/winbond.c Tue Dec 14 03:02:34 2010 (r6179) @@ -345,6 +345,30 @@ {EOT}}}, {0xb07, "W83527HG", { /* TODO: Not yet in sensors-detect */ + {NOLDN, NULL, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, + 0x2a,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0xB0,0x73,0xff,0x00,MISC,0x00,0x00,0x50,0x00, + 0x00,0xe2,0x21,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}}, + {0x8, "Watchdog timer", + {0x30,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x9, "GPIO 2, GPIO3, GPIO5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9, + 0xf0,0xf1,0xf2,0xf3,0xf8,0xf9,0xfa,0xfe,EOT}, + {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "ACPI", + {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x00,0x00,0x00,0x00,NANA,NANA,0x00,0x00,0x1c,0x00, + 0x7c,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xb, "Hardware monitor", + {0x30,0x60,0x61,0x70,0xf0,0xf2,EOT}, + {0x00,0x00,0x00,0x00,0x81,0x00,EOT}}, {EOT}}}, /* ID only */ {0x52, "W83627HF/F/HG/G", {

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[commit] r6178 - in trunk/src/southbridge/amd: sb600 sb700
by repository service 14 Dec '10

14 Dec '10

Author: zbao Date: Tue Dec 14 02:47:18 2010 New Revision: 6178 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6178 Log: Set the ROMSIZE as 4MB. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/amd/sb600/Kconfig trunk/src/southbridge/amd/sb700/Kconfig trunk/src/southbridge/amd/sb700/bootblock.c Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Mon Dec 13 23:16:45 2010 (r6177) +++ trunk/src/southbridge/amd/sb600/Kconfig Tue Dec 14 02:47:18 2010 (r6178) @@ -23,6 +23,11 @@ select HAVE_USBDEBUG select TINY_BOOTBLOCK +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb600/bootblock.c" + depends on SOUTHBRIDGE_AMD_SB600 + config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_AMD_SB600 Modified: trunk/src/southbridge/amd/sb700/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb700/Kconfig Mon Dec 13 23:16:45 2010 (r6177) +++ trunk/src/southbridge/amd/sb700/Kconfig Tue Dec 14 02:47:18 2010 (r6178) @@ -23,6 +23,11 @@ select HAVE_USBDEBUG select TINY_BOOTBLOCK +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb700/bootblock.c" + depends on SOUTHBRIDGE_AMD_SB700 + config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n Modified: trunk/src/southbridge/amd/sb700/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/sb700/bootblock.c Mon Dec 13 23:16:45 2010 (r6177) +++ trunk/src/southbridge/amd/sb700/bootblock.c Tue Dec 14 02:47:18 2010 (r6178) @@ -23,12 +23,12 @@ #include <device/pci_ids.h> /* - * Enable 1MB (LPC) ROM access at 0xFFF00000 - 0xFFFFFFFF. + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. * * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * - * The SB700 power-on default is to map 256K ROM space. + * The SB700 power-on default is to map 512K ROM space. * * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00, * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. @@ -39,7 +39,7 @@ device_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB700_LPC), 0); + PCI_DEVICE_ID_ATI_SB700_LPC), 0); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_read_config8(dev, 0x48); @@ -57,8 +57,10 @@ * Enable LPC ROM range start at: * 0xfff8(0000): 512KB * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */ + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ /* Enable LPC ROM range end at 0xffff(ffff). */ pci_write_config16(dev, 0x6e, 0xffff); }

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build service results for r6174
by repository service 13 Dec '10

13 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6174 to the coreboot repository. This caused the following changes: Change Log: Compile cbmem.c instead of including it in romstage, and do that only if resume is done. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Build Log: Compilation of amd:mahogany has been fixed Compilation of amd:mahogany_fam10 has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of asrock:939a785gmh has been fixed Compilation of asus:a8v-e_deluxe has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of asus:m4a78-em has been fixed Compilation of asus:m4a785-m has been fixed Compilation of getac:p470 has been fixed Compilation of gigabyte:ma785gmt has been fixed Compilation of gigabyte:ma78gm has been fixed Compilation of ibase:mb899 has been fixed Compilation of iei:kino-780am2-fam10 has been fixed Compilation of intel:d945gclf has been fixed Compilation of jetway:pa78vm5 has been fixed Compilation of kontron:986lcd-m has been fixed Compilation of roda:rk886ex has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6177 - trunk/src/mainboard/msi/ms9652_fam10
by repository service 13 Dec '10

13 Dec '10

Author: stepan Date: Mon Dec 13 23:16:45 2010 New Revision: 6177 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6177 Log: no leading zeroes. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Dec 13 21:43:33 2010 (r6176) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Dec 13 23:16:45 2010 (r6177) @@ -97,7 +97,7 @@ config RAMBASE hex - default 0x00200000 + default 0x200000 config TTYS0_BAUD int

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[commit] r6171 - in trunk/src: include lib mainboard/emulation/qemu-x86 northbridge/amd/amdfam10 northbridge/amd/amdk8 northbridge/amd/gx1 northbridge/amd/gx2 northbridge/amd/lx northbridge/intel/e...
by repository service 13 Dec '10

13 Dec '10

Author: ruik Date: Mon Dec 13 20:50:25 2010 New Revision: 6171 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6171 Log: We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic. Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/include/cbmem.h trunk/src/lib/cbmem.c trunk/src/mainboard/emulation/qemu-x86/northbridge.c trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/northbridge/amd/gx1/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/lx/northbridge.c trunk/src/northbridge/intel/e7501/northbridge.c trunk/src/northbridge/intel/e7520/northbridge.c trunk/src/northbridge/intel/e7525/northbridge.c trunk/src/northbridge/intel/i3100/northbridge.c trunk/src/northbridge/intel/i440bx/northbridge.c trunk/src/northbridge/intel/i440lx/northbridge.c trunk/src/northbridge/intel/i82810/northbridge.c trunk/src/northbridge/intel/i82830/northbridge.c trunk/src/northbridge/intel/i855/northbridge.c trunk/src/northbridge/intel/i945/northbridge.c trunk/src/northbridge/via/cn400/northbridge.c trunk/src/northbridge/via/cn700/northbridge.c trunk/src/northbridge/via/cx700/northbridge.c trunk/src/northbridge/via/vt8601/northbridge.c trunk/src/northbridge/via/vt8623/northbridge.c Modified: trunk/src/include/cbmem.h ============================================================================== --- trunk/src/include/cbmem.h Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/include/cbmem.h Mon Dec 13 20:50:25 2010 (r6171) @@ -21,13 +21,14 @@ #define _CBMEM_H_ /* Reserve 64k for ACPI and other tables */ -#define HIGH_MEMORY_TABLES ( 64 * 1024 ) +#define HIGH_MEMORY_DEF_SIZE ( 64 * 1024 ) +extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_TABLES) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_TABLES ) +#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) +#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) #else -#define HIGH_MEMORY_SIZE HIGH_MEMORY_TABLES +#define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE #endif #define CBMEM_ID_FREESPACE 0x46524545 Modified: trunk/src/lib/cbmem.c ============================================================================== --- trunk/src/lib/cbmem.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/lib/cbmem.c Mon Dec 13 20:50:25 2010 (r6171) @@ -193,7 +193,6 @@ #if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif -extern uint64_t high_tables_base, high_tables_size; void cbmem_initialize(void) { Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -11,8 +11,7 @@ #include <delay.h> #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif #define CMOS_ADDR_PORT 0x70 @@ -49,8 +48,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif assign_resources(dev->link_list); Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -841,8 +841,7 @@ #endif #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif #if CONFIG_GFXUMA == 1 @@ -1033,13 +1032,13 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_MEMORY_SIZE / 1024, high_tables_base); } #endif } @@ -1078,11 +1077,11 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -820,8 +820,6 @@ #if CONFIG_WRITE_HIGH_TABLES==1 #include <cbmem.h> -#define HIGH_TABLES_SIZE ((HIGH_MEMORY_SIZE + 1024) / 1024) -extern uint64_t high_tables_base, high_tables_size; #endif #if CONFIG_GFXUMA == 1 @@ -1020,13 +1018,13 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_MEMORY_SIZE / 1024, high_tables_base); } #endif } @@ -1065,11 +1063,11 @@ if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } Modified: trunk/src/northbridge/amd/gx1/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx1/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/amd/gx1/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -67,8 +67,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -116,8 +115,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif /* Report the memory regions */ Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/amd/gx2/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -432,8 +432,7 @@ void chipsetInit (void); #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void enable_dev(struct device *dev) @@ -457,8 +456,8 @@ tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif ram_resource(dev, 0, 0, tomk); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { Modified: trunk/src/northbridge/amd/lx/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/amd/lx/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -373,8 +373,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -396,8 +395,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } Modified: trunk/src/northbridge/intel/e7501/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7501/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/e7501/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -10,8 +10,7 @@ #include "chip.h" #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -92,8 +91,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/e7520/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7520/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/e7520/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -17,8 +17,7 @@ static unsigned int max_bus; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -111,8 +110,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/e7525/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/e7525/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/e7525/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -17,8 +17,7 @@ static unsigned int max_bus; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -111,8 +110,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/i3100/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i3100/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i3100/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -38,8 +38,7 @@ static u32 max_bus; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -132,8 +131,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/i440bx/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i440bx/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -34,8 +34,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void i440bx_domain_set_resources(device_t dev) @@ -75,8 +74,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/i440lx/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i440lx/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i440lx/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -63,8 +63,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void i440lx_domain_set_resources(device_t dev) @@ -104,8 +103,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/i82810/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82810/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i82810/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -84,8 +84,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -150,8 +149,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif assign_resources(dev->link_list); } Modified: trunk/src/northbridge/intel/i82830/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82830/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i82830/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -65,8 +65,7 @@ } #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) { @@ -119,8 +118,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } Modified: trunk/src/northbridge/intel/i855/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i855/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i855/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -54,8 +54,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) { @@ -112,8 +111,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } assign_resources(dev->link_list); Modified: trunk/src/northbridge/intel/i945/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i945/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/intel/i945/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -93,8 +93,7 @@ } #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -183,8 +182,8 @@ #if CONFIG_WRITE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; #endif } Modified: trunk/src/northbridge/via/cn400/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn400/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/via/cn400/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -178,9 +178,7 @@ #endif #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void cn400_domain_set_resources(device_t dev) @@ -211,9 +209,10 @@ #if CONFIG_WRITE_HIGH_TABLES == 1 /* Locate the High Tables at the Top of Low Memory below the Video RAM */ - high_tables_base = (uint64_t) (tolmk - (CONFIG_VIDEO_MB *1024) - HIGH_TABLES_SIZE) * 1024; - high_tables_size = (uint64_t) HIGH_TABLES_SIZE* 1024; - printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions. */ Modified: trunk/src/northbridge/via/cn700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn700/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/via/cn700/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -98,9 +98,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -141,9 +139,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - CONFIG_VIDEO_MB * 1024 - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions. */ Modified: trunk/src/northbridge/via/cx700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cx700/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/via/cx700/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -33,9 +33,7 @@ #include "northbridge.h" #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -77,9 +75,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */ Modified: trunk/src/northbridge/via/vt8601/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8601/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/via/vt8601/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -46,9 +46,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -92,9 +90,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */ Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Mon Dec 13 14:44:33 2010 (r6170) +++ trunk/src/northbridge/via/vt8623/northbridge.c Mon Dec 13 20:50:25 2010 (r6171) @@ -106,9 +106,7 @@ }; #if CONFIG_WRITE_HIGH_TABLES==1 -/* maximum size of high tables in KB */ -#define HIGH_TABLES_SIZE 64 -extern uint64_t high_tables_base, high_tables_size; +#include <cbmem.h> #endif static void pci_domain_set_resources(device_t dev) @@ -152,9 +150,10 @@ } #if CONFIG_WRITE_HIGH_TABLES == 1 - high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE* 1024; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); + high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", + tomk*1024, high_tables_base, high_tables_size); #endif /* Report the memory regions */

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coreboot December 2010