coreboot December 2010

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[commit] r6173 - in trunk/src: lib northbridge/intel/i945 southbridge/amd/sb700 southbridge/via/k8t890
by repository service 13 Dec '10

13 Dec '10

Author: ruik Date: Mon Dec 13 20:59:13 2010 New Revision: 6173 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6173 Log: Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well. The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/lib/cbmem.c trunk/src/northbridge/intel/i945/raminit.c trunk/src/northbridge/intel/i945/raminit.h trunk/src/southbridge/amd/sb700/early_setup.c trunk/src/southbridge/amd/sb700/fadt.c trunk/src/southbridge/amd/sb700/lpc.c trunk/src/southbridge/amd/sb700/sb700.h trunk/src/southbridge/via/k8t890/early_car.c Modified: trunk/src/lib/cbmem.c ============================================================================== --- trunk/src/lib/cbmem.c Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/lib/cbmem.c Mon Dec 13 20:59:13 2010 (r6173) @@ -36,20 +36,7 @@ u64 size; } __attribute__((packed)); - -#ifdef __PRE_RAM__ - -/* note this should be done as weak function but we do #include - of C files in the romstage breaking this (in same compile - unit is weak and non weak function -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) -*/ -#ifndef get_cbmem_toc - #define get_cbmem_toc() (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE) -#endif - -#else - +#ifndef __PRE_RAM__ static struct cbmem_entry *bss_cbmem_toc; struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/northbridge/intel/i945/raminit.c Mon Dec 13 20:59:13 2010 (r6173) @@ -26,6 +26,11 @@ #include <arch/romcc_io.h> #include "raminit.h" #include "i945.h" +#include <cbmem.h> + +struct cbmem_entry *get_cbmem_toc(void) { + return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); +} /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP Modified: trunk/src/northbridge/intel/i945/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.h Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/northbridge/intel/i945/raminit.h Mon Dec 13 20:59:13 2010 (r6173) @@ -71,5 +71,4 @@ unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us); - #endif /* RAMINIT_H */ Modified: trunk/src/southbridge/amd/sb700/early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/early_setup.c Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/southbridge/amd/sb700/early_setup.c Mon Dec 13 20:59:13 2010 (r6173) @@ -22,6 +22,7 @@ #include <reset.h> #include <arch/cpu.h> +#include <cbmem.h> #include "sb700.h" #include "smbus.c" @@ -40,6 +41,33 @@ return inb(PM_INDEX + 1); } +static void sb700_acpi_init(void) { + pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF); + pmio_write(0x21, ACPI_PM_EVT_BLK >> 8); + pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF); + pmio_write(0x23, ACPI_PM1_CNT_BLK >> 8); + pmio_write(0x24, ACPI_PM_TMR_BLK & 0xFF); + pmio_write(0x25, ACPI_PM_TMR_BLK >> 8); + pmio_write(0x28, ACPI_GPE0_BLK & 0xFF); + pmio_write(0x29, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pmio_write(0x26, ACPI_CPU_CONTROL & 0xFF); + pmio_write(0x27, ACPI_CPU_CONTROL >> 8); + + pmio_write(0x2A, 0); /* AcpiSmiCmdLo */ + pmio_write(0x2B, 0); /* AcpiSmiCmdHi */ + + pmio_write(0x2C, ACPI_PMA_CNT_BLK & 0xFF); + pmio_write(0x2D, ACPI_PMA_CNT_BLK >> 8); + + pmio_write(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 20-2B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + pmio_write(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ +} + /* RPR 2.28: Get SB ASIC Revision. */ static u8 set_sb700_revision(void) { @@ -588,10 +616,61 @@ { printk(BIOS_INFO, "sb700_early_setup()\n"); sb700_por_init(); + sb700_acpi_init(); } static int smbus_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } + +int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { + int i; + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + + for (i = 0; i<size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } + + return nvram_pos; +} + +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { + u32 data = *old_dword; + int i; + for (i = 0; i<size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + data &= ~(0xff << (i * 8)); + data |= inb(BIOSRAM_DATA) << (i *8); + nvram_pos++; + } + *old_dword = data; + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, + nvram_pos-size); + return nvram_pos; +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 +static int acpi_is_wakeup_early(void) { + u16 tmp; + tmp = inw(ACPI_PM1_CNT_BLK); + printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); + return (((tmp & (7 << 10)) >> 10) == 3); +} +#endif + +struct cbmem_entry *get_cbmem_toc(void) { + uint32_t xdata = 0; + int xnvram_pos = 0xfc, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} + #endif Modified: trunk/src/southbridge/amd/sb700/fadt.c ============================================================================== --- trunk/src/southbridge/amd/sb700/fadt.c Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/southbridge/amd/sb700/fadt.c Mon Dec 13 20:59:13 2010 (r6173) @@ -55,33 +55,6 @@ fadt->acpi_disable = 0xf1; fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - - pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x26, ACPI_CPU_CONTROL & 0xFF); - pm_iowrite(0x27, ACPI_CPU_CONTROL >> 8); - - pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 20-2B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ - pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; Modified: trunk/src/southbridge/amd/sb700/lpc.c ============================================================================== --- trunk/src/southbridge/amd/sb700/lpc.c Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/southbridge/amd/sb700/lpc.c Mon Dec 13 20:59:13 2010 (r6173) @@ -28,6 +28,7 @@ #include <bitops.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <cbmem.h> #include "sb700.h" static void lpc_init(device_t dev) @@ -63,6 +64,27 @@ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); + + /* hack, but the whole sb700 startup lacks any device which + is doing the acpi init */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + { + extern u8 acpi_slp_type; + u16 tmp = inw(ACPI_PM1_CNT_BLK); + acpi_slp_type = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); + } +#endif +} + +void set_cbmem_toc(struct cbmem_entry *toc) { + u32 dword = (u32) toc; + int nvram_pos = 0xfc, i; + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } } static void sb700_lpc_read_resources(device_t dev) Modified: trunk/src/southbridge/amd/sb700/sb700.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700.h Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/southbridge/amd/sb700/sb700.h Mon Dec 13 20:59:13 2010 (r6173) @@ -24,6 +24,8 @@ #include "chip.h" /* Power management index/data registers */ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 #define PM_INDEX 0xcd6 #define PM_DATA 0xcd7 #define PM2_INDEX 0xcd0 @@ -68,5 +70,8 @@ #endif +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); + void sb700_enable_usbdebug(unsigned int port); #endif /* SB700_H */ Modified: trunk/src/southbridge/via/k8t890/early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/early_car.c Mon Dec 13 20:53:58 2010 (r6172) +++ trunk/src/southbridge/via/k8t890/early_car.c Mon Dec 13 20:59:13 2010 (r6173) @@ -154,8 +154,6 @@ return nvram_pos; } -/* this should be a function struct cbmem_entry *get_cbmem_toc(void) { -*/ - -#define get_cbmem_toc() ((struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC)) + return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +}

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build service results for r6173
by repository service 13 Dec '10

13 Dec '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6173 to the coreboot repository. This caused the following changes: Change Log: Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well. The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:mahogany has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=mahogany&vendo… Compilation of amd:mahogany_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=mahogany_fam10… Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=tilapia_fam10&… Compilation of asrock:939a785gmh has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=939a785gmh&ven… Compilation of asus:a8v-e_deluxe has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=a8v-e_deluxe&v… Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=a8v-e_se&vendo… Compilation of asus:m2v has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m2v&vendor=asu… Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m2v-mx_se&vend… Compilation of asus:m4a78-em has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m4a78-em&vendo… Compilation of asus:m4a785-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=m4a785-m&vendo… Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=p470&vendor=ge… Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=ma785gmt&vendo… Compilation of gigabyte:ma78gm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=ma78gm&vendor=… Compilation of ibase:mb899 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=mb899&vendor=i… Compilation of iei:kino-780am2-fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=kino-780am2-fa… Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=d945gclf&vendo… Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=pa78vm5&vendor… Compilation of kontron:986lcd-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=986lcd-m&vendo… Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6173&device=rk886ex&vendor… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] Implement DIMM loading for DDR on K8
by Rudolf Marek 13 Dec '10

13 Dec '10

Hello, Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs. Dual DIMM Enable (DualDimmEn)—Bit 9. When this bit is set, the A copy of the memory address bus is enabled, regardless of the MC0_EN (Function 2, Offset 94h) value, and the B copy of the memory bus is disabled if 939 package with 128-bit bus is not used. This bit should be set if unbuffered DIMMs are used, and two DIMM sockets are connected to the A copy of the memory address bus, as in SODIMM or 939 package configurations. See “Register Differences in Revisions of the AMD AthlonTM 64. The patch does not implement support for three dimm configurations supported from revE. On the other hand it should improve greatly memory stability across the 939 platform. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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[commit] r6176 - trunk/src/northbridge/amd/amdk8
by repository service 13 Dec '10

13 Dec '10

Author: ruik Date: Mon Dec 13 21:43:33 2010 New Revision: 6176 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6176 Log: Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs. The patch does not implement support for three dimm configurations supported from revE. On the other hand it should improve greatly memory stability across the 939 platform. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/northbridge/amd/amdk8/raminit.c Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Mon Dec 13 21:04:25 2010 (r6175) +++ trunk/src/northbridge/amd/amdk8/raminit.c Mon Dec 13 21:43:33 2010 (r6176) @@ -1164,14 +1164,13 @@ dcl &= ~DCL_UnBuffDimm; if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { - dcl |= DCL_UnBuffDimm; /* set DCL_DualDIMMen too? */ - - /* set DCL_En2T if you have non-equal DDR mem types! */ - + dcl |= DCL_UnBuffDimm; +#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939 if ((cpuid_eax(1) & 0x30) == 0x30) { /* CS[7:4] is copy of CS[3:0], should be set for 939 socket */ dcl |= DCL_UpperCSMap; } +#endif } else { dcl |= DCL_UnBuffDimm; } @@ -1382,21 +1381,150 @@ const struct mem_param *param; long dimm_mask; }; + +static const unsigned char min_cycle_times[] = { + [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ + [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ + [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ + [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ +}; + +#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939 + +/* return the minimum cycle time and set 2T accordingly */ +static unsigned int spd_dimm_loading_socket939(const struct mem_controller *ctrl, long dimm_mask) { + +/* + 1 raise so we detect 0 as bad field */ +#define DDR200 (NBCAP_MEMCLK_100MHZ + 1) +#define DDR333 (NBCAP_MEMCLK_166MHZ + 1) +#define DDR400 (NBCAP_MEMCLK_200MHZ + 1) +#define DDR_2T 0x80 +#define DDR_MASK 0x3 + +#define DDR200_2T (DDR_2T | DDR200) +#define DDR333_2T (DDR_2T | DDR333) +#define DDR400_2T (DDR_2T | DDR400) + +/* + Following table comes directly from BKDG (unbuffered DIMM support) + [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty + X uses same layout but 1 means double rank 0 is single rank/empty + + Following tables come from BKDG the ch{0_0,1_0,0_1,1_1} maps to + MEMCS_{1L,1H,2L,2H} in i the PDF. PreE is table 45, and revE table 46. +*/ + + static const unsigned char dimm_loading_config_preE[16][16] = { + [0x8] = {[0x0] = DDR400,[0x8] = DDR400}, + [0x2] = {[0x0] = DDR333,[0x2] = DDR400}, + [0xa] = {[0x0] = DDR400_2T,[0x2] = DDR400_2T, + [0x8] = DDR400_2T,[0xa] = DDR333_2T}, + [0xc] = {[0x0] = DDR400,[0xc] = DDR400}, + [0x3] = {[0x0] = DDR333,[0x3] = DDR400}, + [0xf] = {[0x0] = DDR400_2T,[0x3] = DDR400_2T, + [0xc] = DDR400_2T,[0xf] = DDR333_2T}, + }; + + static const unsigned char dimm_loading_config_revE[16][16] = { + [0x8] = {[0x0] = DDR400, [0x8] = DDR400}, + [0x2] = {[0x0] = DDR333, [0x2] = DDR400}, + [0x4] = {[0x0] = DDR400, [0x4] = DDR400}, + [0x1] = {[0x0] = DDR333, [0x1] = DDR400}, + [0xa] = {[0x0] = DDR400_2T, [0x2] = DDR400_2T, + [0x8] = DDR400_2T, [0xa] = DDR333_2T}, + [0x5] = {[0x0] = DDR400_2T, [0x1] = DDR400_2T, + [0x4] = DDR400_2T, [0x5] = DDR333_2T}, + [0xc] = {[0x0] = DDR400, [0xc] = DDR400, [0x4] = DDR400, [0x8] = DDR400}, + [0x3] = {[0x0] = DDR333, [0x1] = DDR333, [0x2] = DDR333, [0x3] = DDR400}, + [0xe] = {[0x0] = DDR400_2T, [0x4] = DDR400_2T, [0x2] = DDR400_2T, + [0x6] = DDR400_2T, [0x8] = DDR400_2T, [0xc] = DDR400_2T, + [0xa] = DDR333_2T, [0xe] = DDR333_2T}, + [0xb] = {[0x0] = DDR333, [0x1] = DDR400_2T, [0x2] = DDR333_2T, + [0x3] = DDR400_2T, [0x8] = DDR333_2T, [0x9] = DDR400_2T, + [0xa] = DDR333_2T, [0xb] = DDR333_2T}, + [0xd] = {[0x0] = DDR400_2T, [0x8] = DDR400_2T, [0x1] = DDR400_2T, + [0x9] = DDR333_2T, [0x4] = DDR400_2T, [0xc] = DDR400_2T, + [0x5] = DDR333_2T, [0xd] = DDR333_2T}, + [0x7] = {[0x0] = DDR333, [0x2] = DDR400_2T, [0x1] = DDR333_2T, + [0x3] = DDR400_2T, [0x4] = DDR333_2T, [0x6] = DDR400_2T, + [0x5] = DDR333_2T, [0x7] = DDR333_2T}, + [0xf] = {[0x0] = DDR400_2T, [0x1] = DDR400_2T, [0x4] = DDR400_2T, + [0x5] = DDR333_2T, [0x2] = DDR400_2T, [0x3] = DDR400_2T, + [0x6] = DDR400_2T, [0x7] = DDR333_2T, [0x8] = DDR400_2T, + [0x9] = DDR400_2T, [0xc] = DDR400_2T, [0xd] = DDR333_2T, + [0xa] = DDR333_2T, [0xb] = DDR333_2T, [0xe] = DDR333_2T, + [0xf] = DDR333_2T}, + }; + /*The dpos matches channel positions defined in BKDG and above arrays + The rpos is bitmask of dual rank dimms in same order as dpos */ + unsigned int dloading = 0, dloading_cycle_time, i, rpos = 0, dpos =0; + const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; + int rank; + uint32_t dcl; + + if (is_cpu_pre_e0()) { + dimm_loading_config = dimm_loading_config_preE; + } + + /* only DIMMS two per channel */ + for (i = 0; i < 2; i++) { + if ((dimm_mask & (1 << i))) { + /* read rank channel 0 */ + rank = spd_read_byte(ctrl->channel0[i], 5); + if (rank < 0) goto hw_error; + rpos |= (rank == 2) ? (1 << (3 - (i * 2))) : 0; + dpos |= (1 << (3 - (i * 2))); + } + + if ((dimm_mask & (1 << (i+DIMM_SOCKETS)))) { + /* read rank channel 1*/ + rank = spd_read_byte(ctrl->channel1[i], 5); + if (rank < 0) goto hw_error; + rpos |= (rank == 2) ? (1 << (2 - (i * 2))) : 0; + dpos |= (1 << (2 - (i * 2))); + } + } + /* now the lookup, decode the max speed DDR400_2T etc */ + dloading = dimm_loading_config[dpos][rpos] & DDR_MASK; +#if 0 + printk(BIOS_DEBUG, "XXX %x %x dload %x 2T %x\n", dpos,rpos, dloading, dimm_loading_config[dpos][rpos] & DDR_2T); +#endif +hw_error: + if (dloading != 0) { + /* map it back to cycle load times */ + dloading_cycle_time = min_cycle_times[dloading - 1]; + /* we have valid combination check the restrictions */ + dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; + /* Set DuallDimm is second channel is completely empty (revD+) */ + if (((cpuid_eax(1) & 0xfff0f) >= 0x10f00) && ((dpos & 0x5) == 0)) { + printk(BIOS_DEBUG, "Setting DualDIMMen\n"); + dcl |= DCL_DualDIMMen; + } + pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + } else { + /* if we don't find it we se it to DDR400 */ + printk(BIOS_WARNING, "Detected strange DIMM configuration, may not work! (or bug)\n"); + dloading_cycle_time = min_cycle_times[NBCAP_MEMCLK_200MHZ]; + } + + return dloading_cycle_time; +} + +#endif /* #if defined(CONFIG_CPU_AMD_SOCKET_939) */ + static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *ctrl, long dimm_mask) { /* Compute the minimum cycle time for these dimms */ struct spd_set_memclk_result result; unsigned min_cycle_time, min_latency, bios_cycle_time; +#if defined(CONFIG_CPU_AMD_SOCKET_939) + unsigned dloading_cycle_time; +#endif int i; uint32_t value; static const uint8_t latency_indicies[] = { 26, 23, 9 }; - static const unsigned char min_cycle_times[] = { - [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ - [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ - [NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */ - [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ - }; value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); @@ -1545,6 +1673,16 @@ } #endif #endif + +#if defined(CONFIG_CPU_AMD_SOCKET_939) && CONFIG_CPU_AMD_SOCKET_939 + dloading_cycle_time = spd_dimm_loading_socket939(ctrl, dimm_mask); + if (dloading_cycle_time > min_cycle_time) { + min_cycle_time = dloading_cycle_time; + printk(BIOS_WARNING, "Memory speed reduced due to signal loading conditions\n"); + } +#endif + + /* Now that I know the minimum cycle time lookup the memory parameters */ result.param = get_mem_param(min_cycle_time);

1 0

[commit] r6175 - trunk/src/mainboard/asrock/939a785gmh
by repository service 13 Dec '10

13 Dec '10

Author: ruik Date: Mon Dec 13 21:04:25 2010 New Revision: 6175 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6175 Log: This patch just turns on the ACPI resume. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Mon Dec 13 21:02:23 2010 (r6174) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Mon Dec 13 21:04:25 2010 (r6175) @@ -11,6 +11,7 @@ select SOUTHBRIDGE_AMD_SB700 select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select HAVE_MP_TABLE select HAVE_PIRQ_TABLE select HAVE_MAINBOARD_RESOURCES

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[commit] r6174 - in trunk/src: include lib mainboard/asus/m2v mainboard/asus/m2v-mx_se mainboard/getac/p470 mainboard/ibase/mb899 mainboard/intel/d945gclf mainboard/kontron/986lcd-m mainboard/roda/...
by repository service 13 Dec '10

13 Dec '10

Author: ruik Date: Mon Dec 13 21:02:23 2010 New Revision: 6174 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6174 Log: Compile cbmem.c instead of including it in romstage, and do that only if resume is done. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/include/cbmem.h trunk/src/lib/Makefile.inc trunk/src/lib/cbmem.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m2v/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c Modified: trunk/src/include/cbmem.h ============================================================================== --- trunk/src/include/cbmem.h Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/include/cbmem.h Mon Dec 13 21:02:23 2010 (r6174) @@ -49,8 +49,9 @@ void cbmem_list(void); void cbmem_arch_init(void); +extern struct cbmem_entry *get_cbmem_toc(void); + #ifndef __PRE_RAM__ -struct cbmem_entry *get_cbmem_toc(void); void set_cbmem_toc(struct cbmem_entry *); #endif #endif Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/lib/Makefile.inc Mon Dec 13 21:02:23 2010 (r6174) @@ -15,6 +15,7 @@ ramstage-y += gcc.c ramstage-y += cbmem.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c romstage-y += uart8250.c romstage-y += memset.c romstage-y += memcpy.c Modified: trunk/src/lib/cbmem.c ============================================================================== --- trunk/src/lib/cbmem.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/lib/cbmem.c Mon Dec 13 21:02:23 2010 (r6174) @@ -48,6 +48,13 @@ { /* do nothing, this should be called by chipset to save TOC in NVRAM */ } +#else + +struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); + return NULL; +} #endif Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -74,15 +74,6 @@ #define SB_VFSMAF 0 - -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - /* this function might fail on some K8 CPUs with errata #181 */ static void ldtstop_sb(void) { Modified: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/asus/m2v/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -73,15 +73,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" - -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/getac/p470/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -262,14 +262,6 @@ #include <cbmem.h> -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM_ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - void main(unsigned long bist) { u32 reg32; Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/ibase/mb899/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -225,14 +225,6 @@ #include <cbmem.h> -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - void main(unsigned long bist) { u32 reg32; Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -186,14 +186,6 @@ #include <cbmem.h> -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - void main(unsigned long bist) { u32 reg32; Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -314,14 +314,6 @@ #include <cbmem.h> -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - void main(unsigned long bist) { u32 reg32; Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Dec 13 20:59:13 2010 (r6173) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Mon Dec 13 21:02:23 2010 (r6174) @@ -235,14 +235,6 @@ #include <cbmem.h> -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - void main(unsigned long bist) { u32 reg32;

1 0

[commit] r6172 - trunk/src/northbridge/amd/amdk8
by repository service 13 Dec '10

13 Dec '10

Author: ruik Date: Mon Dec 13 20:53:58 2010 New Revision: 6172 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6172 Log: Following patch adds support to bring out the memory out of self refresh when doing resume. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> The patch is based on my 2008 patch. Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/northbridge/amd/amdk8/raminit.c Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Mon Dec 13 20:50:25 2010 (r6171) +++ trunk/src/northbridge/amd/amdk8/raminit.c Mon Dec 13 20:53:58 2010 (r6172) @@ -2226,6 +2226,12 @@ #endif { int i; + u32 whatWait = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 + int suspend = acpi_is_wakeup_early(); +#else + int suspend = 0; +#endif /* Error if I don't have memory */ if (memory_end_k(ctrl, controllers) == 0) { @@ -2277,13 +2283,31 @@ } pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); } - dcl |= DCL_DisDqsHys; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + + if (!suspend) { + dcl |= DCL_DisDqsHys; + pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + } dcl &= ~DCL_DisDqsHys; dcl &= ~DCL_DLL_Disable; dcl &= ~DCL_D_DRV; dcl &= ~DCL_QFC_EN; - dcl |= DCL_DramInit; + + if (suspend) { + enable_lapic(); + init_timer(); + dcl |= (DCL_ESR | DCL_SRS); + /* Handle errata 85 Insufficient Delay Between MEMCLK Startup + and CKE Assertion During Resume From S3 */ + udelay(10); /* for unregistered */ + if (is_registered(&ctrl[i])) { + udelay(100); /* 110us for registered (we wait 10us already) */ + } + whatWait = DCL_ESR; + } else { + dcl |= DCL_DramInit; + whatWait = DCL_DramInit; + } pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); } @@ -2305,7 +2329,7 @@ if ((loops & 1023) == 0) { printk(BIOS_DEBUG, "."); } - } while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS)); + } while(((dcl & whatWait) != 0) && (loops < TIMEOUT_LOOPS)); if (loops >= TIMEOUT_LOOPS) { printk(BIOS_DEBUG, " failed\n"); continue; @@ -2313,11 +2337,15 @@ if (!is_cpu_pre_c0()) { /* Wait until it is safe to touch memory */ +#if 0 + /* the registers are marked read-only but code zeros them */ dcl &= ~(DCL_MemClrStatus | DCL_DramEnable); pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); +#endif do { dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); - } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) ); + } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) || + ((dcl & DCL_SRS))); } printk(BIOS_DEBUG, " done\n");

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[PATCH] Add support for the ASUS M2N-E board
by Uwe Hermann 13 Dec '10

13 Dec '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r6153 - in trunk/src: cpu/intel/car mainboard/asus/p2b southbridge/intel/i82371eb
by repository service 13 Dec '10

13 Dec '10

Author: ranma Date: Wed Dec 8 22:40:12 2010 New Revision: 6153 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6153 Log: Tobias Diedrich wrote: > Definitively a iasl problem, it can't even disassemble it's own > output back to something equivalent to the input file. > It seems to be generating Bytecode for the Add where it shouldn't. Here is a solution using the SSDT. Unfortunately iasl does not resolve simple arithmetic at compile time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the Processor statement. This patch instead dynamically generates the processor statement. I can't use the speedstep generate_cpu_entries() directly since the cpu doesn't support speedstep. For now the code is in the southbridge directory, but maybe it should go into cpu/intel/ somewhere. IIRC notebook cpus of the era can already have speedstep, so it would probably be possible to pair the i82371eb with a speedstep-capable cpu... Also, I don't know if multiprocessor boards (abit bp6?) would need to be handled differently. Abuild-tested. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/cpu/intel/car/Makefile.inc trunk/src/cpu/intel/car/disable_cache_as_ram.c trunk/src/cpu/intel/car/post_cache_as_ram.c Modified: trunk/src/mainboard/asus/p2b/dsdt.asl trunk/src/southbridge/intel/i82371eb/acpi_tables.c Added: trunk/src/cpu/intel/car/Makefile.inc ============================================================================== Added: trunk/src/cpu/intel/car/disable_cache_as_ram.c ============================================================================== Added: trunk/src/cpu/intel/car/post_cache_as_ram.c ============================================================================== Modified: trunk/src/mainboard/asus/p2b/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/p2b/dsdt.asl Wed Dec 8 20:58:30 2010 (r6152) +++ trunk/src/mainboard/asus/p2b/dsdt.asl Wed Dec 8 22:40:12 2010 (r6153) @@ -21,15 +21,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - /* Looks like the P_CNT field can't be a name or method (except - * builtins like Add()) and has to be hardcoded or generated - * into SSDT */ - Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off Modified: trunk/src/southbridge/intel/i82371eb/acpi_tables.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/acpi_tables.c Wed Dec 8 20:58:30 2010 (r6152) +++ trunk/src/southbridge/intel/i82371eb/acpi_tables.c Wed Dec 8 22:40:12 2010 (r6153) @@ -26,9 +26,46 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include "i82371eb.h" extern const unsigned char AmlCode[]; +static int determine_total_number_of_cores(void) +{ + device_t cpu; + int count = 0; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + count++; + } + return count; +} + +void generate_cpu_entries(void) +{ + int len; + int len_pr; + int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; + int numcpus = determine_total_number_of_cores(); + printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); + + /* without the outer scope, furhter ssdt addition will end up + * within the processor statement */ + len = acpigen_write_scope("\\_PR"); + for (cpu=0; cpu < numcpus; cpu++) { + len_pr = acpigen_write_processor(cpu, pcontrol_blk, plen); + acpigen_patch_len(len_pr - 1); + len += len_pr; + } + acpigen_patch_len(len - 1); +} + unsigned long __attribute__((weak)) acpi_fill_slit(unsigned long current) { // Not implemented @@ -57,6 +94,10 @@ const char *oem_table_id) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + /* generate_cpu_entries() generates weird bytecode and has to come + * last or else the following entries will end up inside the + * processor scope */ + generate_cpu_entries(); return (unsigned long) acpigen_get_current(); }

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Trac reminder: list of new ticket(s)
by coreboot tracker 13 Dec '10

13 Dec '10

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coreboot December 2010