coreboot October 2010

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[commit] r5998 - in trunk/src: mainboard/asus/p2b-d southbridge/intel/i82371eb
by repository service 28 Oct '10

28 Oct '10

Author: uwe Date: Thu Oct 28 10:19:22 2010 New Revision: 5998 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5998 Log: Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D. - Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the Intel 82371EB southbridge (sets the proper chip-select) and sets an IOAPIC ID. - We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC" as on 82371EB-based boards the IOAPIC is an external chip (not integrated in the southbridge) and it's only populated on multi-CPU boards. That is, we cannot unconditionally enable it, only on SMP-capable boards. - Due to the reason explained above, remove "select IOAPIC" from src/southbridge/intel/i82371eb/Kconfig, and add it to src/mainboard/asus/p2b-d/Kconfig. - Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already). - Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c, that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC are set. - Rework ASUS P2B-D mptable.c to fix a number of things: - Convert it to use mptable_write_buses() as all mptable.c files should do. - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC). - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc. This is build-tested on ASUS P2B-D, and also boot-tested successfully there. On Linux I now get two entries in /proc/cpuinfo (where only one appeared before this patch), i.e. both populated CPUs are found. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/p2b-d/Kconfig trunk/src/mainboard/asus/p2b-d/devicetree.cb trunk/src/mainboard/asus/p2b-d/mptable.c trunk/src/mainboard/asus/p2b-d/romstage.c trunk/src/southbridge/intel/i82371eb/Kconfig trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Modified: trunk/src/mainboard/asus/p2b-d/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-d/Kconfig Wed Oct 27 22:32:49 2010 (r5997) +++ trunk/src/mainboard/asus/p2b-d/Kconfig Thu Oct 28 10:19:22 2010 (r5998) @@ -28,6 +28,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP + select IOAPIC select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM @@ -48,4 +49,8 @@ int default 2 +config MAX_PHYSICAL_CPUS + int + default 2 + endif # BOARD_ASUS_P2B_D Modified: trunk/src/mainboard/asus/p2b-d/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-d/devicetree.cb Wed Oct 27 22:32:49 2010 (r5997) +++ trunk/src/mainboard/asus/p2b-d/devicetree.cb Thu Oct 28 10:19:22 2010 (r5998) @@ -1,10 +1,10 @@ chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/intel/slot_1 # CPU socket 0 + device lapic 0 on end # Local APIC of CPU 0 end - chip cpu/intel/slot_1 # CPU - device lapic 1 on end # APIC + chip cpu/intel/slot_1 # CPU socket 1 + device lapic 1 on end # Local APIC of CPU 1 end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b-d/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/mptable.c Wed Oct 27 22:32:49 2010 (r5997) +++ trunk/src/mainboard/asus/p2b-d/mptable.c Thu Oct 28 10:19:22 2010 (r5998) @@ -27,6 +27,7 @@ static void *smp_write_config_table(void *v) { + int ioapic_id, ioapic_ver, isa_bus; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -35,13 +36,12 @@ smp_write_processors(mc); - /* Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "ISA "); + mptable_write_buses(mc, NULL, &isa_bus); + + ioapic_id = 2; + ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; @@ -49,45 +49,39 @@ if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - smp_write_ioapic(mc, 3, 0x20, res->base); + smp_write_ioapic(mc, 3, ioapic_ver, res->base); } dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - smp_write_ioapic(mc, 4, 0x20, res->base); + smp_write_ioapic(mc, 4, ioapic_ver, res->base); } dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - smp_write_ioapic(mc, 5, 0x20, res->base); + smp_write_ioapic(mc, 5, ioapic_ver, res->base); } dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) - smp_write_ioapic(mc, 8, 0x20, res->base); + smp_write_ioapic(mc, 8, ioapic_ver, res->base); } } - mptable_add_isa_interrupts(mc, 0x2, 0x2, 0); + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0x2, 0xb, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0x2, 0xa, 0x2, 0x13); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_lintsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0, - MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x2, 0x0, MP_APIC_ALL, 0x1); + /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */ - /* There is no extension information... */ + /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); - /* Compute the checksums */ + /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); Modified: trunk/src/mainboard/asus/p2b-d/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/romstage.c Wed Oct 27 22:32:49 2010 (r5997) +++ trunk/src/mainboard/asus/p2b-d/romstage.c Thu Oct 28 10:19:22 2010 (r5998) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" @@ -48,8 +47,6 @@ void main(unsigned long bist) { - enable_lapic(); /* FIXME? */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/southbridge/intel/i82371eb/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82371eb/Kconfig Wed Oct 27 22:32:49 2010 (r5997) +++ trunk/src/southbridge/intel/i82371eb/Kconfig Thu Oct 28 10:19:22 2010 (r5998) @@ -1,6 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB bool - select IOAPIC select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT Modified: trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Wed Oct 27 22:32:49 2010 (r5997) +++ trunk/src/southbridge/intel/i82371eb/i82371eb_isa.c Thu Oct 28 10:19:22 2010 (r5998) @@ -28,6 +28,35 @@ #include <arch/ioapic.h> #include "i82371eb.h" +static void enable_intel_82093aa_ioapic(void) +{ + u16 reg16; + u32 reg32; + u8 ioapic_id = 2; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + device_t dev; + + dev = dev_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); + + /* Enable IOAPIC. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= (1 << 8); /* APIC Chip Select */ + pci_write_config16(dev, XBCS, reg16); + + /* Set the IOAPIC ID. */ + *ioapic_index = 0; + *ioapic_data = ioapic_id << 24; + + /* Read back and verify the IOAPIC ID. */ + *ioapic_index = 0; + reg32 = (*ioapic_data >> 24) & 0x0f; + printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32); + if (reg32 != ioapic_id) + die("IOAPIC error!\n"); +} + static void isa_init(struct device *dev) { u32 reg32; @@ -45,6 +74,18 @@ /* Initialize ISA DMA. */ isa_dma_init(); + +#if CONFIG_IOAPIC + /* + * Unlike most other southbridges the 82371EB doesn't have a built-in + * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs + * have a discrete IOAPIC (Intel 82093AA) soldered onto the board. + * + * Thus, we can/must only enable the IOAPIC if it actually exists, + * i.e. the respective mainboard does "select IOAPIC". + */ + enable_intel_82093aa_ioapic(); +#endif } static void sb_read_resources(struct device *dev)

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How the file, c_start.d is made?
by ali hagigat 27 Oct '10

27 Oct '10

The only rule for building c_start.o from c_start.S is the following in build/arch/i386/lib/c_start.d: build/arch/i386/lib/c_start.o: src/arch/i386/lib/c_start.S \ /root/build/coreboot/coreboot-v4/build/config.h \ src/include/cpu/x86/post_code.h The question is that what rule is making the file, c_start.d itself?

4 5

[patch] explicitly enable NIC and AC97 on A8N-E
by Jonathan A. Kollasch 27 Oct '10

27 Oct '10

Enable CK804 AC'97 audio interface and explicitly enable NIC on A8N-E. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> --- (Note, this needs the previous patch to ck804_early_setup.c or switching the board to ck804_early_setup_car.c.)

2 2

[commit] r5997 - trunk/src/mainboard/asus/a8n_e
by repository service 27 Oct '10

27 Oct '10

Author: jakllsch Date: Wed Oct 27 22:32:49 2010 New Revision: 5997 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5997 Log: Enable CK804 AC'97 audio interface and explicitly enable NIC on A8N-E. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asus/a8n_e/Kconfig Modified: trunk/src/mainboard/asus/a8n_e/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8n_e/Kconfig Wed Oct 27 22:30:32 2010 (r5996) +++ trunk/src/mainboard/asus/a8n_e/Kconfig Wed Oct 27 22:32:49 2010 (r5997) @@ -15,6 +15,8 @@ select CACHE_AS_RAM select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_512 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string

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[patch] ck804 early setup correction
by Jonathan A. Kollasch 27 Oct '10

27 Oct '10

Correct an apparent copy-paste error that shows up at compile time on boards using ck804_early_setup.c that select CK804_USE_NIC. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

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[commit] r5996 - trunk/src/southbridge/nvidia/ck804
by repository service 27 Oct '10

27 Oct '10

Author: jakllsch Date: Wed Oct 27 22:30:32 2010 New Revision: 5996 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5996 Log: Correct an apparent copy-paste error that shows up at compile time on boards using ck804_early_setup.c that select CK804_USE_NIC. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Wed Oct 27 19:41:40 2010 (r5995) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Wed Oct 27 22:30:32 2010 (r5996) @@ -266,11 +266,11 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #if CONFIG_CK804_USE_NIC - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), #endif #if CONFIG_CK804_USE_ACI

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[patch] ck804 early smbus
by Jonathan A. Kollasch 27 Oct '10

27 Oct '10

Convert ck804_early_smbus.c to a separately compiled unit. Additionally, make the second SMBus more accessible in romstage. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

2 2

[patch] move ck804 to tiny bootblock
by Jonathan A. Kollasch 27 Oct '10

27 Oct '10

Convert all ck804-based boards to tiny bootblock. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

2 2

HT3 for AMD boards
by Scott Duplichan 27 Oct '10

27 Oct '10

Hello, An HT configuration change is needed to allow the southbridge link to run at HT3 frequencies on supported hardware. AMD family 10h processors support HT3, as do many AMD motherboards. When the southbridge runs at the default settings of 8-bit, 200 MHz, the throughput is insufficient for supporting high resolution graphics. I have the needed changes ready but can test only the mahogany_fam10 project. The change involves the buid swap list, which is also used by projects supporting the previous generation AMD processor (family 0Fh). The change may also allow family 0Fh boards to use improved SB link settings. Here is my proposal. If it seems OK, I will submit a patch. 1) Add an option for HT_MANUAL_SWAP_LIST to amdfam10/kconfig and amdk8/kconfig. The default is zero, which means it has no effect unless overridden. 2) Modify ht_wrapper.c to use HT_MANUAL_SWAP_LIST as the swap list, if non-zero. 3) In mainboard/amd/mahogany_fam10/Kconfig, override HT_MANUAL_SWAP_LIST with the value that is known to allow HT3 to work. 4) Possibly do the same for mainboard/amd/mahogany/Kconfig and test using a family 0Fh processor (I think I can find one). 5) Modify amdht/comlib.h so that if a critical HT initialization error occurs, it is no longer ignored. It will now log a message such as: === Failure at line 1145 of file src/northbridge/amd/amdht/h3finit.c ===, though execution will continue for backwards compatibility. The idea is that nothing changes by default, except for the one or two projects I can test on real hardware. For other boards, owners of the hardware can add the HT_MANUAL_SWAP_LIST override to their mainboard kconfig and tweak it until it works. Thanks, Scott

3 6

[commit] r5995 - trunk/src/mainboard/msi/ms7135
by repository service 27 Oct '10

27 Oct '10

Author: jakllsch Date: Wed Oct 27 19:41:40 2010 New Revision: 5995 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5995 Log: Drop referenced-yet-does-nothing static function from ms7135 romstage. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/src/mainboard/msi/ms7135/romstage.c Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Wed Oct 27 19:26:57 2010 (r5994) +++ trunk/src/mainboard/msi/ms7135/romstage.c Wed Oct 27 19:41:40 2010 (r5995) @@ -57,11 +57,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" -static void memreset_setup(void) -{ - /* FIXME: Nothing to do? */ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { /* FIXME: Nothing to do? */ @@ -173,7 +168,6 @@ dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(nodes, ctrl); #if 0

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coreboot October 2010