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Re: [coreboot] [PATCH] Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D
by Keith Hui 26 Oct '10

26 Oct '10

Some 440BX SMP activity! Woot! :-D There is a note in northbridge/intel/i440bx/raminit.c about a bit in a 440BX register that needs configured for SMP machines (NBXCFG I think? don't recall off my head - could be myself who left the note there). You will want to make sure that gets addressed. Cheers Keith On Mon, Oct 25, 2010 at 6:00 AM, <coreboot-request(a)coreboot.org> wrote: > Date: Sun, 24 Oct 2010 23:56:15 +0200 > From: Uwe Hermann <uwe(a)hermann-uwe.de> > To: coreboot(a)coreboot.org > Subject: [coreboot] [PATCH] Add IOAPIC support for Intel 82371EB and > fixup SMP on ASUS P2B-D > Message-ID: <20101024215614.GX3256@greenwood> > Content-Type: text/plain; charset="us-ascii" > > See patch. > > As soon as this patch is merged, I'll send follow-up patches to > convert/fix the other 440BX/82371EB-based SMP-capable boards. > >

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[commit] r5993 - in trunk/src: northbridge/amd/amdht northbridge/intel/e7501 northbridge/intel/e7520 northbridge/intel/i3100 northbridge/intel/i855 southbridge/intel/i82801cx southbridge/intel/i828...
by repository service 26 Oct '10

26 Oct '10

Author: uwe Date: Wed Oct 27 00:46:43 2010 New Revision: 5993 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5993 Log: Convert some comments to proper Doxygen syntax. Also, make them all fit in 80chars/column, fix some whitespace issues and also some typos I noticed. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/amd/amdht/AsPsNb.c trunk/src/northbridge/intel/e7501/raminit.c trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/i3100/raminit_ep80579.c trunk/src/northbridge/intel/i855/raminit.c trunk/src/southbridge/intel/i82801cx/i82801cx.h trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c trunk/src/southbridge/intel/i82870/p64h2_ioapic.c trunk/src/southbridge/sis/sis966/sis761.c trunk/src/southbridge/sis/sis966/sis966_lpc.c trunk/src/southbridge/sis/sis966/sis966_nic.c trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c trunk/src/superio/smsc/lpc47b272/superio.c trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c trunk/src/superio/smsc/lpc47m10x/superio.c trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c trunk/src/superio/smsc/lpc47n217/superio.c trunk/src/superio/smsc/lpc47n227/lpc47n227.h trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c trunk/src/superio/smsc/lpc47n227/superio.c Modified: trunk/src/northbridge/amd/amdht/AsPsNb.c ============================================================================== --- trunk/src/northbridge/amd/amdht/AsPsNb.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/northbridge/amd/amdht/AsPsNb.c Wed Oct 27 00:46:43 2010 (r5993) @@ -17,39 +17,23 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -/* - *---------------------------------------------------------------------------- - * MODULES USED - * - *---------------------------------------------------------------------------- - */ #undef FILECODE #define FILECODE 0xCCCC + #include "comlib.h" #include "AsPsDefs.h" #include "AsPsNb.h" - -/*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS - * - *---------------------------------------------------------------------------- - */ u8 getNumOfNodeNb(void); u8 translateNodeIdToDeviceIdNb(u8 nodeId); - -/*---------------------------------------------------------------------------- - * FUNCTION: getMinNbCOF - * INPUT: None - * OUTPUT: minNbCOF (in multiple of half of CLKIN, 100MHz) - * DESCRIPTION: - * This function returns the minimum possible NbCOF (in 100MHz) - * for the system . - * This function can be run on any core and is used by the HT & Memory init code - * in Phase 1. - * ---------------------------------------------------------------------------- +/** + * Return the minimum possible NbCOF (in 100MHz) for the system. + * + * This function can be run on any core and is used by the HT & Memory init + * code in Phase 1. + * + * @return minNbCOF (in multiple of half of CLKIN, 100MHz). */ u8 getMinNbCOF(void) { @@ -130,14 +114,13 @@ return (u8)dtemp; } -/*---------------------------------------------------------------------------- - * FUNCTION: translateNodeIdToDeviceId - * INPUT: u8 nodeId - node ID of the node - * OUTPUT: u8 - PCI device ID of the node - * DESCRIPTION: - * This function return the PCI device ID for PCI access using node ID. - * This function may need to chnage node ID to device ID in big MP systems. - * ---------------------------------------------------------------------------- +/** + * Return the PCI device ID for PCI access using node ID. + * + * This function may need to change node ID to device ID in big MP systems. + * + * @param nodeId Node ID of the node. + * @return PCI device ID of the node. */ u8 translateNodeIdToDeviceIdNb(u8 nodeId) { Modified: trunk/src/northbridge/intel/e7501/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/northbridge/intel/e7501/raminit.c Wed Oct 27 00:46:43 2010 (r5993) @@ -17,6 +17,10 @@ #include <stdlib.h> #include "e7501.h" +/*----------------------------------------------------------------------------- +Definitions: +-----------------------------------------------------------------------------*/ + // Uncomment this to enable run-time checking of DIMM parameters // for dual-channel operation // Unfortunately the code seems to chew up several K of space. @@ -47,10 +51,6 @@ unsigned long side2; }; -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DEFINITIONS */ -/**********************************************************************************/ - static const uint32_t refresh_frequency[] = { /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) @@ -451,9 +451,10 @@ 0x88888888, 0x88888888, 0x88888888, 0x88888888, }; -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* TABLES */ -/**********************************************************************************/ +/*----------------------------------------------------------------------------- +Delay functions: +-----------------------------------------------------------------------------*/ + #define SLOW_DOWN_IO inb(0x80) //#define SLOW_DOWN_IO udelay(40); @@ -477,27 +478,26 @@ #define EXTRA_DELAY DO_DELAY -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DELAY FUNCTIONS */ -/**********************************************************************************/ - static void die_on_spd_error(int spd_return_value) { if (spd_return_value < 0) die("Error reading SPD info\n"); } -//---------------------------------------------------------------------------------- -// Function: sdram_spd_get_page_size -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: struct dimm_size - log2(page size) for each side of the DIMM. -// Description: Calculate the page size for each physical bank of the DIMM: -// log2(page size) = (# columns) + log2(data width) -// -// NOTE: page size is the total number of data bits in a row. -// -static struct dimm_size sdram_spd_get_page_size(uint16_t - dimm_socket_address) +/*----------------------------------------------------------------------------- +Serial presence detect (SPD) functions: +-----------------------------------------------------------------------------*/ + +/** + * Calculate the page size for each physical bank of the DIMM: + * log2(page size) = (# columns) + log2(data width) + * + * NOTE: Page size is the total number of data bits in a row. + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return log2(page size) for each side of the DIMM. + */ +static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) { uint16_t module_data_width; int value; @@ -554,13 +554,12 @@ return pgsz; // Never reached } -//---------------------------------------------------------------------------------- -// Function: sdram_spd_get_width -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: dimm_size - width in bits of each DIMM side's DRAMs. -// Description: Read the width in bits of each DIMM side's DRAMs via SPD. -// (i.e. 4, 8, 16) -// +/** + * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return Width in bits of each DIMM side's DRAMs. + */ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) { int value; @@ -601,18 +600,19 @@ return width; } -//---------------------------------------------------------------------------------- -// Function: spd_get_dimm_size -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: dimm_size - log2(number of bits) for each side of the DIMM -// Description: Calculate the log base 2 size in bits of both DIMM sides. -// log2(# bits) = (# columns) + log2(data width) + -// (# rows) + log2(banks per SDRAM) -// -// Note that it might be easier to use SPD byte 31 here, it has the -// DIMM size as a multiple of 4MB. The way we do it now we can size -// both sides of an asymmetric dimm. -// +/** + * Calculate the log base 2 size in bits of both DIMM sides. + * + * log2(# bits) = (# columns) + log2(data width) + + * (# rows) + log2(banks per SDRAM) + * + * Note that it might be easier to use SPD byte 31 here, it has the DIMM size + * as a multiple of 4MB. The way we do it now we can size both sides of an + * asymmetric DIMM. + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return log2(number of bits) for each side of the DIMM. + */ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) { int value; @@ -651,20 +651,21 @@ } #ifdef VALIDATE_DIMM_COMPATIBILITY -//---------------------------------------------------------------------------------- -// Function: are_spd_values_equal -// Parameters: spd_byte_number - -// dimmN_address - SMBus addresses of DIMM sockets to interrogate -// Return Value: 1 if both DIMM sockets report the same value for the specified -// SPD parameter; 0 if the values differed or an error occurred. -// Description: Determine whether two DIMMs have the same value for a SPD parameter. -// + +/** + * Determine whether two DIMMs have the same value for an SPD parameter. + * + * @param spd_byte_number The SPD byte number to compare in both DIMMs. + * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. + * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. + * @return 1 if both DIMM sockets report the same value for the specified + * SPD parameter, 0 if the values differed or an error occurred. + */ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address, uint16_t dimm1_address) { uint8_t bEqual = 0; - int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); @@ -676,23 +677,24 @@ } #endif -//---------------------------------------------------------------------------------- -// Function: spd_get_supported_dimms -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: uint8_t - a bitmask indicating which of the possible sockets -// for each channel was found to contain a compatible DIMM. -// Bit 0 corresponds to the closest socket for channel 0, -// Bit 1 to the next socket for channel 0, -// ... -// Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0, -// Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1, -// ... -// Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 -// Description: Scan for compatible DIMMs. -// The code in this module only supports dual-channel operation, -// so we test that compatible DIMMs are paired. -// +/** + * Scan for compatible DIMMs. + * + * The code in this module only supports dual-channel operation, so we test + * that compatible DIMMs are paired. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @return A bitmask indicating which of the possible sockets for each channel + * was found to contain a compatible DIMM. + * Bit 0 corresponds to the closest socket for channel 0 + * Bit 1 to the next socket for channel 0 + * ... + * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 + * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 + * ... + * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 + */ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) { int i; @@ -828,25 +830,17 @@ return dimm_mask; } -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* SPD (SERIAL PRESENCE DETECT) FUNCTIONS */ -/**********************************************************************************/ - -//---------------------------------------------------------------------------------- -// Function: do_ram_command -// Parameters: -// command - specifies the command to be sent to the DIMMs: -// RAM_COMMAND_NOP - No Operation -// RAM_COMMAND_PRECHARGE - Precharge all banks -// RAM_COMMAND_MRS - Load Mode Register -// RAM_COMMAND_EMRS - Load Extended Mode Register -// RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS") -// RAM_COMMAND_NORMAL - Normal operation -// jedec_mode_bits - for mode register set & extended mode register set -// commands, bits 0-12 contain the register value in JEDEC format. -// Return Value: None -// Description: Send the specified command to all DIMMs. -// +/*----------------------------------------------------------------------------- +SDRAM configuration functions: +-----------------------------------------------------------------------------*/ + +/** + * Send the specified command to all DIMMs. + * + * @param command Specifies the command to be sent to the DIMMs. + * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the + * register value in JEDEC format. + */ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { int i; @@ -916,14 +910,15 @@ } } -//---------------------------------------------------------------------------------- -// Function: set_ram_mode -// Parameters: jedec_mode_bits - for mode register set & extended mode register set -// commands, bits 0-12 contain the register value in JEDEC format. -// Return Value: None -// Description: Set the mode register of all DIMMs. The proper CAS# latency -// setting is added to the mode bits specified by the caller. -// +/** + * Set the mode register of all DIMMs. + * + * The proper CAS# latency setting is added to the mode bits specified + * by the caller. + * + * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the + * register value in JEDEC format. + */ static void set_ram_mode(uint16_t jedec_mode_bits) { ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); @@ -948,22 +943,22 @@ do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); } -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* SDRAM CONFIGURATION FUNCTIONS */ -/**********************************************************************************/ - -//---------------------------------------------------------------------------------- -// Function: configure_dimm_row_boundaries -// Parameters: -// dimm_log2_num_bits - log2(number of bits) for each side of the DIMM -// total_dram_64M_multiple - total DRAM in the system (as a -// multiple of 64 MB) for DIMMs < dimm_index -// dimm_index - which DIMM pair is being processed -// (0..MAX_DIMM_SOCKETS_PER_CHANNEL) -// Return Value: New multiple of 64 MB total DRAM in the system -// Description: Configure the E7501's DRAM Row Boundary registers for the memory -// present in the specified DIMM. -// +/*----------------------------------------------------------------------------- +DIMM-independant configuration functions: +-----------------------------------------------------------------------------*/ + +/** + * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory + * present in the specified DIMM. + * + * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of + * the DIMM. + * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of + * 64 MB) for DIMMs < dimm_index. + * @param dimm_index Which DIMM pair is being processed + * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). + * @return New multiple of 64 MB total DRAM in the system. + */ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) { int i; @@ -1017,18 +1012,16 @@ return total_dram_64M_multiple; } -//---------------------------------------------------------------------------------- -// Function: configure_e7501_ram_addresses -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Program the E7501's DRAM row boundary addresses and its Top Of -// Low Memory (TOLM). If necessary, set up a remap window so we -// don't waste DRAM that ordinarily would lie behind addresses -// reserved for memory-mapped I/O. -// +/** + * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). + * + * If necessary, set up a remap window so we don't waste DRAM that ordinarily + * would lie behind addresses reserved for memory-mapped I/O. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). + */ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl, uint8_t dimm_mask) { @@ -1130,13 +1123,10 @@ } } -//---------------------------------------------------------------------------------- -// Function: initialize_ecc -// Parameters: None -// Return Value: None -// Description: If we're configured to use ECC, initialize the SDRAM and -// clear the E7501's ECC error flags. -// +/** + * If we're configured to use ECC, initialize the SDRAM and clear the E7501's + * ECC error flags. + */ static void initialize_ecc(void) { uint32_t dram_controller_mode; @@ -1177,17 +1167,15 @@ } -//---------------------------------------------------------------------------------- -// Function: configure_e7501_dram_timing -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Program the DRAM Timing register of the E7501 (except for CAS# -// latency, which is assumed to have been programmed already), based -// on the parameters of the various installed DIMMs. -// +/** + * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# + * latency, which is assumed to have been programmed already), based on the + * parameters of the various installed DIMMs. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). + */ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask) { @@ -1314,16 +1302,14 @@ die(SPD_ERROR); } -//---------------------------------------------------------------------------------- -// Function: configure_e7501_cas_latency -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Determine the shortest CAS# latency that the E7501 and all DIMMs -// have in common, and program the E7501 to use it. -// +/** + * Determine the shortest CAS# latency that the E7501 and all DIMMs have in + * common, and program the E7501 to use it. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). + */ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask) { @@ -1471,17 +1457,15 @@ die(SPD_ERROR); } -//---------------------------------------------------------------------------------- -// Function: configure_e7501_dram_controller_mode -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Configure the refresh interval so that we refresh no more often -// than required by the "most needy" DIMM. Also disable ECC if any -// of the DIMMs don't support it. -// +/** + * Configure the refresh interval so that we refresh no more often than + * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs + * don't support it. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). + */ static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl, uint8_t dimm_mask) @@ -1579,18 +1563,16 @@ pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode); } -//---------------------------------------------------------------------------------- -// Function: configure_e7501_row_attributes -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Configure the E7501's DRAM Row Attributes (DRA) registers -// based on DIMM parameters read via SPD. This tells the controller -// the width of the SDRAM chips on each DIMM side (x4 or x8) and -// the page size of each DIMM side (4, 8, 16, or 32 KB). -// +/** + * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM + * parameters read via SPD. This tells the controller the width of the SDRAM + * chips on each DIMM side (x4 or x8) and the page size of each DIMM side + * (4, 8, 16, or 32 KB). + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). + */ static void configure_e7501_row_attributes(const struct mem_controller *ctrl, uint8_t dimm_mask) { @@ -1634,14 +1616,12 @@ pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes); } -//---------------------------------------------------------------------------------- -// Function: enable_e7501_clocks -// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Enable clock signals for populated DIMM sockets and disable them -// for unpopulated sockets (to reduce EMI). -// +/* + * Enable clock signals for populated DIMM sockets and disable them for + * unpopulated sockets (to reduce EMI). + * + * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). + */ static void enable_e7501_clocks(uint8_t dimm_mask) { int i; @@ -1660,17 +1640,11 @@ pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); } -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */ -/**********************************************************************************/ - -//---------------------------------------------------------------------------------- -// Function: RAM_RESET_DDR_PTR -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: DDR Receive FIFO RE-Sync (?) -// +/* DIMM-dedependent configuration functions */ + +/** + * DDR Receive FIFO RE-Sync (?) + */ static void RAM_RESET_DDR_PTR(void) { uint8_t byte; @@ -1683,17 +1657,15 @@ pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); } -//---------------------------------------------------------------------------------- -// Function: ram_set_d0f0_regs -// Parameters: None -// Return Value: None -// Description: Set E7501 registers that are either independent of DIMM specifics, -// or establish default settings that will be overridden when we -// learn the specifics. -// This sets PCI configuration registers to known good values based -// on the table 'constant_register_values', which are a triple of -// configuration register offset, mask, and bits to set. -// +/** + * Set E7501 registers that are either independent of DIMM specifics, or + * establish default settings that will be overridden when we learn the + * specifics. + * + * This sets PCI configuration registers to known good values based on the + * table 'constant_register_values', which are a triple of configuration + * register offset, mask, and bits to set. + */ static void ram_set_d0f0_regs(void) { int i; @@ -1726,14 +1698,13 @@ } } -//---------------------------------------------------------------------------------- -// Function: write_8dwords -// Parameters: src_addr -// dst_addr -// Return Value: None -// Description: Copy 64 bytes from one location to another. -// -static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr) +/** + * Copy 64 bytes from one location to another. + * + * @param src_addr TODO + * @param dst_addr TODO + */ +static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) { int i; for (i = 0; i < 8; i++) { @@ -1743,17 +1714,16 @@ } } -//---------------------------------------------------------------------------------- -// Function: ram_set_rcomp_regs -// Parameters: None -// Return Value: None -// Description: Set the E7501's (undocumented) RCOMP registers. -// Per the 855PM datasheet and IXP2800 HW Initialization Reference -// Manual, RCOMP registers appear to affect drive strength, -// pullup/pulldown offset, and slew rate of various signal groups. -// Comments below are conjecture based on apparent similarity -// between the E7501 and these two chips. -// +/** + * Set the E7501's (undocumented) RCOMP registers. + * + * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, + * RCOMP registers appear to affect drive strength, pullup/pulldown offset, + * and slew rate of various signal groups. + * + * Comments below are conjecture based on apparent similarity between the + * E7501 and these two chips. + */ static void ram_set_rcomp_regs(void) { uint32_t dword; @@ -1857,20 +1827,19 @@ } -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DIMM-INDEPENDENT CONFIGURATION FUNCTIONS */ -/**********************************************************************************/ - -//---------------------------------------------------------------------------------- -// Function: sdram_enable -// Parameters: controllers - not used -// ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: Go through the JEDEC initialization sequence for all DIMMs, -// then enable refresh and initialize ECC and memory to zero. -// Upon exit, SDRAM is up and running. -// +/*----------------------------------------------------------------------------- +Public interface: +-----------------------------------------------------------------------------*/ + +/** + * Go through the JEDEC initialization sequence for all DIMMs, then enable + * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up + * and running. + * + * @param controllers Not used. + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + */ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { @@ -1975,16 +1944,14 @@ DUMPNORTH(); } -//---------------------------------------------------------------------------------- -// Function: sdram_set_spd_registers -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: Configure SDRAM controller parameters that depend on -// characteristics of the DIMMs installed in the system. These -// characteristics are read from the DIMMs via the standard Serial -// Presence Detect (SPD) interface. -// +/** + * Configure SDRAM controller parameters that depend on characteristics of the + * DIMMs installed in the system. These characteristics are read from the + * DIMMs via the standard Serial Presence Detect (SPD) interface. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { uint8_t dimm_mask; @@ -2023,14 +1990,13 @@ pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); } -//---------------------------------------------------------------------------------- -// Function: sdram_set_registers -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: Do basic ram setup that does NOT depend on serial presence detect -// information (i.e. independent of DIMM specifics). -// +/** + * Do basic RAM setup that does NOT depend on serial presence detect + * information (i.e. independent of DIMM specifics). + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + */ static void sdram_set_registers(const struct mem_controller *ctrl) { RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n"); @@ -2039,7 +2005,3 @@ ram_set_rcomp_regs(); ram_set_d0f0_regs(); } - -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* PUBLIC INTERFACE */ -/**********************************************************************************/ Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/northbridge/intel/e7520/raminit.c Wed Oct 27 00:46:43 2010 (r5993) @@ -15,7 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include <cpu/x86/mtrr.h> @@ -81,8 +80,6 @@ print_spew("done.\n"); } - - struct dimm_size { unsigned long side1; unsigned long side2; @@ -209,7 +206,6 @@ return 0; } - static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) { unsigned dimm_mask; @@ -236,7 +232,6 @@ return dimm_mask; } - static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -296,7 +291,6 @@ } - static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { @@ -798,6 +792,7 @@ } } } + static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -1030,7 +1025,6 @@ write32(BAR+0x154, recenb); } - static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; Modified: trunk/src/northbridge/intel/i3100/raminit_ep80579.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit_ep80579.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/northbridge/intel/i3100/raminit_ep80579.c Wed Oct 27 00:46:43 2010 (r5993) @@ -16,7 +16,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include <cpu/x86/mtrr.h> Modified: trunk/src/northbridge/intel/i855/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/northbridge/intel/i855/raminit.c Wed Oct 27 00:46:43 2010 (r5993) @@ -25,6 +25,10 @@ #include <delay.h> #include "i855.h" +/*----------------------------------------------------------------------------- +Macros and definitions: +-----------------------------------------------------------------------------*/ + #define VALIDATE_DIMM_COMPATIBILITY /* Debugging macros. */ @@ -65,10 +69,6 @@ unsigned int side2; }; -/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DEFINITIONS */ -/**********************************************************************************/ - static const uint32_t refresh_frequency[] = { /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) @@ -104,7 +104,7 @@ #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) /*----------------------------------------------------------------------------- -SPD functions. +SPD functions: -----------------------------------------------------------------------------*/ static void die_on_spd_error(int spd_return_value) @@ -117,15 +117,16 @@ */ } -//---------------------------------------------------------------------------------- -// Function: sdram_spd_get_page_size -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: struct dimm_size - log2(page size) for each side of the DIMM. -// Description: Calculate the page size for each physical bank of the DIMM: -// log2(page size) = (# columns) + log2(data width) -// -// NOTE: page size is the total number of data bits in a row. -// +/** + * Calculate the page size for each physical bank of the DIMM: + * + * log2(page size) = (# columns) + log2(data width) + * + * NOTE: Page size is the total number of data bits in a row. + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return log2(page size) for each side of the DIMM. + */ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) { uint16_t module_data_width; @@ -180,13 +181,12 @@ return pgsz; } -//---------------------------------------------------------------------------------- -// Function: sdram_spd_get_width -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: dimm_size - width in bits of each DIMM side's DRAMs. -// Description: Read the width in bits of each DIMM side's DRAMs via SPD. -// (i.e. 4, 8, 16) -// +/** + * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). + * + * @param dimm_socket_address SMBus address of DIMM socket to interrogate. + * @return Width in bits of each DIMM side's DRAMs. + */ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) { int value; @@ -225,18 +225,19 @@ return width; } -//---------------------------------------------------------------------------------- -// Function: spd_get_dimm_size -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: dimm_size - log2(number of bits) for each side of the DIMM -// Description: Calculate the log base 2 size in bits of both DIMM sides. -// log2(# bits) = (# columns) + log2(data width) + -// (# rows) + log2(banks per SDRAM) -// -// Note that it might be easier to use SPD byte 31 here, it has the -// DIMM size as a multiple of 4MB. The way we do it now we can size -// both sides of an asymmetric dimm. -// +/** + * Calculate the log base 2 size in bits of both DIMM sides. + * + * log2(# bits) = (# columns) + log2(data width) + + * (# rows) + log2(banks per SDRAM) + * + * Note that it might be easier to use SPD byte 31 here, it has the DIMM size + * as a multiple of 4MB. The way we do it now we can size both sides of an + * asymmetric DIMM. + * + * @param dimm SMBus address of DIMM socket to interrogate. + * @return log2(number of bits) for each side of the DIMM. + */ static struct dimm_size spd_get_dimm_size(unsigned dimm) { int value; @@ -270,13 +271,13 @@ return sz; } -//---------------------------------------------------------------------------------- -// Function: spd_get_supported_dimms -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: uint8_t - a bitmask indicating which sockets contain a compatible DIMM. -// Description: Scan for compatible DIMMs. -// +/** + * Scan for compatible DIMMs. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + * @return A bitmask indicating which sockets contain a compatible DIMM. + */ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) { int i; @@ -356,8 +357,9 @@ } /*----------------------------------------------------------------------------- -DIMM-initialization functions. +SDRAM configuration functions: -----------------------------------------------------------------------------*/ + static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { int i; @@ -487,14 +489,16 @@ } /*----------------------------------------------------------------------------- -DIMM-independant configuration functions. +DIMM-independant configuration functions: -----------------------------------------------------------------------------*/ /** - * Set only what I need until it works, then make it figure things out on boot - * assumes only one dimm is populated - */ - + * Set only what I need until it works, then make it figure things out on boot + * assumes only one DIMM is populated. + * + * @param ctrl PCI addresses of memory controller functions, and SMBus + * addresses of DIMM slots on the mainboard. + */ static void sdram_set_registers(const struct mem_controller *ctrl) { /* Modified: trunk/src/southbridge/intel/i82801cx/i82801cx.h ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx.h Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/southbridge/intel/i82801cx/i82801cx.h Wed Oct 27 00:46:43 2010 (r5993) @@ -32,9 +32,7 @@ #define RTC_POWER_FAILED (1<<1) #define SLEEP_AFTER_POWER_FAIL (1<<0) -/********************************************************************/ -/* IDE Controller */ -/********************************************************************/ +/* IDE controller: */ // PCI Configuration Space (D31:F1) #define IDE_TIM_PRI 0x40 // IDE timings, primary @@ -44,9 +42,7 @@ // IDE_TIM bits #define IDE_DECODE_ENABLE (1<<15) -/********************************************************************/ -/* SMBus */ -/********************************************************************/ +/* SMBus: */ // PCI Configuration Space (D31:F3) #define SMB_BASE 0x20 Modified: trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Wed Oct 27 00:46:43 2010 (r5993) @@ -61,15 +61,14 @@ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); } -//---------------------------------------------------------------------------------- -// Function: i82801cx_lpc_route_dma -// Parameters: dev -// mask - identifies whether each channel should be used for PCI DMA -// (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. -// Channel 4 is not used (reserved). -// Return Value: None -// Description: Route all DMA channels to either PCI or LPC. -// +/** + * Route all DMA channels to either PCI or LPC. + * + * @param dev TODO + * @param mask Identifies whether each channel should be used for PCI DMA + * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. + * Channel 4 is not used (reserved). + */ static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; Modified: trunk/src/southbridge/intel/i82870/p64h2_ioapic.c ============================================================================== --- trunk/src/southbridge/intel/i82870/p64h2_ioapic.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/southbridge/intel/i82870/p64h2_ioapic.c Wed Oct 27 00:46:43 2010 (r5993) @@ -18,15 +18,15 @@ pci_write_config16(dev, PCI_COMMAND, command); } -//---------------------------------------------------------------------------------- -// Function: p64h2_ioapic_init -// Parameters: dev - PCI bus/device/function of P64H2 IOAPIC -// NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0 -// Return Value: None -// Description: Configure one of the IOAPICs in a P64H2. -// Note that a PCI bus scan will detect both IOAPICs, so this function -// will be called twice for each P64H2 in the system. -// +/** + * Configure one of the IOAPICs in a P64H2. + * + * Note that a PCI bus scan will detect both IOAPICs, so this function + * will be called twice for each P64H2 in the system. + * + * @param dev PCI bus/device/function of P64H2 IOAPIC. + * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0. + */ static void p64h2_ioapic_init(device_t dev) { uint32_t memoryBase; Modified: trunk/src/southbridge/sis/sis966/sis761.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis761.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/southbridge/sis/sis966/sis761.c Wed Oct 27 00:46:43 2010 (r5993) @@ -41,22 +41,6 @@ #include <cpu/amd/model_fxx_rev.h> #include <arch/io.h> -/** - * @brief Read resources for AGP aperture - * - * @param - * - * There is only one AGP aperture resource needed. The resoruce is added to - * the northbridge of BSP. - * - * The same trick can be used to augment legacy VGA resources which can - * be detect by generic pci reousrce allocator for VGA devices. - * BAD: it is more tricky than I think, the resource allocation code is - * implemented in a way to NOT DOING legacy VGA resource allcation on - * purpose :-(. - */ - - typedef struct msr_struct { unsigned lo; @@ -71,6 +55,20 @@ return result; } +/** + * Read resources for AGP aperture. + * + * There is only one AGP aperture resource needed. The resoruce is added to + * the northbridge of BSP. + * + * The same trick can be used to augment legacy VGA resources which can + * be detect by generic PCI resource allocator for VGA devices. + * BAD: it is more tricky than I think, the resource allocation code is + * implemented in a way to NOT DOING legacy VGA resource allcation on + * purpose :-(. + * + * @param dev TODO + */ static void sis761_read_resources(device_t dev) { /* Read the generic PCI resources */ Modified: trunk/src/southbridge/sis/sis966/sis966_lpc.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_lpc.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/southbridge/sis/sis966/sis966_lpc.c Wed Oct 27 00:46:43 2010 (r5993) @@ -184,10 +184,9 @@ } /** - * @brief Enable resources for children devices - * - * @param dev the device whos children's resources are to be enabled + * Enable resources for children devices. * + * @param dev The device whos children's resources are to be enabled. */ static void sis966_lpc_enable_childrens_resources(device_t dev) { Modified: trunk/src/southbridge/sis/sis966/sis966_nic.c ============================================================================== --- trunk/src/southbridge/sis/sis966/sis966_nic.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/southbridge/sis/sis966/sis966_nic.c Wed Oct 27 00:46:43 2010 (r5993) @@ -124,17 +124,14 @@ pci_write_config8(dev, 0x73, bTmp); } -//----------------------------------------------------------------------------- -// Procedure: ReadEEprom -// -// Description: This routine serially reads one word out of the EEPROM. -// -// Arguments: -// Reg - EEPROM word to read. -// -// Returns: -// Contents of EEPROM word (Reg). -//----------------------------------------------------------------------------- +/** + * Read one word out of the serial EEPROM. + * + * @param dev TODO + * @param base TODO + * @param Reg EEPROM word to read. + * @return Contents of EEPROM word (Reg). + */ #define LoopNum 200 static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg) { Modified: trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c Wed Oct 27 00:46:43 2010 (r5993) @@ -23,38 +23,26 @@ #include <arch/romcc_io.h> #include "lpc47b272.h" -/* - * Function: pnp_enter_conf_state - * Parameters: dev - high 8 bits = Super I/O port - * Return Value: None - * Description: Enable access to the LPC47B272's configuration registers. - */ +/** Enable access to the LPC47B272's configuration registers. */ static inline void pnp_enter_conf_state(device_t dev) { unsigned port = dev>>8; outb(0x55, port); } -/* - * Function: pnp_exit_conf_state - * Parameters: dev - high 8 bits = Super I/O port - * Return Value: None - * Description: Disable access to the LPC47B272's configuration registers. - */ +/** Disable access to the LPC47B272's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { unsigned port = dev>>8; outb(0xaa, port); } -/* - * Function: lpc47b272_enable_serial - * Parameters: dev - high 8 bits = Super I/O port, - * low 8 bits = logical device number (per lpc47b272.h) - * iobase - processor I/O port address to assign to this serial device - * Return Value: bool - * Description: Configure the base I/O port of the specified serial device - * and enable the serial device. +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. */ static void lpc47b272_enable_serial(device_t dev, unsigned iobase) { Modified: trunk/src/superio/smsc/lpc47b272/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47b272/superio.c Wed Oct 27 00:46:43 2010 (r5993) @@ -69,30 +69,23 @@ { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, }, }; -/**********************************************************************************/ -/* PUBLIC INTERFACE */ -/**********************************************************************************/ - -/* - * Function: enable_dev - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Create device structures and allocate resources to devices - * specified in the pnp_dev_info array (above). +/** + * Create device structures and allocate resources to devices specified in the + * pnp_dev_info array (above). + * + * @param dev Pointer to structure describing a Super I/O device. */ static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -/* - * Function: lpc47b272_pnp_set_resources - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Configure the specified Super I/O device with the resources - * (I/O space, etc.) that have been allocated for it. +/** + * Configure the specified Super I/O device with the resources (I/O space, + * etc.) that have been allocated for it. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47b272_pnp_set_resources(device_t dev) { @@ -122,13 +115,13 @@ pnp_exit_conf_state(dev); } -/* - * Function: lpc47b272_init - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Initialize the specified Super I/O device. - * Devices other than COM ports and the keyboard controller are - * ignored. For COM ports, we configure the baud rate. +/** + * Initialize the specified Super I/O device. + * + * Devices other than COM ports and the keyboard controller are ignored. + * For COM ports, we configure the baud rate. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47b272_init(device_t dev) { @@ -157,40 +150,25 @@ } } -/**********************************************************************************/ -/* PRIVATE FUNCTIONS */ -/**********************************************************************************/ - -/* - * Function: pnp_enter_conf_state - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Enable access to the LPC47B272's configuration registers. - */ +/** Enable access to the LPC47B272's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/* - * Function: pnp_exit_conf_state - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Disable access to the LPC47B272's configuration registers. - */ +/** Disable access to the LPC47B272's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } #if 0 -/* - * Function: dump_pnp_device - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Print the values of all of the LPC47B272's configuration registers. - * NOTE: The LPC47B272 must be in configuration mode when this - * function is called. +/** + * Print the values of all of the LPC47B272's configuration registers. + * + * NOTE: The LPC47B272 must be in config mode when this function is called. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void dump_pnp_device(device_t dev) { Modified: trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c Wed Oct 27 00:46:43 2010 (r5993) @@ -22,38 +22,26 @@ #include <arch/romcc_io.h> #include "lpc47m10x.h" -/* - * Function: pnp_enter_conf_state - * Parameters: dev - high 8 bits = Super I/O port - * Return Value: None - * Description: Enable access to the LPC47M10X2's configuration registers. - */ +/** Enable access to the LPC47M10X2's configuration registers. */ static inline void pnp_enter_conf_state(device_t dev) { unsigned port = dev>>8; outb(0x55, port); } -/* - * Function: pnp_exit_conf_state - * Parameters: dev - high 8 bits = Super I/O port - * Return Value: None - * Description: Disable access to the LPC47M10X2's configuration registers. - */ +/** Disable access to the LPC47M10X2's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { unsigned port = dev>>8; outb(0xaa, port); } -/* - * Function: lpc47m10x_enable_serial - * Parameters: dev - high 8 bits = Super I/O port, - * low 8 bits = logical device number (per lpc47m10x.h) - * iobase - processor I/O port address to assign to this serial device - * Return Value: bool - * Description: Configure the base I/O port of the specified serial device - * and enable the serial device. +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. */ static void lpc47m10x_enable_serial(device_t dev, unsigned iobase) { Modified: trunk/src/superio/smsc/lpc47m10x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47m10x/superio.c Wed Oct 27 00:46:43 2010 (r5993) @@ -67,30 +67,23 @@ { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, }; -/**********************************************************************************/ -/* PUBLIC INTERFACE */ -/**********************************************************************************/ - -/* - * Function: enable_dev - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Create device structures and allocate resources to devices - * specified in the pnp_dev_info array (above). +/** + * Create device structures and allocate resources to devices specified in the + * pnp_dev_info array (above). + * + * @param dev Pointer to structure describing a Super I/O device. */ static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -/* - * Function: lpc47m10x_pnp_set_resources - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Configure the specified Super I/O device with the resources - * (I/O space, etc.) that have been allocated for it. +/** + * Configure the specified Super I/O device with the resources (I/O space, + * etc.) that have been allocated for it. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47m10x_pnp_set_resources(device_t dev) { @@ -120,13 +113,13 @@ pnp_exit_conf_state(dev); } -/* - * Function: lpc47m10x_init - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Initialize the specified Super I/O device. - * Devices other than COM ports and the keyboard controller are - * ignored. For COM ports, we configure the baud rate. +/** + * Initialize the specified Super I/O device. + * + * Devices other than COM ports and the keyboard controller are ignored. + * For COM ports, we configure the baud rate. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47m10x_init(device_t dev) { @@ -155,40 +148,25 @@ } } -/**********************************************************************************/ -/* PRIVATE FUNCTIONS */ -/**********************************************************************************/ - -/* - * Function: pnp_enter_conf_state - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Enable access to the LPC47M10X2's configuration registers. - */ +/** Enable access to the LPC47M10X2's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/* - * Function: pnp_exit_conf_state - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Disable access to the LPC47M10X2's configuration registers. - */ +/** Disable access to the LPC47M10X2's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } #if 0 -/* - * Function: dump_pnp_device - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Print the values of all of the LPC47M10X2's configuration registers. - * NOTE: The LPC47M10X2 must be in configuration mode when this - * function is called. +/** + * Print the values of all of the LPC47M10X2's configuration registers. + * + * NOTE: The LPC47M10X2 must be in config mode when this function is called. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void dump_pnp_device(device_t dev) { Modified: trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c Wed Oct 27 00:46:43 2010 (r5993) @@ -24,38 +24,25 @@ #include <assert.h> #include "lpc47n217.h" -/* - * Function: pnp_enter_conf_state - * Parameters: dev - high 8 bits = Super I/O port - * Return Value: None - * Description: Enable access to the LPC47N217's configuration registers. - */ +/** Enable access to the LPC47N217's configuration registers. */ static inline void pnp_enter_conf_state(device_t dev) { unsigned port = dev>>8; outb(0x55, port); } -/* - * Function: pnp_exit_conf_state - * Parameters: dev - high 8 bits = Super I/O port - * Return Value: None - * Description: Disable access to the LPC47N217's configuration registers. - */ +/** Disable access to the LPC47N217's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { unsigned port = dev>>8; outb(0xaa, port); } -/* - * Function: lpc47n217_pnp_set_iobase - * Parameters: dev - high 8 bits = Super I/O port, - * low 8 bits = logical device number (per lpc47n217.h) - * iobase - base I/O port for the logical device - * Return Value:None - * Description: Program the base I/O port for the specified logical device. +/** + * Program the base I/O port for the specified logical device. * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Base I/O port for the logical device. */ void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase) { @@ -80,19 +67,17 @@ } } -/* - * Function: lpc47n217_pnp_set_enable - * Parameters: dev - high 8 bits = Super I/O port, - * low 8 bits = logical device number (per lpc47n217.h) - * enable - 0 to disable, anythig else to enable - * Return Value:None - * Description: Enable or disable the specified logical device. - * Technically, a full disable requires setting the device's base - * I/O port below 0x100. We don't do that here, because we don't - * have access to a data structure that specifies what the 'real' - * base port is (when asked to enable the device). Also the function - * is used only to disable the device while its true base port is - * programmed (see lpc47n217_enable_serial() below). +/** + * Enable or disable the specified logical device. + * + * Technically, a full disable requires setting the device's base I/O port + * below 0x100. We don't do that here, because we don't have access to a data + * structure that specifies what the 'real' base port is (when asked to enable + * the device). Also the function is used only to disable the device while its + * true base port is programmed (see lpc47n217_enable_serial() below). + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param enable 0 to disable, anythig else to enable. */ void lpc47n217_pnp_set_enable(device_t dev, int enable) { @@ -130,20 +115,19 @@ pnp_write_config(dev, power_register, new_power); } -/* - * Function: lpc47n217_enable_serial - * Parameters: dev - high 8 bits = Super I/O port, - * low 8 bits = logical device number (per lpc47n217.h) - * iobase - processor I/O port address to assign to this serial device - * Return Value:bool - * Description: Configure the base I/O port of the specified serial device - * and enable the serial device. +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. */ static void lpc47n217_enable_serial(device_t dev, unsigned iobase) { - /* NOTE: Cannot use pnp_set_XXX() here because they assume chip - * support for logical devices, which the LPC47N217 doesn't have*/ - + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N217 doesn't have. + */ pnp_enter_conf_state(dev); lpc47n217_pnp_set_enable(dev, 0); lpc47n217_pnp_set_iobase(dev, iobase); Modified: trunk/src/superio/smsc/lpc47n217/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n217/superio.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47n217/superio.c Wed Oct 27 00:46:43 2010 (r5993) @@ -72,30 +72,23 @@ { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, } }; -/**********************************************************************************/ -/* PUBLIC INTERFACE */ -/**********************************************************************************/ - -/* - * Function: enable_dev - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Create device structures and allocate resources to devices - * specified in the pnp_dev_info array (above). +/** + * Create device structures and allocate resources to devices specified in the + * pnp_dev_info array (above). + * + * @param dev Pointer to structure describing a Super I/O device. */ static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -/* - * Function: lpc47n217_pnp_set_resources - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Configure the specified Super I/O device with the resources - * (I/O space, etc.) that have been allocate for it. +/** + * Configure the specified Super I/O device with the resources (I/O space, + * etc.) that have been allocate for it. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47n217_pnp_set_resources(device_t dev) { @@ -118,8 +111,9 @@ { pnp_enter_conf_state(dev); - /* NOTE: Cannot use pnp_enable_resources() here because it assumes chip - * support for logical devices, which the LPC47N217 doesn't have + /* + * NOTE: Cannot use pnp_enable_resources() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have. */ lpc47n217_pnp_set_enable(dev, 1); @@ -130,10 +124,10 @@ { pnp_enter_conf_state(dev); - /* NOTE: Cannot use pnp_set_enable() here because it assumes chip - * support for logical devices, which the LPC47N217 doesn't have + /* + * NOTE: Cannot use pnp_set_enable() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have. */ - if(dev->enabled) { lpc47n217_pnp_set_enable(dev, 1); } @@ -144,13 +138,13 @@ pnp_exit_conf_state(dev); } -/* - * Function: lpc47n217_init - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Initialize the specified Super I/O device. - * Devices other than COM ports are ignored. - * For COM ports, we configure the baud rate. +/** + * Initialize the specified Super I/O device. + * + * Devices other than COM ports are ignored. For COM ports, we configure the + * baud rate. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47n217_init(device_t dev) { @@ -173,10 +167,6 @@ } } -/**********************************************************************************/ -/* PRIVATE FUNCTIONS */ -/**********************************************************************************/ - static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { @@ -186,10 +176,10 @@ } /* Now store the resource */ - /* NOTE: Cannot use pnp_set_XXX() here because they assume chip - * support for logical devices, which the LPC47N217 doesn't have + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N217 doesn't have. */ - if (resource->flags & IORESOURCE_IO) { lpc47n217_pnp_set_iobase(dev, resource->base); } @@ -327,36 +317,25 @@ pnp_write_config(dev, power_register, new_power); } -/* - * Function: pnp_enter_conf_state - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Enable access to the LPC47N217's configuration registers. - */ +/** Enable access to the LPC47N217's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/* - * Function: pnp_exit_conf_state - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Disable access to the LPC47N217's configuration registers. - */ +/** Disable access to the LPC47N217's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } #if 0 -/* - * Function: dump_pnp_device - * Parameters: dev - pointer to structure describing a Super I/O device - * Return Value: None - * Description: Print the values of all of the LPC47N217's configuration registers. - * NOTE: The LPC47N217 must be in configuration mode when this - * function is called. +/** + * Print the values of all of the LPC47N217's configuration registers. + * + * NOTE: The LPC47N217 must be in config mode when this function is called. + * + * @param dev Pointer to structure describing a Super I/O device. */ static void dump_pnp_device(device_t dev) { Modified: trunk/src/superio/smsc/lpc47n227/lpc47n227.h ============================================================================== --- trunk/src/superio/smsc/lpc47n227/lpc47n227.h Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47n227/lpc47n227.h Wed Oct 27 00:46:43 2010 (r5993) @@ -17,9 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Since the LPC47N227 does not have logical devices but a flat configuration +/* + * Since the LPC47N227 does not have logical devices but a flat configuration * space, these are arbitrary, but must match declarations in the mainboard - * devicetree.cb + * devicetree.cb. */ #define LPC47N227_PP 1 /* Parallel Port */ #define LPC47N227_SP1 2 /* COM1 */ Modified: trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c Wed Oct 27 00:46:43 2010 (r5993) @@ -23,38 +23,34 @@ #include <arch/romcc_io.h> #include "lpc47n227.h" -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Enable access to the LPC47N227's configuration registers. -// +/** + * Enable access to the LPC47N227's configuration registers. + * + * @param dev High 8 bits = Super I/O port. + */ static inline void pnp_enter_conf_state(device_t dev) { unsigned port = dev >> 8; outb(0x55, port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - high 8 bits = Super I/O port -// Return Value: None -// Description: Disable access to the LPC47N227's configuration registers. -// +/** + * Disable access to the LPC47N227's configuration registers. + * + * @param dev High 8 bits = Super I/O port. + */ static void pnp_exit_conf_state(device_t dev) { unsigned port = dev >> 8; outb(0xaa, port); } -//---------------------------------------------------------------------------------- -// Function: lpc47n227_pnp_set_iobase -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47n227.h) -// iobase - base I/O port for the logical device -// Return Value: None -// Description: Program the base I/O port for the specified logical device. -// +/** + * Program the base I/O port for the specified logical device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Base I/O port for the logical device. + */ void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase) { // LPC47N227 requires base ports to be a multiple of 4 @@ -78,20 +74,18 @@ } } -//---------------------------------------------------------------------------------- -// Function: lpc47n227_pnp_set_enable -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47n227.h) -// enable - 0 to disable, anythig else to enable -// Return Value: None -// Description: Enable or disable the specified logical device. -// Technically, a full disable requires setting the device's base -// I/O port below 0x100. We don't do that here, because we don't -// have access to a data structure that specifies what the 'real' -// base port is (when asked to enable the device). Also the function -// is used only to disable the device while its true base port is -// programmed (see lpc47n227_enable_serial() below). -// +/** + * Enable or disable the specified logical device. + * + * Technically, a full disable requires setting the device's base I/O port + * below 0x100. We don't do that here, because we don't have access to a data + * structure that specifies what the 'real' base port is (when asked to enable + * the device). Also the function is used only to disable the device while its + * true base port is programmed (see lpc47n227_enable_serial() below). + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param enable 0 to disable, anythig else to enable. + */ void lpc47n227_pnp_set_enable(device_t dev, int enable) { uint8_t power_register = 0; @@ -128,20 +122,19 @@ pnp_write_config(dev, power_register, new_power); } -//---------------------------------------------------------------------------------- -// Function: lpc47n227_enable_serial -// Parameters: dev - high 8 bits = Super I/O port, -// low 8 bits = logical device number (per lpc47n227.h) -// iobase - processor I/O port address to assign to this serial device -// Return Value: bool -// Description: Configure the base I/O port of the specified serial device -// and enable the serial device. -// +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ static void lpc47n227_enable_serial(device_t dev, unsigned iobase) { - // NOTE: Cannot use pnp_set_XXX() here because they assume chip - // support for logical devices, which the LPC47N227 doesn't have - + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N227 doesn't have. + */ pnp_enter_conf_state(dev); lpc47n227_pnp_set_enable(dev, 0); lpc47n227_pnp_set_iobase(dev, iobase); Modified: trunk/src/superio/smsc/lpc47n227/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n227/superio.c Wed Oct 27 00:40:16 2010 (r5992) +++ trunk/src/superio/smsc/lpc47n227/superio.c Wed Oct 27 00:46:43 2010 (r5993) @@ -70,38 +70,34 @@ {0x7f8, 0x4},} }; -/**********************************************************************************/ -/* PUBLIC INTERFACE */ -/**********************************************************************************/ - -//---------------------------------------------------------------------------------- -// Function: enable_dev -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Create device structures and allocate resources to devices -// specified in the pnp_dev_info array (above). -// +/** + * Create device structures and allocate resources to devices specified in the + * pnp_dev_info array (above). + * + * @param dev Pointer to structure describing a Super I/O device. + */ static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -//---------------------------------------------------------------------------------- -// Function: lpc47n227_pnp_set_resources -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Configure the specified Super I/O device with the resources -// (I/O space, etc.) that have been allocate for it. -// +/** + * Configure the specified Super I/O device with the resources (I/O space, + * etc.) that have been allocate for it. + * + * @param dev Pointer to structure describing a Super I/O device. + */ void lpc47n227_pnp_set_resources(device_t dev) { struct resource *res; pnp_enter_conf_state(dev); - // NOTE: Cannot use pnp_set_resources() here because it assumes chip - // support for logical devices, which the LPC47N227 doesn't have + /* + * NOTE: Cannot use pnp_set_resources() here because it assumes chip + * support for logical devices, which the LPC47N227 doesn't have. + */ for (res = dev->resource_list; res; res = res->next) lpc47n227_pnp_set_resource(dev, res); @@ -112,8 +108,10 @@ { pnp_enter_conf_state(dev); - // NOTE: Cannot use pnp_enable_resources() here because it assumes chip - // support for logical devices, which the LPC47N227 doesn't have + /* + * NOTE: Cannot use pnp_enable_resources() here because it assumes chip + * support for logical devices, which the LPC47N227 doesn't have. + */ lpc47n227_pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); @@ -123,9 +121,10 @@ { pnp_enter_conf_state(dev); - // NOTE: Cannot use pnp_set_enable() here because it assumes chip - // support for logical devices, which the LPC47N227 doesn't have - + /* + * NOTE: Cannot use pnp_set_enable() here because it assumes chip + * support for logical devices, which the LPC47N227 doesn't have. + */ if (dev->enabled) { lpc47n227_pnp_set_enable(dev, 1); } else { @@ -135,14 +134,14 @@ pnp_exit_conf_state(dev); } -//---------------------------------------------------------------------------------- -// Function: lpc47n227_init -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Initialize the specified Super I/O device. -// Devices other than COM ports and keyboard controller are ignored. -// For COM ports, we configure the baud rate. -// +/** + * Initialize the specified Super I/O device. + * + * Devices other than COM ports and keyboard controller are ignored. + * For COM ports, we configure the baud rate. + * + * @param dev Pointer to structure describing a Super I/O device. + */ static void lpc47n227_init(device_t dev) { struct superio_smsc_lpc47n227_config *conf = dev->chip_info; @@ -169,10 +168,6 @@ } } -/**********************************************************************************/ -/* PRIVATE FUNCTIONS */ -/**********************************************************************************/ - static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { @@ -182,9 +177,10 @@ } /* Now store the resource */ - // NOTE: Cannot use pnp_set_XXX() here because they assume chip - // support for logical devices, which the LPC47N227 doesn't have - + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N227 doesn't have. + */ if (resource->flags & IORESOURCE_IO) { lpc47n227_pnp_set_iobase(dev, resource->base); } else if (resource->flags & IORESOURCE_DRQ) { @@ -328,25 +324,14 @@ pnp_write_config(dev, power_register, new_power); } -//---------------------------------------------------------------------------------- -// Function: pnp_enter_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Enable access to the LPC47N227's configuration registers. -// +/** Enable access to the LPC47N227's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -//---------------------------------------------------------------------------------- -// Function: pnp_exit_conf_state -// Parameters: dev - pointer to structure describing a Super I/O device -// Return Value: None -// Description: Disable access to the LPC47N227's configuration registers. -// +/** Disable access to the LPC47N227's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } -

1 0

[PATCH] Fix util/mptable typo
by Tobias Diedrich 26 Oct '10

26 Oct '10

We need to call smp_write_lintsrc instead of smp_write_intsrc for local ints. This is wrong in most coreboot mptables, probably all generated by util/mptable.c After fixing this now XP can boot in MPS mode on my M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: src/mainboard/iwill/dk8_htx/mptable.c =================================================================== --- src/mainboard/iwill/dk8_htx/mptable.c (revision 5991) +++ src/mainboard/iwill/dk8_htx/mptable.c (working copy) @@ -173,8 +173,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/asrock/939a785gmh/mptable.c =================================================================== --- src/mainboard/asrock/939a785gmh/mptable.c (revision 5991) +++ src/mainboard/asrock/939a785gmh/mptable.c (working copy) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/getac/p470/mptable.c =================================================================== --- src/mainboard/getac/p470/mptable.c (revision 5991) +++ src/mainboard/getac/p470/mptable.c (working copy) @@ -81,8 +81,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Index: src/mainboard/broadcom/blast/mptable.c =================================================================== --- src/mainboard/broadcom/blast/mptable.c (revision 5991) +++ src/mainboard/broadcom/blast/mptable.c (working copy) @@ -137,8 +137,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/supermicro/h8dmr/mptable.c =================================================================== --- src/mainboard/supermicro/h8dmr/mptable.c (revision 5991) +++ src/mainboard/supermicro/h8dmr/mptable.c (working copy) @@ -125,8 +125,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/supermicro/h8dme/mptable.c =================================================================== --- src/mainboard/supermicro/h8dme/mptable.c (revision 5991) +++ src/mainboard/supermicro/h8dme/mptable.c (working copy) @@ -124,8 +124,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/supermicro/h8dmr_fam10/mptable.c =================================================================== --- src/mainboard/supermicro/h8dmr_fam10/mptable.c (revision 5991) +++ src/mainboard/supermicro/h8dmr_fam10/mptable.c (working copy) @@ -110,8 +110,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/supermicro/h8qme_fam10/mptable.c =================================================================== --- src/mainboard/supermicro/h8qme_fam10/mptable.c (revision 5991) +++ src/mainboard/supermicro/h8qme_fam10/mptable.c (working copy) @@ -108,8 +108,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/kontron/986lcd-m/mptable.c =================================================================== --- src/mainboard/kontron/986lcd-m/mptable.c (revision 5991) +++ src/mainboard/kontron/986lcd-m/mptable.c (working copy) @@ -102,8 +102,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Index: src/mainboard/kontron/kt690/mptable.c =================================================================== --- src/mainboard/kontron/kt690/mptable.c (revision 5991) +++ src/mainboard/kontron/kt690/mptable.c (working copy) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Index: src/mainboard/gigabyte/m57sli/mptable.c =================================================================== --- src/mainboard/gigabyte/m57sli/mptable.c (revision 5991) +++ src/mainboard/gigabyte/m57sli/mptable.c (working copy) @@ -119,8 +119,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/gigabyte/ma78gm/mptable.c =================================================================== --- src/mainboard/gigabyte/ma78gm/mptable.c (revision 5991) +++ src/mainboard/gigabyte/ma78gm/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/gigabyte/ga_2761gxdk/mptable.c =================================================================== --- src/mainboard/gigabyte/ga_2761gxdk/mptable.c (revision 5991) +++ src/mainboard/gigabyte/ga_2761gxdk/mptable.c (working copy) @@ -113,8 +113,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/gigabyte/ma785gmt/mptable.c =================================================================== --- src/mainboard/gigabyte/ma785gmt/mptable.c (revision 5991) +++ src/mainboard/gigabyte/ma785gmt/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/amd/mahogany/mptable.c =================================================================== --- src/mainboard/amd/mahogany/mptable.c (revision 5991) +++ src/mainboard/amd/mahogany/mptable.c (working copy) @@ -101,7 +101,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/amd/pistachio/mptable.c =================================================================== --- src/mainboard/amd/pistachio/mptable.c (revision 5991) +++ src/mainboard/amd/pistachio/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Index: src/mainboard/amd/dbm690t/mptable.c =================================================================== --- src/mainboard/amd/dbm690t/mptable.c (revision 5991) +++ src/mainboard/amd/dbm690t/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Index: src/mainboard/amd/serengeti_cheetah/mptable.c =================================================================== --- src/mainboard/amd/serengeti_cheetah/mptable.c (revision 5991) +++ src/mainboard/amd/serengeti_cheetah/mptable.c (working copy) @@ -161,8 +161,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/amd/mahogany_fam10/mptable.c =================================================================== --- src/mainboard/amd/mahogany_fam10/mptable.c (revision 5991) +++ src/mainboard/amd/mahogany_fam10/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/amd/tilapia_fam10/mptable.c =================================================================== --- src/mainboard/amd/tilapia_fam10/mptable.c (revision 5991) +++ src/mainboard/amd/tilapia_fam10/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/amd/serengeti_cheetah_fam10/mptable.c =================================================================== --- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c (revision 5991) +++ src/mainboard/amd/serengeti_cheetah_fam10/mptable.c (working copy) @@ -185,8 +185,8 @@ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/iei/kino-780am2-fam10/mptable.c =================================================================== --- src/mainboard/iei/kino-780am2-fam10/mptable.c (revision 5991) +++ src/mainboard/iei/kino-780am2-fam10/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/hp/dl145_g1/mptable.c =================================================================== --- src/mainboard/hp/dl145_g1/mptable.c (revision 5991) +++ src/mainboard/hp/dl145_g1/mptable.c (working copy) @@ -90,8 +90,8 @@ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/hp/dl145_g3/mptable.c =================================================================== --- src/mainboard/hp/dl145_g3/mptable.c (revision 5991) +++ src/mainboard/hp/dl145_g3/mptable.c (working copy) @@ -178,8 +178,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa); - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1); //extended table entries smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); Index: src/mainboard/hp/dl165_g6_fam10/mptable.c =================================================================== --- src/mainboard/hp/dl165_g6_fam10/mptable.c (revision 5991) +++ src/mainboard/hp/dl165_g6_fam10/mptable.c (working copy) @@ -143,8 +143,8 @@ } /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); //extended table entries smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); Index: src/mainboard/tyan/s2912/mptable.c =================================================================== --- src/mainboard/tyan/s2912/mptable.c (revision 5991) +++ src/mainboard/tyan/s2912/mptable.c (working copy) @@ -108,8 +108,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2850/mptable.c =================================================================== --- src/mainboard/tyan/s2850/mptable.c (revision 5991) +++ src/mainboard/tyan/s2850/mptable.c (working copy) @@ -148,8 +148,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, apicid_8111, 0x10); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2735/mptable.c =================================================================== --- src/mainboard/tyan/s2735/mptable.c (revision 5991) +++ src/mainboard/tyan/s2735/mptable.c (working copy) @@ -79,8 +79,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); /* MP Config Extended Table Entries: Index: src/mainboard/tyan/s2880/mptable.c =================================================================== --- src/mainboard/tyan/s2880/mptable.c (revision 5991) +++ src/mainboard/tyan/s2880/mptable.c (working copy) @@ -191,8 +191,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2881/mptable.c =================================================================== --- src/mainboard/tyan/s2881/mptable.c (revision 5991) +++ src/mainboard/tyan/s2881/mptable.c (working copy) @@ -102,8 +102,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s4880/mptable.c =================================================================== --- src/mainboard/tyan/s4880/mptable.c (revision 5991) +++ src/mainboard/tyan/s4880/mptable.c (working copy) @@ -197,8 +197,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2891/mptable.c =================================================================== --- src/mainboard/tyan/s2891/mptable.c (revision 5991) +++ src/mainboard/tyan/s2891/mptable.c (working copy) @@ -138,8 +138,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2882/mptable.c =================================================================== --- src/mainboard/tyan/s2882/mptable.c (revision 5991) +++ src/mainboard/tyan/s2882/mptable.c (working copy) @@ -213,8 +213,8 @@ #endif /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2892/mptable.c =================================================================== --- src/mainboard/tyan/s2892/mptable.c (revision 5991) +++ src/mainboard/tyan/s2892/mptable.c (working copy) @@ -160,8 +160,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s4882/mptable.c =================================================================== --- src/mainboard/tyan/s4882/mptable.c (revision 5991) +++ src/mainboard/tyan/s4882/mptable.c (working copy) @@ -196,8 +196,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2875/mptable.c =================================================================== --- src/mainboard/tyan/s2875/mptable.c (revision 5991) +++ src/mainboard/tyan/s2875/mptable.c (working copy) @@ -165,8 +165,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2885/mptable.c =================================================================== --- src/mainboard/tyan/s2885/mptable.c (revision 5991) +++ src/mainboard/tyan/s2885/mptable.c (working copy) @@ -113,8 +113,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2895/mptable.c =================================================================== --- src/mainboard/tyan/s2895/mptable.c (revision 5991) +++ src/mainboard/tyan/s2895/mptable.c (working copy) @@ -188,8 +188,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/tyan/s2912_fam10/mptable.c =================================================================== --- src/mainboard/tyan/s2912_fam10/mptable.c (revision 5991) +++ src/mainboard/tyan/s2912_fam10/mptable.c (working copy) @@ -108,8 +108,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/via/vt8454c/mptable.c =================================================================== --- src/mainboard/via/vt8454c/mptable.c (revision 5991) +++ src/mainboard/via/vt8454c/mptable.c (working copy) @@ -55,8 +55,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Index: src/mainboard/via/epia-n/mptable.c =================================================================== --- src/mainboard/via/epia-n/mptable.c (revision 5991) +++ src/mainboard/via/epia-n/mptable.c (working copy) @@ -66,8 +66,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/ibase/mb899/mptable.c =================================================================== --- src/mainboard/ibase/mb899/mptable.c (revision 5991) +++ src/mainboard/ibase/mb899/mptable.c (working copy) @@ -130,8 +130,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Index: src/mainboard/roda/rk886ex/mptable.c =================================================================== --- src/mainboard/roda/rk886ex/mptable.c (revision 5991) +++ src/mainboard/roda/rk886ex/mptable.c (working copy) @@ -81,8 +81,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Index: src/mainboard/msi/ms9282/mptable.c =================================================================== --- src/mainboard/msi/ms9282/mptable.c (revision 5991) +++ src/mainboard/msi/ms9282/mptable.c (working copy) @@ -121,8 +121,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/msi/ms9185/mptable.c =================================================================== --- src/mainboard/msi/ms9185/mptable.c (revision 5991) +++ src/mainboard/msi/ms9185/mptable.c (working copy) @@ -152,8 +152,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/msi/ms9652_fam10/mptable.c =================================================================== --- src/mainboard/msi/ms9652_fam10/mptable.c (revision 5991) +++ src/mainboard/msi/ms9652_fam10/mptable.c (working copy) @@ -110,8 +110,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/msi/ms7260/mptable.c =================================================================== --- src/mainboard/msi/ms7260/mptable.c (revision 5991) +++ src/mainboard/msi/ms7260/mptable.c (working copy) @@ -102,8 +102,8 @@ } /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ Index: src/mainboard/sunw/ultra40/mptable.c =================================================================== --- src/mainboard/sunw/ultra40/mptable.c (revision 5991) +++ src/mainboard/sunw/ultra40/mptable.c (working copy) @@ -189,8 +189,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/jetway/pa78vm5/mptable.c =================================================================== --- src/mainboard/jetway/pa78vm5/mptable.c (revision 5991) +++ src/mainboard/jetway/pa78vm5/mptable.c (working copy) @@ -101,7 +101,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/technexion/tim8690/mptable.c =================================================================== --- src/mainboard/technexion/tim8690/mptable.c (revision 5991) +++ src/mainboard/technexion/tim8690/mptable.c (working copy) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Index: src/mainboard/technexion/tim5690/mptable.c =================================================================== --- src/mainboard/technexion/tim5690/mptable.c (revision 5991) +++ src/mainboard/technexion/tim5690/mptable.c (working copy) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Index: src/mainboard/nvidia/l1_2pvv/mptable.c =================================================================== --- src/mainboard/nvidia/l1_2pvv/mptable.c (revision 5991) +++ src/mainboard/nvidia/l1_2pvv/mptable.c (working copy) @@ -167,8 +167,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Index: src/mainboard/intel/xe7501devkit/mptable.c =================================================================== --- src/mainboard/intel/xe7501devkit/mptable.c (revision 5991) +++ src/mainboard/intel/xe7501devkit/mptable.c (working copy) @@ -73,8 +73,8 @@ { // Chipset PCI bus // Type Trigger | Polarity Bus ID IRQ APIC ID PIN# - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3 Index: src/mainboard/intel/d945gclf/mptable.c =================================================================== --- src/mainboard/intel/d945gclf/mptable.c (revision 5991) +++ src/mainboard/intel/d945gclf/mptable.c (working copy) @@ -86,8 +86,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Index: src/mainboard/intel/eagleheights/mptable.c =================================================================== --- src/mainboard/intel/eagleheights/mptable.c (revision 5991) +++ src/mainboard/intel/eagleheights/mptable.c (working copy) @@ -166,8 +166,8 @@ mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1); /* Internal PCI device for i3100 */ Index: src/mainboard/asus/m4a785-m/mptable.c =================================================================== --- src/mainboard/asus/m4a785-m/mptable.c (revision 5991) +++ src/mainboard/asus/m4a785-m/mptable.c (working copy) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Index: src/mainboard/asus/p2b-d/mptable.c =================================================================== --- src/mainboard/asus/p2b-d/mptable.c (revision 5991) +++ src/mainboard/asus/p2b-d/mptable.c (working copy) @@ -79,10 +79,10 @@ 0x2, 0xa, 0x2, 0x13); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ Index: src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- src/mainboard/asus/a8v-e_se/mptable.c (revision 5991) +++ src/mainboard/asus/a8v-e_se/mptable.c (working copy) @@ -109,8 +109,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums. */ Index: src/mainboard/asus/p2b-ds/mptable.c =================================================================== --- src/mainboard/asus/p2b-ds/mptable.c (revision 5991) +++ src/mainboard/asus/p2b-ds/mptable.c (working copy) @@ -81,10 +81,10 @@ 0x0, 0x30, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ Index: src/mainboard/asus/a8n_e/mptable.c =================================================================== --- src/mainboard/asus/a8n_e/mptable.c (revision 5991) +++ src/mainboard/asus/a8n_e/mptable.c (working copy) @@ -116,10 +116,10 @@ 0x17); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x1); Index: util/mptable/mptable.c =================================================================== --- util/mptable/mptable.c (revision 5991) +++ util/mptable/mptable.c (working copy) @@ -1179,7 +1179,7 @@ printf( "\t %6d", (int)entry.dstApicID ); printf( "\t %3d\n", (int)entry.dstApicINT ); } - printf("\tsmp_write_intsrc(mc, %s, %s|%s, 0x%x, 0x%x, MP_APIC_ALL, 0x%x);\n", + printf("\tsmp_write_lintsrc(mc, %s, %s|%s, 0x%x, 0x%x, MP_APIC_ALL, 0x%x);\n", intTypes[ (int)entry.intType ], triggerMode[ ((int)entry.intFlags >> 2) & 0x03 ] , polarityMode[ (int)entry.intFlags & 0x03 ],

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[commit] r5992 - in trunk: src/mainboard/amd/dbm690t src/mainboard/amd/mahogany src/mainboard/amd/mahogany_fam10 src/mainboard/amd/pistachio src/mainboard/amd/serengeti_cheetah src/mainboard/amd/se...
by repository service 26 Oct '10

26 Oct '10

Author: uwe Date: Wed Oct 27 00:40:16 2010 New Revision: 5992 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5992 Log: We need to call smp_write_lintsrc() instead of smp_write_intsrc() for local ints. This is wrong in most coreboot mptables, probably all generated by util/mptable/mptable.c. After fixing this now XP can boot in MPS mode on my M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/amd/dbm690t/mptable.c trunk/src/mainboard/amd/mahogany/mptable.c trunk/src/mainboard/amd/mahogany_fam10/mptable.c trunk/src/mainboard/amd/pistachio/mptable.c trunk/src/mainboard/amd/serengeti_cheetah/mptable.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c trunk/src/mainboard/amd/tilapia_fam10/mptable.c trunk/src/mainboard/asrock/939a785gmh/mptable.c trunk/src/mainboard/asus/a8n_e/mptable.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/asus/m4a785-m/mptable.c trunk/src/mainboard/asus/p2b-d/mptable.c trunk/src/mainboard/asus/p2b-ds/mptable.c trunk/src/mainboard/broadcom/blast/mptable.c trunk/src/mainboard/getac/p470/mptable.c trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c trunk/src/mainboard/gigabyte/m57sli/mptable.c trunk/src/mainboard/gigabyte/ma785gmt/mptable.c trunk/src/mainboard/gigabyte/ma78gm/mptable.c trunk/src/mainboard/hp/dl145_g1/mptable.c trunk/src/mainboard/hp/dl145_g3/mptable.c trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c trunk/src/mainboard/ibase/mb899/mptable.c trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c trunk/src/mainboard/intel/d945gclf/mptable.c trunk/src/mainboard/intel/eagleheights/mptable.c trunk/src/mainboard/intel/xe7501devkit/mptable.c trunk/src/mainboard/iwill/dk8_htx/mptable.c trunk/src/mainboard/jetway/pa78vm5/mptable.c trunk/src/mainboard/kontron/986lcd-m/mptable.c trunk/src/mainboard/kontron/kt690/mptable.c trunk/src/mainboard/msi/ms7260/mptable.c trunk/src/mainboard/msi/ms9185/mptable.c trunk/src/mainboard/msi/ms9282/mptable.c trunk/src/mainboard/msi/ms9652_fam10/mptable.c trunk/src/mainboard/nvidia/l1_2pvv/mptable.c trunk/src/mainboard/roda/rk886ex/mptable.c trunk/src/mainboard/sunw/ultra40/mptable.c trunk/src/mainboard/supermicro/h8dme/mptable.c trunk/src/mainboard/supermicro/h8dmr/mptable.c trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c trunk/src/mainboard/technexion/tim5690/mptable.c trunk/src/mainboard/technexion/tim8690/mptable.c trunk/src/mainboard/tyan/s2735/mptable.c trunk/src/mainboard/tyan/s2850/mptable.c trunk/src/mainboard/tyan/s2875/mptable.c trunk/src/mainboard/tyan/s2880/mptable.c trunk/src/mainboard/tyan/s2881/mptable.c trunk/src/mainboard/tyan/s2882/mptable.c trunk/src/mainboard/tyan/s2885/mptable.c trunk/src/mainboard/tyan/s2891/mptable.c trunk/src/mainboard/tyan/s2892/mptable.c trunk/src/mainboard/tyan/s2895/mptable.c trunk/src/mainboard/tyan/s2912/mptable.c trunk/src/mainboard/tyan/s2912_fam10/mptable.c trunk/src/mainboard/tyan/s4880/mptable.c trunk/src/mainboard/tyan/s4882/mptable.c trunk/src/mainboard/via/epia-n/mptable.c trunk/src/mainboard/via/vt8454c/mptable.c trunk/util/mptable/mptable.c Modified: trunk/src/mainboard/amd/dbm690t/mptable.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/dbm690t/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Modified: trunk/src/mainboard/amd/mahogany/mptable.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/mahogany/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -101,7 +101,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/amd/mahogany_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/mahogany_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/amd/pistachio/mptable.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/pistachio/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Modified: trunk/src/mainboard/amd/serengeti_cheetah/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -161,8 +161,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -185,8 +185,8 @@ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/amd/tilapia_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/amd/tilapia_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/asrock/939a785gmh/mptable.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/asrock/939a785gmh/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/asus/a8n_e/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/asus/a8n_e/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -116,10 +116,10 @@ 0x17); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x1); Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -109,8 +109,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums. */ Modified: trunk/src/mainboard/asus/m4a785-m/mptable.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/asus/m4a785-m/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/asus/p2b-d/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/asus/p2b-d/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -79,10 +79,10 @@ 0x2, 0xa, 0x2, 0x13); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ Modified: trunk/src/mainboard/asus/p2b-ds/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/asus/p2b-ds/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -81,10 +81,10 @@ 0x0, 0x30, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ Modified: trunk/src/mainboard/broadcom/blast/mptable.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/broadcom/blast/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -137,8 +137,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/getac/p470/mptable.c ============================================================================== --- trunk/src/mainboard/getac/p470/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/getac/p470/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -81,8 +81,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -113,8 +113,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/gigabyte/m57sli/mptable.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/gigabyte/m57sli/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -119,8 +119,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/gigabyte/ma785gmt/mptable.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/gigabyte/ma785gmt/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/gigabyte/ma78gm/mptable.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/gigabyte/ma78gm/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/hp/dl145_g1/mptable.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/hp/dl145_g1/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -90,8 +90,8 @@ //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/hp/dl145_g3/mptable.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/hp/dl145_g3/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -178,8 +178,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa); - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1); //extended table entries smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); Modified: trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -143,8 +143,8 @@ } /* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); //extended table entries smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001); Modified: trunk/src/mainboard/ibase/mb899/mptable.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/ibase/mb899/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -130,8 +130,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -100,7 +100,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/intel/d945gclf/mptable.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/intel/d945gclf/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -86,8 +86,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/intel/eagleheights/mptable.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/intel/eagleheights/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -166,8 +166,8 @@ mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1); /* Internal PCI device for i3100 */ Modified: trunk/src/mainboard/intel/xe7501devkit/mptable.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/intel/xe7501devkit/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -73,8 +73,8 @@ { // Chipset PCI bus // Type Trigger | Polarity Bus ID IRQ APIC ID PIN# - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3 Modified: trunk/src/mainboard/iwill/dk8_htx/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/iwill/dk8_htx/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -173,8 +173,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/jetway/pa78vm5/mptable.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/jetway/pa78vm5/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -101,7 +101,7 @@ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); Modified: trunk/src/mainboard/kontron/986lcd-m/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/kontron/986lcd-m/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -102,8 +102,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/kontron/kt690/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/kontron/kt690/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Modified: trunk/src/mainboard/msi/ms7260/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/msi/ms7260/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -102,8 +102,8 @@ } /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ Modified: trunk/src/mainboard/msi/ms9185/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/msi/ms9185/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -152,8 +152,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/msi/ms9282/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/msi/ms9282/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -121,8 +121,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/msi/ms9652_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/msi/ms9652_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -110,8 +110,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/nvidia/l1_2pvv/mptable.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/nvidia/l1_2pvv/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -167,8 +167,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/roda/rk886ex/mptable.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/roda/rk886ex/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -81,8 +81,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/sunw/ultra40/mptable.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/sunw/ultra40/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -189,8 +189,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/supermicro/h8dme/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/supermicro/h8dme/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -124,8 +124,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/supermicro/h8dmr/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/supermicro/h8dmr/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -125,8 +125,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -110,8 +110,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -108,8 +108,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/technexion/tim5690/mptable.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/technexion/tim5690/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Modified: trunk/src/mainboard/technexion/tim8690/mptable.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/technexion/tim8690/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -99,7 +99,7 @@ } #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); Modified: trunk/src/mainboard/tyan/s2735/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2735/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -79,8 +79,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1); /* MP Config Extended Table Entries: Modified: trunk/src/mainboard/tyan/s2850/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2850/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -148,8 +148,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, apicid_8111, 0x10); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2875/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2875/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -165,8 +165,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2880/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -191,8 +191,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2881/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2881/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -102,8 +102,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2882/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -213,8 +213,8 @@ #endif /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2885/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2885/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -113,8 +113,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2891/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2891/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -138,8 +138,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2892/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2892/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -160,8 +160,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2895/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2895/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -188,8 +188,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2912/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2912/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -108,8 +108,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s2912_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s2912_fam10/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -108,8 +108,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s4880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s4880/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -197,8 +197,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/tyan/s4882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/tyan/s4882/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -196,8 +196,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/via/epia-n/mptable.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/via/epia-n/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -66,8 +66,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x17); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/via/vt8454c/mptable.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/src/mainboard/via/vt8454c/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -55,8 +55,8 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/util/mptable/mptable.c ============================================================================== --- trunk/util/mptable/mptable.c Tue Oct 26 18:10:20 2010 (r5991) +++ trunk/util/mptable/mptable.c Wed Oct 27 00:40:16 2010 (r5992) @@ -1179,7 +1179,7 @@ printf( "\t %6d", (int)entry.dstApicID ); printf( "\t %3d\n", (int)entry.dstApicINT ); } - printf("\tsmp_write_intsrc(mc, %s, %s|%s, 0x%x, 0x%x, MP_APIC_ALL, 0x%x);\n", + printf("\tsmp_write_lintsrc(mc, %s, %s|%s, 0x%x, 0x%x, MP_APIC_ALL, 0x%x);\n", intTypes[ (int)entry.intType ], triggerMode[ ((int)entry.intFlags >> 2) & 0x03 ] , polarityMode[ (int)entry.intFlags & 0x03 ],

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[PATCH] Query cpu instead of using CONFIG_CPU_ADDR_BITS on AMD cpus
by Tobias Diedrich 26 Oct '10

26 Oct '10

This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the Linux kernel, which was previously complaining that the MTRR setup is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of address space. Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: src/cpu/amd/mtrr/amd_mtrr.c =================================================================== --- src/cpu/amd/mtrr/amd_mtrr.c (revision 5985) +++ src/cpu/amd/mtrr/amd_mtrr.c (working copy) @@ -1,5 +1,6 @@ #include <console/console.h> #include <device/device.h> +#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> @@ -175,11 +176,13 @@ enable_cache(); - /* FIXME we should probably query the cpu for this - * but so far this is all any recent AMD cpu has supported. - */ address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 + /* AMD specific MSR to query number of address bits */ + if (cpuid_eax(0x80000000) >= 0x80000008) { + address_bits = cpuid_eax(0x80000008) & 0xff; + } + /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. */

1 0

[commit] r5991 - in trunk/src: mainboard/asus/a8n_e mainboard/msi/ms7135 mainboard/sunw/ultra40 mainboard/tyan/s2891 mainboard/tyan/s2892 mainboard/tyan/s2895 southbridge/nvidia/ck804
by repository service 26 Oct '10

26 Oct '10

Author: jakllsch Date: Tue Oct 26 18:10:20 2010 New Revision: 5991 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5991 Log: Convert all ck804-based boards to tiny bootblock. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: trunk/src/southbridge/nvidia/ck804/bootblock.c Modified: trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/southbridge/nvidia/ck804/Kconfig Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Oct 26 18:10:20 2010 (r5991) @@ -79,7 +79,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -119,9 +118,6 @@ enumerate_ht_chain(); sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/mainboard/msi/ms7135/romstage.c Tue Oct 26 18:10:20 2010 (r5991) @@ -85,7 +85,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -126,9 +125,6 @@ enumerate_ht_chain(); sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } if (bist == 0) { Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Tue Oct 26 18:10:20 2010 (r5991) @@ -97,7 +97,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -147,9 +146,6 @@ enumerate_ht_chain(); sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } if (bist == 0) { Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/mainboard/tyan/s2891/romstage.c Tue Oct 26 18:10:20 2010 (r5991) @@ -69,7 +69,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -122,9 +121,6 @@ enumerate_ht_chain(); sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } if (bist == 0) { Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/mainboard/tyan/s2892/romstage.c Tue Oct 26 18:10:20 2010 (r5991) @@ -75,7 +75,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -116,9 +115,6 @@ enumerate_ht_chain(); sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } if (bist == 0) { Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/mainboard/tyan/s2895/romstage.c Tue Oct 26 18:10:20 2010 (r5991) @@ -89,7 +89,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -140,9 +139,6 @@ enumerate_ht_chain(); sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); } if (bist == 0) { Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 26 17:51:57 2010 (r5990) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Tue Oct 26 18:10:20 2010 (r5991) @@ -3,6 +3,11 @@ select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC + select TINY_BOOTBLOCK + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/nvidia/ck804/bootblock.c" if SOUTHBRIDGE_NVIDIA_CK804 config ID_SECTION_OFFSET hex Added: trunk/src/southbridge/nvidia/ck804/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/nvidia/ck804/bootblock.c Tue Oct 26 18:10:20 2010 (r5991) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Jonathan Kollasch <jakllsch(a)kollasch.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> + +#include "southbridge/nvidia/ck804/ck804_enable_rom.c" + +static void bootblock_southbridge_init(void) +{ + ck804_enable_rom(); +}

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[commit] r5990 - in trunk/src: mainboard/broadcom/blast mainboard/hp/dl145_g3 mainboard/hp/dl165_g6_fam10 mainboard/msi/ms9185 southbridge/broadcom/bcm5785
by repository service 26 Oct '10

26 Oct '10

Author: oxygene Date: Tue Oct 26 17:51:57 2010 New Revision: 5990 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5990 Log: Move bcm5785_enable_rom.c include to where it's used. Right now, it breaks the build of bootblock enabled boards with that chipset. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Tue Oct 26 17:11:45 2010 (r5989) +++ trunk/src/mainboard/broadcom/blast/romstage.c Tue Oct 26 17:51:57 2010 (r5990) @@ -17,6 +17,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Oct 26 17:11:45 2010 (r5989) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Oct 26 17:51:57 2010 (r5990) @@ -57,6 +57,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Oct 26 17:11:45 2010 (r5989) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Oct 26 17:51:57 2010 (r5990) @@ -49,6 +49,7 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Tue Oct 26 17:11:45 2010 (r5989) +++ trunk/src/mainboard/msi/ms9185/romstage.c Tue Oct 26 17:51:57 2010 (r5990) @@ -49,6 +49,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" +#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Tue Oct 26 17:11:45 2010 (r5989) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Tue Oct 26 17:51:57 2010 (r5990) @@ -20,7 +20,6 @@ #include <reset.h> #include "bcm5785.h" -#include "bcm5785_enable_rom.c" static void bcm5785_enable_lpc(void) {

1 0

[commit] r5989 - trunk/src/cpu/amd/model_10xxx
by repository service 26 Oct '10

26 Oct '10

Author: oxygene Date: Tue Oct 26 17:11:45 2010 New Revision: 5989 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5989 Log: reg is only used inside the #if clause, so declare it there. trivial. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Oct 26 07:26:01 2010 (r5988) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Oct 26 17:11:45 2010 (r5989) @@ -913,9 +913,9 @@ { u8 i; u8 nodes = get_nodes(); - u32 reg; #if CONFIG_RAMINIT_SYSINFO + u32 reg; /* read Node0 F0_0x64 bit [8:10] to find out SbLink # */ reg = pci_read_config32(NODE_HT(0), 0x64); sysinfo->sblk = (reg >> 8) & 7;

1 0

[PATCH] ASUS M2V support
by Tobias Diedrich 26 Oct '10

26 Oct '10

Add support for K8T890CF, VT8237A and ASUS M2V board. Needs crosschecking on VT8237R and VT8237S, since I had to touch some common codepaths like in src/southbridge/via/vt8237r/vt8237r_early_smbus.c Also because of the changed PCIe init code. Stupid issues that caused way too much (~1 day) headscratching until fixed: - I forgot to add the pci id in vt8237r_lpc.c: It was booting, but interrupts didn't work - I didn't have the 13.0 and 13.1 bridges in devicetree.cb: Linux saw the 13.0 bridge, but not the coreboot device scan. When enabling the 13.1 bridge, VGA init failed, since coreboot didn't see and initialize the bridge. Tested: - Linux boot (ACPI, APIC and LAPIC enabled) with acpi/mptables-enabled coreboot - HPET (detected and seems to work) - Serial port works - PCI slot irq routing works - PCIe slot irq routing works - MMCONFIG for extended pcie config space works - Booting from IDE HDD/CDROM works - Seabios won't boot from SATA, but both SATA controllers work in Linux - All 8 USB ports work FIXME: - PCIe doesn't get initialized on cold boot, only works when warm rebooting into Coreboot from Machine booted by AMI BIOS Someone with Datasheets needs to have a look I think - Onboard sound spews lots of "hda-intel: spurious response" messages and times out eventually. So for now we disable the bridge - VLINK settings works for me, but I don't have Datasheets Signed-Off-By: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- -- Tobias PGP: http://8ef7ddba.uguu.de

2 1

[commit] r5988 - trunk/src/southbridge/nvidia/mcp55
by repository service 26 Oct '10

26 Oct '10

Author: sduplichan Date: Tue Oct 26 07:26:01 2010 New Revision: 5988 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5988 Log: When gcc 4.5.0 is used, compiling mcp55_early_setup_car.c fails. This change eliminates the compiler warning that causes the build to fail. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Mon Oct 25 17:32:07 2010 (r5987) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Oct 26 07:26:01 2010 (r5988) @@ -363,9 +363,9 @@ static int mcp55_early_setup_x(void) { /*find out how many mcp55 we have */ - unsigned busn[HT_CHAIN_NUM_MAX]; - unsigned devn[HT_CHAIN_NUM_MAX]; - unsigned io_base[HT_CHAIN_NUM_MAX]; + unsigned busn[HT_CHAIN_NUM_MAX] = {0}; + unsigned devn[HT_CHAIN_NUM_MAX] = {0}; + unsigned io_base[HT_CHAIN_NUM_MAX] = {0}; /* FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation Need to use same trick about pci1234 to verify node/link connection

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coreboot October 2010