coreboot October 2010

coreboot@coreboot.org

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316 discussions

[PATCH] Remove incorrect IOAPIC lines from some mptable.c files
by Uwe Hermann 31 Oct '10

31 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r6006 - in trunk: src/mainboard/asus/p2b-d src/mainboard/intel/eagleheights src/mainboard/via/epia-n util/mptable
by repository service 31 Oct '10

31 Oct '10

Author: uwe Date: Sun Oct 31 20:37:50 2010 New Revision: 6006 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6006 Log: Remove incorrect IOAPIC lines from some mptable.c files. - via/epia-n/mptable.c - intel/eagleheights/mptable.c (commented out anyway) - asus/p2b-d/mptable.c - asus/p2b-ds/mptable.c Some files still incorrectly contain some smp_write_ioapic() lines from the original mptable utility target (Supermicro P4DPE), which has one IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total. However, none of the boards where this chunk of code is present has multiple IOAPICs (and even if they had, the PCI devices where those are located would probably be different anyway), so drop the incorrect mptable.c contents. Also drop the lines from the mptable utility, so that future mptable.c files don't incorrectly inherit any of this stuff. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Modified: trunk/src/mainboard/asus/p2b-d/mptable.c trunk/src/mainboard/intel/eagleheights/mptable.c trunk/src/mainboard/via/epia-n/mptable.c trunk/util/mptable/mptable.c Modified: trunk/src/mainboard/asus/p2b-d/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-d/mptable.c Sun Oct 31 15:17:51 2010 (r6005) +++ trunk/src/mainboard/asus/p2b-d/mptable.c Sun Oct 31 20:37:50 2010 (r6006) @@ -42,35 +42,6 @@ ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 3, ioapic_ver, res->base); - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 4, ioapic_ver, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 5, ioapic_ver, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 8, ioapic_ver, res->base); - } - } - /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); Modified: trunk/src/mainboard/intel/eagleheights/mptable.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mptable.c Sun Oct 31 15:17:51 2010 (r6005) +++ trunk/src/mainboard/intel/eagleheights/mptable.c Sun Oct 31 20:37:50 2010 (r6006) @@ -129,40 +129,7 @@ /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - /* - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 3, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 4, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 5, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - } - */ + mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ Modified: trunk/src/mainboard/via/epia-n/mptable.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mptable.c Sun Oct 31 15:17:51 2010 (r6005) +++ trunk/src/mainboard/via/epia-n/mptable.c Sun Oct 31 20:37:50 2010 (r6006) @@ -21,38 +21,7 @@ /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 3, 0x20, res->base); - } - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 4, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 5, 0x20, res->base); - } - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - } + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ Modified: trunk/util/mptable/mptable.c ============================================================================== --- trunk/util/mptable/mptable.c Sun Oct 31 15:17:51 2010 (r6005) +++ trunk/util/mptable/mptable.c Sun Oct 31 20:37:50 2010 (r6006) @@ -320,9 +320,7 @@ }; char *postamble[] = { -" /* There is no extension information... */", -"", -" /* Compute the checksums */", +" /* Compute the checksums. */", " mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);", " mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);", " printk(BIOS_DEBUG, \"Wrote the mp table end at: %p - %p\\n\",", @@ -341,38 +339,7 @@ char *ioapic_code[] = { " smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);", -" {", -" device_t dev;", -" struct resource *res;", -" dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 3, 0x20, res->base);", -" }", -" }", -" dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 4, 0x20, res->base);", -" }", -" }", -" dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 5, 0x20, res->base);", -" }", -" }", -" dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));", -" if (dev) {", -" res = find_resource(dev, PCI_BASE_ADDRESS_0);", -" if (res) {", -" smp_write_ioapic(mc, 8, 0x20, res->base);", -" }", -" }", -" }", +" /* TODO: If you have multiple IOAPICs, add them here. */", 0 }; static void

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[PATCH] Various PIRQ/MPTABLE/ACPI Kconfig fixes
by Uwe Hermann 31 Oct '10

31 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

1 0

FOSDEM devroom request
by Rudolf Marek 31 Oct '10

31 Oct '10

Hi all, I have written following to the devroom request. Thanks. Rudolf Hello, We would like to ask for common devroom for both collaborating projects - Coreboot and Flashrom. Coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) you can find in most of today's computers. Flashrom is a utility for identifying, reading, writing, verifying and erasing flash chips. It is designed to flash BIOS/EFI/coreboot/firmware/optionROM images on mainboards, network/graphics/storage controller cards, and various programmer devices. Both projects are closely related, for example, the Coreboot uses Flashrom to write the images. Both attract people which like the hardware and close to the hardware system programming. On the last FOSDEM there was a Coreboot devroom. Flashrom presented itself only during Carl Daniel's lightning talk. This year is a great opportunity for both projects to share a common devroom to attract hardware oriented people together. As for the devroom topic, we would like to offer more hands-on sessions and kind of mini lectures explaining various parts of non-trivial problematics which both project face. If one judges the last year Coreboot devroom attendance, we had all the time full room, which was nice although we prepared "just" lectures about the project (with demo) and "how stuff works" oriented lectures. Our aim for this year is to bring both projects even closer to potential users or developers using above mentioned more individual approach. We would also like to apply for the main talk track to catch an attention of completely new users or developers which never heard of our projects. The intended topic of the talk would be more general and serve as the introduction to this interesting part of computer hardware & software.

2 5

usb2 support in Filo / coreboot
by Mark Field 31 Oct '10

31 Oct '10

hello, I have been reading about coreboot to see if it can solve a small problem I have. I have an Via EPIA-ML8000AG and would like to boot linux from a usb pendrive, this works, but is very slow, which I believe is down to the fact that although the board has a usb2 controller the bios only supports usb1 >From reading coreboot.org I think my board is supported and I could use Filo as a payload to boot linux from usb, but I can't see any reference to whether this would be at usb1 or usb2 speeds. would anyone be able to comment? Thanks Mark

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[commit] r6005 - trunk/src/cpu/amd/model_10xxx
by repository service 31 Oct '10

31 Oct '10

Author: sduplichan Date: Sun Oct 31 15:17:51 2010 New Revision: 6005 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6005 Log: Fix AMD family 10h engineering sample is reported as 'thermal test kit'. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/cpu/amd/model_10xxx/processor_name.c Modified: trunk/src/cpu/amd/model_10xxx/processor_name.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/processor_name.c Sat Oct 30 23:27:13 2010 (r6004) +++ trunk/src/cpu/amd/model_10xxx/processor_name.c Sun Oct 31 15:17:51 2010 (r6005) @@ -204,7 +204,7 @@ memset(program_string, 0, sizeof(program_string)); if (!Model) { - processor_name_string = Pg ? sample : thermal; + processor_name_string = Pg ? thermal : sample; goto done; }

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printall target
by ali hagigat 31 Oct '10

31 Oct '10

My question is about the main makefile of Coreboot and the rule 'printall'. I wonder if anybody can write a 'sed' or 'awk' command or any other shell command to print the result of 'objs' , 'initobjs' , 'drivers' .....on separate lines(each pathname is printed on a separate line and then there is a new line at the end of each line, second pathname of a file is written on the second line and continues...) Now spaces are separating the strings, make them difficult to read.

2 1

how to prevent legacy resource conflict with multiple VGA cards
by Scott Duplichan 31 Oct '10

31 Oct '10

Hello, I have Win7 working well with mahogany_fam10 if I use a PCI video card. However, Device manager complains that it is unable to find enough free resources for the UMA graphics controller. Running an AMI legacy BIOS shows the problem can be solved by enabling the PCI command register memory and I/O enable bits for only the graphics card that you are using. Is there a way to make coreboot do this, and if not, any suggestions on where best to implement such a feature? Thanks, Scott

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[PATCH] Mptable related fixes for ASUS P2B-DS
by Uwe Hermann 30 Oct '10

30 Oct '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r6004 - trunk/src/mainboard/asus/p2b-ds
by repository service 30 Oct '10

30 Oct '10

Author: uwe Date: Sat Oct 30 23:27:13 2010 New Revision: 6004 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6004 Log: Mptable related fixes for ASUS P2B-DS. - Add "select IOAPIC" in the board's Kconfig file. - Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already). - Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c, that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC are set. - Rework ASUS P2B-DS mptable.c to fix a number of things: - Convert it to use mptable_write_buses() as all mptable.c files should do. - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC). - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig trunk/src/mainboard/asus/p2b-ds/devicetree.cb trunk/src/mainboard/asus/p2b-ds/mptable.c trunk/src/mainboard/asus/p2b-ds/romstage.c Modified: trunk/src/mainboard/asus/p2b-ds/Kconfig ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/Kconfig Fri Oct 29 22:40:06 2010 (r6003) +++ trunk/src/mainboard/asus/p2b-ds/Kconfig Sat Oct 30 23:27:13 2010 (r6004) @@ -28,6 +28,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP + select IOAPIC select UDELAY_TSC select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM @@ -48,4 +49,8 @@ int default 2 +config MAX_PHYSICAL_CPUS + int + default 2 + endif # BOARD_ASUS_P2B_DS Modified: trunk/src/mainboard/asus/p2b-ds/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/devicetree.cb Fri Oct 29 22:40:06 2010 (r6003) +++ trunk/src/mainboard/asus/p2b-ds/devicetree.cb Sat Oct 30 23:27:13 2010 (r6004) @@ -1,10 +1,10 @@ chip northbridge/intel/i440bx # Northbridge - device lapic_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/intel/slot_1 # CPU socket 0 + device lapic 0 on end # Local APIC of CPU 0 end - chip cpu/intel/slot_1 # CPU - device lapic 1 on end # APIC + chip cpu/intel/slot_1 # CPU socket 1 + device lapic 1 on end # Local APIC of CPU 1 end end device pci_domain 0 on # PCI domain Modified: trunk/src/mainboard/asus/p2b-ds/mptable.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/mptable.c Fri Oct 29 22:40:06 2010 (r6003) +++ trunk/src/mainboard/asus/p2b-ds/mptable.c Sat Oct 30 23:27:13 2010 (r6004) @@ -27,6 +27,7 @@ static void *smp_write_config_table(void *v) { + int ioapic_id, ioapic_ver, isa_bus; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -35,61 +36,24 @@ smp_write_processors(mc); - /* Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "ISA "); - - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - - dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 3, 0x20, res->base); - } - dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 4, 0x20, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 5, 0x20, res->base); - } - dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) - smp_write_ioapic(mc, 8, 0x20, res->base); - } - } - - mptable_add_isa_interrupts(mc, 0x1, 0x2, 0); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0x0, 0x13, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0x0, 0x18, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, - 0x0, 0x30, 0x2, 0x10); - - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_lintsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, - MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x1, 0x0, MP_APIC_ALL, 0x1); + mptable_write_buses(mc, NULL, &isa_bus); - /* There is no extension information... */ + ioapic_id = 2; + ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); - /* Compute the checksums */ + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); + + /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); + + /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1); + + /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); Modified: trunk/src/mainboard/asus/p2b-ds/romstage.c ============================================================================== --- trunk/src/mainboard/asus/p2b-ds/romstage.c Fri Oct 29 22:40:06 2010 (r6003) +++ trunk/src/mainboard/asus/p2b-ds/romstage.c Sat Oct 30 23:27:13 2010 (r6004) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include "southbridge/intel/i82371eb/i82371eb.h" #include "northbridge/intel/i440bx/raminit.h" @@ -47,8 +46,6 @@ void main(unsigned long bist) { - enable_lapic(); /* FIXME? */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();

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coreboot October 2010