coreboot October 2010

coreboot@coreboot.org

55 participants
316 discussions

build questions
by Flemming Richter Mikkelsen 05 Nov '10

05 Nov '10

Hello. Today I tried to build coreboot for the very first time. I discovered that the debug configs caused some harmless warnings of the type "referenced but not used". Also, I tried scan-build. I never tried this before, and therefore I don't know it limitations. A make generated a list of 60 bugs. Not all of them are real bugs though. It looks like it found that we use math operation on a uninitialized value: File: northbridge/amd/amdfam10/../amdmct/mct/mctndi_d.c Location: line 98, column 6 Description: The left expression of the compound assignment is an uninitialized value. The computed value will also be garbage DctSelBaseOffset -= Base; Anyway, the computed value is never used. Would it make sense to remove unused variables? If so, I can try to create a few patches. I think scan-build is almost useless when it generate a list of 60 "bugs".

2 1

[patch] fix unexpacted MTRR setup for UMA memory
by Scott Duplichan 05 Nov '10

05 Nov '10

Hello, I find an unexpected MTRR setup for my RS780/SB700 UMA board. With a single 1GB DIMM and 256MB UMA size, the variable MTRRs look like this: -----coreboot+seabios----- default memory type: UC variable range 0: 000000000-03FFFFFFF WB variable range 1: 040000000-04FFFFFFF WB variable range 2: 030000000-03FFFFFFF UC variable range 3: disabled variable range 4: disabled variable range 5: disabled variable range 6: disabled variable range 7: disabled Variable range 1 is unexpected. It creates a window of WB-IO, which is highly unusual. -----Production BIOS (AMI):----- default memory type: UC variable range 0: 000000000-01FFFFFFF WB variable range 1: 020000000-02FFFFFFF WB variable range 2: disabled variable range 3: disabled variable range 4: disabled variable range 5: disabled variable range 6: disabled variable range 7: disabled The above is how uma is normally handled. Build up WB ranges until the needed size is reached. -----[patched] coreboot+seabios----- default memory type: UC variable range 0: 000000000-01FFFFFFF WB variable range 1: 020000000-02FFFFFFF WB variable range 2: disabled variable range 3: disabled variable range 4: disabled variable range 5: disabled variable range 6: disabled variable range 7: disabled With the patch, coreboot matches the production BIOS. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 5978) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -423,11 +423,8 @@ if (var_state.hole_startk || var_state.hole_sizek) { printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); } else { - // Increase the base range and set up UMA as an UC hole instead - var_state.range_sizek += (uma_memory_size >> 10); - - var_state.hole_startk = (uma_memory_base >> 10); - var_state.hole_sizek = (uma_memory_size >> 10); + // Reduce the dram wb mtrr range so that it does not cover the uma at the end + var_state.range_sizek -= (uma_memory_size >> 10); } #endif /* Write the last range */

4 7

[PATCH 0/7] ASUS M2V support (v2)
by Tobias Diedrich 03 Nov '10

03 Nov '10

An update to this patch series: I found the gpio that was keeping the pcie slots in reset. Azalia HDAC is also working now. Remaining problems: - While my ati pcie graphics card works in the peg slot, a network card (x1 link) doesn't, but with the asus bios both work. - ACPI still giving stop 0xa5 (next debugging target) -- Tobias PGP: http://8ef7ddba.uguu.de

4 26

Re: [coreboot] [PATCH] Geode GX2 auto DRAM detect patch
by Nils 01 Nov '10

01 Nov '10

***Ping*** It would be nice if someone finds the time to ack/commit or comment my patch. On 10/7/10 , Nils wrote: >This patch brings the adapted Geode LX auto DRAM detect code to GX2 , >cleans up some files and adds a processor speed setting function in human >readable Mhz. > >Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils

5 14

[PATCH 4/4] Geode GX2 auto DRAM detect patch V2
by Nils 01 Nov '10

01 Nov '10

This patch changes Geode GX2 to use the auto DRAM detect code from Geode LX and changes the boards to use it. It also adds a processor speed setting function in human readable Mhz and removes the useless and broken PLLMSR settings. (the processor speed was hardcoded to 366Mhz in pll_reset.c) Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

[PATCH 3/4] Geode GX2 auto DRAM detect patch V2
by Nils 01 Nov '10

01 Nov '10

This patch removes some unused code. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl>

2 1

[PATCH 2/4] Geode GX2 auto DRAM detect patch V2
by Nils 01 Nov '10

01 Nov '10

This patch cleans up some white space and comments. It also adds a copyright header to pll_reset.c . Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils.

2 1

[PATCH 1/4] Geode GX2 auto DRAM detect patch V2
by Nils 01 Nov '10

01 Nov '10

This patch changes the MSR register numbers in to more descriptive names. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks, Nils

2 1

[commit] r6007 - in trunk/src/mainboard: amd/mahogany_fam10 amd/tilapia_fam10 asus/m4a785-m gigabyte/ma785gmt gigabyte/ma78gm iei/kino-780am2-fam10 jetway/pa78vm5
by repository service 01 Nov '10

01 Nov '10

Author: uwe Date: Mon Nov 1 00:24:18 2010 New Revision: 6007 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6007 Log: Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig trunk/src/mainboard/amd/tilapia_fam10/Kconfig trunk/src/mainboard/asus/m4a785-m/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/Kconfig trunk/src/mainboard/gigabyte/ma78gm/Kconfig trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig trunk/src/mainboard/jetway/pa78vm5/Kconfig Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -81,10 +81,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 Modified: trunk/src/mainboard/amd/tilapia_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/amd/tilapia_fam10/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -81,10 +81,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 Modified: trunk/src/mainboard/asus/m4a785-m/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/asus/m4a785-m/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -80,10 +80,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x83a2 Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -81,10 +81,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -81,10 +81,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060 Modified: trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/iei/kino-780am2-fam10/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -81,10 +81,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x0000 Modified: trunk/src/mainboard/jetway/pa78vm5/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/Kconfig Sun Oct 31 20:37:50 2010 (r6006) +++ trunk/src/mainboard/jetway/pa78vm5/Kconfig Mon Nov 1 00:24:18 2010 (r6007) @@ -81,10 +81,6 @@ hex default 0xc0000 -config ACPI_SSDTX_NUM - int - default 0 - config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x3060

1 0

[PATCH 0/4] Geode GX2 auto DRAM detect patch V2
by Nils 31 Oct '10

31 Oct '10

This patch series splits up the Geode GX2 auto DRAM detect patch into 4 patches as requested. It should be easy to review now. The patches are Abuild and boot tested on my Wyse S50 . They should be applied in this order. Thanks, Nils.

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coreboot October 2010