coreboot January 2010

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[commit] r5026 - in trunk/src/southbridge/intel/i82801gx: . acpi
by svn＠coreboot.org 17 Jan '10

17 Jan '10

Author: stepan Date: 2010-01-17 14:49:07 +0100 (Sun, 17 Jan 2010) New Revision: 5026 Modified: trunk/src/southbridge/intel/i82801gx/acpi/sleepstates.asl trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c Log: ICH7 update * change the code to use macros names instead of constants in many places * SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x) * SMI: Add support for mainboard GPI handler * SMI: immediate power-off on power button press, if OSPM is not active * Add fix for some USB errata * Some register tweaks for mobile systems * Enable configure SCI on interrupt 9 correctly. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/intel/i82801gx/acpi/sleepstates.asl =================================================================== --- trunk/src/southbridge/intel/i82801gx/acpi/sleepstates.asl 2010-01-17 13:47:35 UTC (rev 5025) +++ trunk/src/southbridge/intel/i82801gx/acpi/sleepstates.asl 2010-01-17 13:49:07 UTC (rev 5026) @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -Name(\_S0, Package(){0x0,0x0,0,0}) -Name(\_S1, Package(){0x1,0x0,0,0}) -Name(\_S3, Package(){0x5,0x0,0,0}) -Name(\_S4, Package(){0x6,0x0,0,0}) -Name(\_S5, Package(){0x7,0x0,0,0}) +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h 2010-01-17 13:47:35 UTC (rev 5025) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h 2010-01-17 13:49:07 UTC (rev 5026) @@ -32,6 +32,8 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 + +#define IO_APIC_ADDR 0xfec00000 #define HPET_ADDR 0xfed00000 #define DEFAULT_RCBA 0xfed1c000 @@ -276,7 +278,20 @@ /* ICH7 PMBASE */ #define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 #define SLP_EN (1 << 13) #define SLP_TYP (7 << 10) @@ -290,8 +305,24 @@ #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 +#define USB4_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c #define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2010-01-17 13:47:35 UTC (rev 5025) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_lpc.c 2010-01-17 13:49:07 UTC (rev 5026) @@ -40,8 +40,8 @@ { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; - volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Enable ACPI I/O and power management. * Set SCI IRQ to IRQ9 @@ -175,7 +175,7 @@ u8 reg8; u16 reg16, pmbase; u32 reg32; - char *state; + const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -238,9 +238,13 @@ /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - reg16 |= (1 << 2); // CLKRUN_EN + reg16 &= ~(3 << 0); // SMI# rate 1 minute + reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only + reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only + reg16 |= (1 << 5); // CPUSLP_EN Desktop only + // another laptop wants this? + // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only + reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using * periodic SMIs. @@ -259,15 +263,10 @@ /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT -#if 0 -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0; - printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n", - reg32, acpi_slp_type); -#endif -#endif - reg32 |= (1 << 1); // enable C3->C0 transition on bus master - reg32 |= 1; // SCI_EN + + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 1); // enable C3->C0 transition on bus master + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); } @@ -308,10 +307,10 @@ u32 reg32; /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(0x3404); + reg32 = RCBA32(HPTC); reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); - RCBA32(0x3404) = reg32; + RCBA32(HPTC) = reg32; } static void enable_clock_gating(void) @@ -319,16 +318,18 @@ u32 reg32; /* Enable Clock Gating for most devices */ - reg32 = RCBA32(0x341c); + reg32 = RCBA32(CG); reg32 |= (1 << 31); // LPC clock gating reg32 |= (1 << 30); // PATA clock gating // SATA clock gating reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 23); // AC97 clock gating - reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating + reg32 |= (1 << 19); // USB EHCI clock gating reg32 |= (1 << 3) | (1 << 1); // DMI clock gating reg32 |= (1 << 2); // PCIe clock gating; - RCBA32(0x341c) = reg32; + reg32 &= ~(1 << 20); // No static clock gating for USB + reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating + RCBA32(CG) = reg32; } #if CONFIG_HAVE_SMI_HANDLER @@ -392,10 +393,16 @@ RCBA16(SPIBASE + 2) = spicontrol; } -static void i82801gx_fixups(void) +static void i82801gx_fixups(struct device *dev) { /* This needs to happen after PCI enumeration */ RCBA32(0x1d40) |= 1; + + /* USB Transient Disconnect Detect: + * Prevent a SE0 condition on the USB ports from being + * interpreted by the UHCI controller as a disconnect + */ + pci_write_config8(dev, 0xad, 0x3); } static void lpc_init(struct device *dev) @@ -437,7 +444,8 @@ setup_i8259(); /* The OS should do this? */ - // i8259_configure_irq_trigger(9, 1); + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); #if CONFIG_HAVE_SMI_HANDLER i82801gx_lock_smm(dev); @@ -445,7 +453,7 @@ i82801gx_spi_init(); - i82801gx_fixups(); + i82801gx_fixups(dev); } static void i82801gx_lpc_read_resources(device_t dev) Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c 2010-01-17 13:47:35 UTC (rev 5025) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smi.c 2010-01-17 13:49:07 UTC (rev 5026) @@ -155,7 +155,35 @@ printk_debug("\n"); } + /** + * @brief read and clear ALT_GP_SMI_STS + * @return ALT_GP_SMI_STS register + */ +static u16 reset_alt_gp_smi_status(void) +{ + u16 reg16; + + reg16 = inl(pmbase + ALT_GP_SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg16, pmbase + ALT_GP_SMI_STS); + + return reg16; +} + +static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) +{ + int i; + printk_debug("ALT_GP_SMI_STS: "); + for (i=15; i<= 0; i--) { + if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16)); + } + printk_debug("\n"); +} + + + +/** * @brief read and clear TCOx_STS * @return TCOx_STS registers */ @@ -212,6 +240,7 @@ void smm_relocate(void) { u32 smi_en; + u16 pm1_en; printk_debug("Initializing SMM handler..."); @@ -232,6 +261,7 @@ dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); + dump_alt_gp_smi_status(reset_alt_gp_smi_status()); dump_tco_status(reset_tco_status()); /* Enable SMI generation: @@ -244,6 +274,10 @@ */ smi_en = 0; /* reset SMI enables */ + +#if 0 + smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; +#endif smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS @@ -260,6 +294,11 @@ outl(smi_en, pmbase + SMI_EN); + pm1_en = 0; + pm1_en |= PWRBTN_EN; + pm1_en |= GBL_EN; + outw(pm1_en, pmbase + PM1_EN); + /** * There are several methods of raising a controlled SMI# via * software, among them: Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2010-01-17 13:47:35 UTC (rev 5025) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_smihandler.c 2010-01-17 13:49:07 UTC (rev 5026) @@ -25,14 +25,15 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#include <device/pci_def.h> #include "i82801gx.h" #include "i82801gx_power.h" #define DEBUG_SMI #define APM_CNT 0xb2 -#define CST_CONTROL 0x85 // 0x85 crashes the box -#define PST_CONTROL 0x80 // 0x80 crashes the box +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 #define ACPI_DISABLE 0x1e #define ACPI_ENABLE 0xe1 #define GNVS_UPDATE 0xea @@ -88,6 +89,8 @@ if (pm1_sts & (1 << 4)) printk_spew("BM "); if (pm1_sts & (1 << 0)) printk_spew("TMROF "); printk_spew("\n"); + int reg16 = inw(pmbase + PM1_EN); + printk_spew("PM1_EN: %x\n", reg16); } /** @@ -245,7 +248,42 @@ outb(reg8, pmbase + SMI_EN); } +static void busmaster_disable_on_bus(int bus) +{ + int slot, func; + unsigned int val; + unsigned char hdr; + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } +} + + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8; @@ -281,12 +319,9 @@ case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break; case 7: printk_debug("SMI#: Entering S5 (Soft Power off)\n"); -#if 0 - /* Set PME_B0_EN before going to S5 */ - reg32 = inl(pmbase + GPE0_EN); - reg32 |= PME_B0_EN; - outl(reg32, pmbase + GPE0_EN); -#endif + + outl(0, pmbase + GPE0_EN); + /* Should we keep the power state after a power loss? * In case the setting is "ON" or "OFF" we don't have * to do anything. But if it's "KEEP" we have to switch @@ -297,6 +332,9 @@ reg8 |= 1; pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); } + + /* also iterates over all bridges on bus 0 */ + busmaster_disable_on_bus(0); break; default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break; } @@ -376,6 +414,16 @@ pm1_sts = reset_pm1_status(); dump_pm1_status(pm1_sts); + + /* While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + // power button pressed + u32 reg32; + reg32 = (7 << 10) | (1 << 13); + outl(reg32, pmbase + PM1_CNT); + } } static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) @@ -386,6 +434,8 @@ dump_gpe0_status(gpe0_sts); } +void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); + static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) { u16 reg16; @@ -393,8 +443,13 @@ outl(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (reg16) - printk_debug("GPI (mask %04x)\n",reg16); + + if (mainboard_smi_gpi) { + mainboard_smi_gpi(reg16); + } else { + if (reg16) + printk_debug("GPI (mask %04x)\n",reg16); + } } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) Modified: trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c =================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c 2010-01-17 13:47:35 UTC (rev 5025) +++ trunk/src/southbridge/intel/i82801gx/i82801gx_usb.c 2010-01-17 13:49:07 UTC (rev 5026) @@ -35,6 +35,10 @@ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + // Erratum + pci_write_config8(dev, 0xca, 0x00); + + // Yes. Another Erratum reg8 = pci_read_config8(dev, 0xca); reg8 |= (1 << 0); pci_write_config8(dev, 0xca, reg8);

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[commit] r5025 - trunk/src/northbridge/intel/i945
by svn＠coreboot.org 17 Jan '10

17 Jan '10

Author: stepan Date: 2010-01-17 14:47:35 +0100 (Sun, 17 Jan 2010) New Revision: 5025 Modified: trunk/src/northbridge/intel/i945/early_init.c trunk/src/northbridge/intel/i945/raminit.c Log: Support a few more i945 variants. With this framework in place it should be possible to support i955 and i975 relatively easy, too. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/northbridge/intel/i945/early_init.c =================================================================== --- trunk/src/northbridge/intel/i945/early_init.c 2010-01-16 18:39:35 UTC (rev 5024) +++ trunk/src/northbridge/intel/i945/early_init.c 2010-01-17 13:47:35 UTC (rev 5025) @@ -92,22 +92,29 @@ u8 reg8; printk_info("\nIntel(R) "); - reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0x8); + + reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); switch (reg8) { case 0: case 1: printk_info("82945G"); break; case 2: - printk_info("82945G/GZ/GC"); + case 3: + printk_info("82945P"); break; - case 0x80: - case 0x81: - case 0x82: - printk_info("82945P/PL"); + case 4: + printk_info("82945GC"); break; + case 5: + printk_info("82945GZ"); + break; + case 6: + case 7: + printk_info("82945PL"); + break; default: - printk_info("Unknown (%02x)", reg8); /* Others unknown. */ + break; } printk_info(" Chipset\n"); @@ -794,32 +801,26 @@ reg32 |= (1 << 16); EPBAR32(EPESD) = reg32; - EPBAR32(EPLE1D) |= (1 << 16); + EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); - EPBAR32(EPLE1D) |= (1 << 0); - EPBAR32(EPLE1A) = DEFAULT_DMIBAR; -#if 0 - EPBAR32(EPLE2D) |= (1 << 16); -#endif - EPBAR32(EPLE2D) |= (1 << 0); + EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); /* DMI Port Root Topology */ + reg32 = DMIBAR32(DMILE1D); reg32 &= 0x00ffffff; - DMIBAR32(DMILE1D) = reg32; - reg32 = DMIBAR32(DMILE1D); reg32 &= 0xff00ffff; reg32 |= (2 << 16); + + reg32 |= (1 << 0); DMIBAR32(DMILE1D) = reg32; - DMIBAR32(DMILE1D) |= (1 << 0); - DMIBAR32(DMILE1A) = DEFAULT_RCBA; - DMIBAR32(DMILE2D) |= (1 << 0); + DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); DMIBAR32(DMILE2A) = DEFAULT_EPBAR; Modified: trunk/src/northbridge/intel/i945/raminit.c =================================================================== --- trunk/src/northbridge/intel/i945/raminit.c 2010-01-16 18:39:35 UTC (rev 5024) +++ trunk/src/northbridge/intel/i945/raminit.c 2010-01-17 13:47:35 UTC (rev 5025) @@ -87,6 +87,46 @@ } #endif +static int memclk(void) +{ + int offset = 0; +#ifdef CHIPSET_I945GM + offset++; +#endif + switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { + case 1: return 400; + case 2: return 533; + case 3: return 667; + default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset); + } + return -1; +} + +#ifdef CHIPSET_I945GM +static int fsbclk(void) +{ + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 400; + case 1: return 533; + case 3: return 667; + default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); + } + return -1; +} +#endif +#ifdef CHIPSET_I945GC +static int fsbclk(void) +{ + switch (MCHBAR32(CLKCFG) & 7) { + case 0: return 1066; + case 1: return 533; + case 2: return 800; + default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); + } + return -1; +} +#endif + static int sdram_capabilities_max_supported_memory_frequency(void) { u32 reg32; @@ -434,6 +474,9 @@ case 667: max_ram_speed = 2; break; } + if (fsbclk() == 533) + max_ram_speed = 1; + sysinfo->memory_frequency = 0; sysinfo->cas = 0; @@ -827,184 +870,274 @@ MCHBAR32(offset+(i*4)) = slew_rate_table[i]; } -static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) -{ - static const u32 dq2030[] = { - 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, - 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, - 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, - 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 - }; +static const u32 dq2030[] = { + 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, + 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, + 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, + 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 +}; - static const u32 dq2330[] = { - 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, - 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, - 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, - 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 - }; +static const u32 dq2330[] = { + 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, + 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, + 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, + 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 +}; - static const u32 cmd2710[] = { - 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, - 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, - 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, - 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f - }; +static const u32 cmd2710[] = { + 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, + 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f +}; - static const u32 cmd3210[] = { - 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f, - 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, - 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f, - 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f - }; +static const u32 cmd3210[] = { + 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, + 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f, + 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f +}; - static const u32 clk2030[] = { - 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211, - 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c, - 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120, - 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937 - }; +static const u32 clk2030[] = { + 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211, + 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c, + 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120, + 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937 +}; - static const u32 ctl3215[] = { - 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908, - 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19, - 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b, - 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d - }; +static const u32 ctl3215[] = { + 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908, + 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19, + 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b, + 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d +}; - static const u32 ctl3220[] = { - 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411, - 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e, - 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311, - 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e - }; +static const u32 ctl3220[] = { + 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411, + 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e, + 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311, + 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e +}; - static const u32 nc[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000 - }; +static const u32 nc[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; - static const u32 const * const dual_channel_slew_group_lookup[] = { - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd3210, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710, - dq2030, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, +enum { + DQ2030, + DQ2330, + CMD2710, + CMD3210, + CLK2030, + CTL3215, + CTL3220, + NC, +}; - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, nc, clk2030, nc, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, nc, clk2030, nc, dq2030, cmd2710, - dq2030, cmd3210, ctl3215, nc, clk2030, nc, nc, nc, +static const u8 dual_channel_slew_group_lookup[] = { + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, - dq2030, cmd3210, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd3210, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710, - dq2030, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, + DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, - dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd2710, ctl3215, nc, clk2030, nc, dq2030, cmd3210, - dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210, - dq2030, cmd2710, ctl3215, nc, clk2030, nc, dq2030, cmd2710, - dq2030, cmd2710, ctl3215, nc, clk2030, nc, nc, nc, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, - nc, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - nc, nc, ctl3215, nc, clk2030, nc, dq2030, cmd3210, - nc, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - nc, nc, ctl3215, nc, clk2030, clk2030, dq2030, cmd2710 - }; + DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, + DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, + DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, NC, NC, - static const u32 const * const single_channel_slew_group_lookup[] = { - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, nc, ctl3215, nc, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + NC, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + NC, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD2710 +}; - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, nc, clk2030, nc, nc, nc, +static const u8 single_channel_slew_group_lookup[] = { + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, - dq2330, cmd3210, nc, ctl3215, nc, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, nc, ctl3215, nc, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, nc, ctl3215, nc, clk2030, nc, nc, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, nc, clk2030, nc, dq2330, cmd3210, - dq2330, cmd3210, ctl3215, nc, clk2030, nc, nc, nc, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, - dq2330, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - dq2330, nc, ctl3215, nc, clk2030, nc, dq2030, cmd3210, - dq2330, nc, nc, ctl3215, nc, clk2030, dq2030, cmd3210, - dq2330, nc, ctl3215, nc, clk2030, clk2030, dq2030, cmd3210 - }; + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, - /* Strength multiplier tables */ - static const u8 dual_channel_strength_multiplier[] = { - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, - 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, - 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, - 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, - 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, - 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 - }; + DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2330, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 +}; - static const u8 single_channel_strength_multiplier[] = { - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, - 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, - 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, - 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 - }; +static const u32 *slew_group_lookup(int dual_channel, int index) +{ + const u8 *slew_group; + /* Dual Channel needs different tables. */ + if (dual_channel) + slew_group = dual_channel_slew_group_lookup; + else + slew_group = single_channel_slew_group_lookup; + switch (slew_group[index]) { + case DQ2030: return dq2030; + case DQ2330: return dq2330; + case CMD2710: return cmd2710; + case CMD3210: return cmd3210; + case CLK2030: return clk2030; + case CTL3215: return ctl3215; + case CTL3220: return ctl3220; + case NC: return nc; + } + + return nc; +} + +#ifdef CHIPSET_I945GM +/* Strength multiplier tables */ +static const u8 dual_channel_strength_multiplier[] = { + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, + 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, + 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, + 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, + 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, + 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, + 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 +}; + +static const u8 single_channel_strength_multiplier[] = { + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, + 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, + 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 +}; +#endif +#ifdef CHIPSET_I945GC +static const u8 dual_channel_strength_multiplier[] = { + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, + 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33 +}; + +static const u8 single_channel_strength_multiplier[] = { + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, + 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 +}; +#endif + +static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) +{ const u8 * strength_multiplier; - const u32* const * slew_group_lookup; - int idx; + int idx, dual_channel; /* Set Strength Multipliers */ @@ -1012,12 +1145,12 @@ if (sdram_capabilities_dual_channel()) { printk_debug("Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; - slew_group_lookup = dual_channel_slew_group_lookup; + dual_channel = 1; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk_debug("Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; - slew_group_lookup = single_channel_slew_group_lookup; + dual_channel = 0; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; } @@ -1033,22 +1166,22 @@ MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7]; /* Channel 0 */ - sdram_write_slew_rates(G1SRPUT, slew_group_lookup[idx * 8 + 0]); - sdram_write_slew_rates(G2SRPUT, slew_group_lookup[idx * 8 + 1]); - if ((slew_group_lookup[idx * 8 + 2] != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) { + sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0)); + sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1)); + if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) { sdram_write_slew_rates(G3SRPUT, ctl3220); } else { - sdram_write_slew_rates(G3SRPUT, slew_group_lookup[idx * 8 + 2]); + sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2)); } - sdram_write_slew_rates(G4SRPUT, slew_group_lookup[idx * 8 + 3]); - sdram_write_slew_rates(G5SRPUT, slew_group_lookup[idx * 8 + 4]); - sdram_write_slew_rates(G6SRPUT, slew_group_lookup[idx * 8 + 5]); + sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3)); + sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4)); + sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5)); /* Channel 1 */ if (sysinfo->dual_channel) { - sdram_write_slew_rates(G7SRPUT, slew_group_lookup[idx * 8 + 6]); - sdram_write_slew_rates(G8SRPUT, slew_group_lookup[idx * 8 + 7]); + sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6)); + sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7)); } else { sdram_write_slew_rates(G7SRPUT, nc); sdram_write_slew_rates(G8SRPUT, nc); @@ -1110,6 +1243,7 @@ reg8 = i945_silicon_revision(); if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) { + reg32 = MCHBAR32(GBRCOMPCTL); reg32 |= (3 << 5); MCHBAR32(GBRCOMPCTL) = reg32; @@ -1352,10 +1486,12 @@ if (sysinfo->interleaved) cum1 = 0; +#if 0 /* Exception: Channel 1 is not populated. C1DRB stays zero */ if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED && sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) cum1 = 0; +#endif for(i = 0; i < 2 * DIMM_SOCKETS; i++) { cum1 += sysinfo->banksize[i + 4]; @@ -1770,12 +1906,9 @@ MCHBAR32(PLLMON) = 0x80800000; - switch (MCHBAR32(CLKCFG) & 0x7) { - case 0: sysinfo->fsb_frequency = 400; break; /* FSB400 */ - case 1: sysinfo->fsb_frequency = 533; break; /* FSB533 */ - case 3: sysinfo->fsb_frequency = 667; break; /* FSB667 */ - default: die("Unsupported FSB speed"); - } + sysinfo->fsb_frequency = fsbclk(); + if (sysinfo->fsb_frequency == -1) + die("Unsupported FSB speed"); /* Program CPCTL according to FSB speed */ /* Only write the lower byte */ @@ -1918,6 +2051,10 @@ { u32 clkcfg; u8 reg8; + u8 offset = 0; +#ifdef CHIPSET_I945GM + offset++; +#endif printk_debug ("Setting Memory Frequency... "); @@ -1939,9 +2076,9 @@ } switch (sysinfo->memory_frequency) { - case 400: clkcfg |= (2 << 4); break; - case 533: clkcfg |= (3 << 4); break; - case 667: clkcfg |= (4 << 4); break; + case 400: clkcfg |= ((1+offset) << 4); break; + case 533: clkcfg |= ((2+offset) << 4); break; + case 667: clkcfg |= ((3+offset) << 4); break; default: die("Target Memory Frequency Error"); } @@ -1993,54 +2130,128 @@ static void sdram_program_clock_crossing(void) { - u32 reg32; int idx = 0; /** * We add the indices according to our clocks from CLKCFG. */ - +#ifdef CHIPSET_I945GM static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ 0x08040120, 0x00000000, /* DDR400 FSB533 */ 0x00100401, 0x00000000, /* DDR533 FSB533 */ + 0xffffffff, 0xffffffff, /* nonexistant */ 0x04020120, 0x00000010, /* DDR400 FSB667 */ 0x10040280, 0x00000040, /* DDR533 FSB667 */ - 0x00100401, 0x00000000 /* DDR667 FSB667 */ + 0x00100401, 0x00000000, /* DDR667 FSB667 */ + + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ }; static const u32 command_clock_crossing[] = { 0x04020208, 0x00000000, /* DDR400 FSB400 */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ 0x00060108, 0x00000000, /* DDR400 FSB533 */ 0x04020108, 0x00000000, /* DDR533 FSB533 */ + 0xffffffff, 0xffffffff, /* nonexistant */ 0x00040318, 0x00000000, /* DDR400 FSB667 */ 0x04020118, 0x00000000, /* DDR533 FSB667 */ - 0x02010804, 0x00000000 /* DDR667 FSB667 */ + 0x02010804, 0x00000000, /* DDR667 FSB667 */ + + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ }; +#endif +#ifdef CHIPSET_I945GC + /* i945 G/P */ + static const u32 data_clock_crossing[] = { + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0x10080201, 0x00000000, /* DDR400 FSB533 */ + 0x00100401, 0x00000000, /* DDR533 FSB533 */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0x04020108, 0x00000000, /* DDR400 FSB800 */ + 0x00020108, 0x00000000, /* DDR533 FSB800 */ + 0x00080201, 0x00000000, /* DDR667 FSB800 */ + + 0x00010402, 0x00000000, /* DDR400 FSB1066 */ + 0x04020108, 0x00000000, /* DDR533 FSB1066 */ + 0x08040110, 0x00000000, /* DDR667 FSB1066 */ + }; + + static const u32 command_clock_crossing[] = { + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0x00010800, 0x00000402, /* DDR400 FSB533 */ + 0x01000400, 0x00000200, /* DDR533 FSB533 */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + 0xffffffff, 0xffffffff, /* nonexistant */ + + 0x02010804, 0x00000000, /* DDR400 FSB800 */ + 0x00010402, 0x00000000, /* DDR533 FSB800 */ + 0x04020180, 0x00000008, /* DDR667 FSB800 */ + + 0x00020904, 0x00000000, /* DDR400 FSB1066 */ + 0x02010804, 0x00000000, /* DDR533 FSB1066 */ + 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ + }; +#endif + printk_debug("Programming Clock Crossing..."); - reg32 = MCHBAR32(CLKCFG); printk_debug("MEM="); - switch ((reg32 >> 4) & 7) { - case 2: printk_debug("400"); idx += 0; break; - case 3: printk_debug("533"); idx += 2; break; - case 4: printk_debug("667"); idx += 4; break; - default: printk_debug("RSVD\n"); return; + switch (memclk()) { + case 400: printk_debug("400"); idx += 0; break; + case 533: printk_debug("533"); idx += 2; break; + case 667: printk_debug("667"); idx += 4; break; + default: printk_debug("RSVD %x", memclk()); return; } printk_debug(" FSB="); - switch (reg32 & 7) { - case 0: printk_debug("400\n"); idx += 0; break; - case 1: printk_debug("533"); idx += 2; break; - case 3: printk_debug("667"); idx += 6; break; - default: printk_debug("RSVD\n"); return; + switch (fsbclk()) { + case 400: printk_debug("400"); idx += 0; break; + case 533: printk_debug("533"); idx += 6; break; + case 667: printk_debug("667"); idx += 12; break; + case 800: printk_debug("800"); idx += 18; break; + case 1066: printk_debug("1066"); idx += 24; break; + default: printk_debug("RSVD %x\n", fsbclk()); return; } + if (command_clock_crossing[idx]==0xffffffff) { + printk_debug("Invalid MEM/FSB combination!\n"); + } + MCHBAR32(CCCFT + 0) = command_clock_crossing[idx]; MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1]; @@ -2560,17 +2771,23 @@ { u8 clocks[2] = { 0, 0 }; +#ifdef CHIPSET_I945GM +#define CLOCKS_WIDTH 2 +#endif +#ifdef CHIPSET_I945GC +#define CLOCKS_WIDTH 3 +#endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= (1 << 0) | (1 << 1); + clocks[0] |= (1 << CLOCKS_WIDTH)-1; if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) - clocks[0] |= (1 << 2) | (1 << 3); + clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= (1 << 0) | (1 << 1); + clocks[1] |= (1 << CLOCKS_WIDTH)-1; if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) - clocks[1] |= (1 << 2) | (1 << 3); + clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; #ifdef OVERRIDE_CLOCK_DISABLE /* Usually system firmware turns off system memory clock signals

1 0

KBuild Report [r5024]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 fail. [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 fail. [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights fail. [51/116] intel/jarrell fail. [52/116] intel/mtarvon fail. [53/116] intel/truxton fail. [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 fail. [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g fail. [86/116] supermicro/x6dhe_g fail. [87/116] supermicro/x6dhe_g2 fail. [88/116] supermicro/x6dhr_ig fail. [89/116] supermicro/x6dhr_ig2 fail. [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 fail. [97/116] tyan/s2850 fail. [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 fail. [100/116] tyan/s2881 fail. [101/116] tyan/s2882 fail. [102/116] tyan/s2885 fail. [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn fail. [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n fail. [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e fail. [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5024/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5023]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 fail. [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 fail. [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights fail. [51/116] intel/jarrell fail. [52/116] intel/mtarvon fail. [53/116] intel/truxton fail. [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 fail. [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g fail. [86/116] supermicro/x6dhe_g fail. [87/116] supermicro/x6dhe_g2 fail. [88/116] supermicro/x6dhr_ig fail. [89/116] supermicro/x6dhr_ig2 fail. [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 fail. [97/116] tyan/s2850 fail. [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 fail. [100/116] tyan/s2881 fail. [101/116] tyan/s2882 fail. [102/116] tyan/s2885 fail. [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn fail. [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n fail. [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e fail. [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5023/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5022]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5022/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5021]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5021/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5020]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5020/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5019]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5019/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5018]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf fail. [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5018/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

KBuild Report [r5017]
by coresystems autobuild service 16 Jan '10

16 Jan '10

[1/116] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/116] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/116] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/116] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/116] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/116] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/116] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/116] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/116] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/116] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/116] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/116] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/116] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/116] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/116] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GENERATE_MP_TABLE = 0x0 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/116] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/116] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/116] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/116] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/116] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/116] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/116] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/116] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/116] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/116] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/116] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/116] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/116] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/116] bcom/winnetp680 ok. Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/bcom/winnetp680/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [30/116] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/116] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/116] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/116] dell/s1850 ok. Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x1 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TTYS0_BAUD = 0x4b00 +CONFIG_TTYS0_BAUD = 0x1c200 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [34/116] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/116] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/116] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/116] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/116] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/116] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/116] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/116] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/116] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/116] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/116] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/116] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/116] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/116] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/116] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/116] intel/d945gclf ok. Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/intel/d945gclf/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xffed8000 +CONFIG_DCACHE_RAM_BASE = 0xffdf8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_GENERATE_ACPI_TABLES = 0x1 +CONFIG_GENERATE_ACPI_TABLES = 0x0 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HAVE_SMI_HANDLER = 0x1 +CONFIG_HAVE_SMI_HANDLER = 0x0 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [50/116] intel/eagleheights ok. Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE2 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x12 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [51/116] intel/jarrell ok. Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x12 +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_REBOOT_CNT = 0x8 +CONFIG_MAX_REBOOT_CNT = 0x3 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [52/116] intel/mtarvon ok. Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [53/116] intel/truxton ok. Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_EP80579 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [54/116] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/116] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/116] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/116] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/116] jetway/j7f24 ok. Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/jetway/j7f24/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [59/116] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/116] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/116] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/116] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/116] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/116] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/116] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/116] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/116] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/116] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/116] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/116] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/116] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/116] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/116] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/116] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/116] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/116] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/116] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/116] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/116] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/116] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [81/116] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/116] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [83/116] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/116] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [85/116] supermicro/x6dai_g ok. Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/116] supermicro/x6dhe_g ok. Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [87/116] supermicro/x6dhe_g2 ok. Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [88/116] supermicro/x6dhr_ig ok. Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [89/116] supermicro/x6dhr_ig2 ok. Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [90/116] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [91/116] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [92/116] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [93/116] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [94/116] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [95/116] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/116] tyan/s2735 ok. Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x1 +CONFIG_USE_PRINTK_IN_CAR = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/116] tyan/s2850 ok. Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [98/116] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [99/116] tyan/s2880 ok. Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xd +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/116] tyan/s2881 ok. Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [101/116] tyan/s2882 ok. Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xf +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [102/116] tyan/s2885 ok. Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0xb +CONFIG_IRQ_SLOT_COUNT = 0x9 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [103/116] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [104/116] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [105/116] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [106/116] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [107/116] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [108/116] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/116] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/116] via/epia-cn ok. Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/via/epia-cn/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 [111/116] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [112/116] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [113/116] via/epia-n ok. Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/via/epia-n/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN400_VIDEO_MB_128MB = 0x0 +CONFIG_CN400_VIDEO_MB_16MB = 0x0 +CONFIG_CN400_VIDEO_MB_32MB = 0x1 +CONFIG_CN400_VIDEO_MB_64MB = 0x0 +CONFIG_CN400_VIDEO_MB_8MB = 0x0 +CONFIG_CN400_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [114/116] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [115/116] via/pc2500e ok. Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/via/pc2500e/Config-abuild.lb ok Creating builddir...ok +CONFIG_CN700_VIDEO_MB_128MB = 0x0 +CONFIG_CN700_VIDEO_MB_16MB = 0x0 +CONFIG_CN700_VIDEO_MB_32MB = 0x1 +CONFIG_CN700_VIDEO_MB_64MB = 0x0 +CONFIG_CN700_VIDEO_MB_8MB = 0x0 +CONFIG_CN700_VIDEO_MB_OFF = 0x0 +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_USE_OPTION_TABLE = 0x1 +CONFIG_USE_OPTION_TABLE = 0x0 [116/116] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5017/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

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coreboot January 2010