[1/116] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/116] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/116] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/116] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/116] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x4
+CONFIG_IRQ_SLOT_COUNT = 0x6
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/116] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
[7/116] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/116] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/116] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/116] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x1
+CONFIG_ACPI_SSDTX_NUM = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/116] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/116] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/116] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/116] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/116] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GENERATE_MP_TABLE = 0x0
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/116] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/116] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/116] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/116] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/116] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/116] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/116] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_AGP_APERTURE_SIZE = 0x4000000
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_ADDR_BITS = 0x24
+CONFIG_CPU_ADDR_BITS = 0x28
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc0000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_ID_SECTION_OFFSET = 0x10
+CONFIG_ID_SECTION_OFFSET = 0x80
-CONFIG_IRQ_SLOT_COUNT = 0x7
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x0
+CONFIG_MEM_TRAIN_SEQ = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x40000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_USE_DCACHE_RAM = 0x0
+CONFIG_USE_DCACHE_RAM = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x0
+CONFIG_USE_PRINTK_IN_CAR = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/116] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/116] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/116] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/116] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/116] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/116] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/116] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[30/116] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/116] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/116] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/116] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x1
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/116] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/116] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/116] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x7
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/116] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/116] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/116] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x6
+CONFIG_IRQ_SLOT_COUNT = 0x5
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/116] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/116] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/116] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/116] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[44/116] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/116] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/116] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/116] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/116] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/116] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GENERATE_ACPI_TABLES = 0x1
+CONFIG_GENERATE_ACPI_TABLES = 0x0
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HAVE_SMI_HANDLER = 0x1
+CONFIG_HAVE_SMI_HANDLER = 0x0
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/116] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x12
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/116] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x12
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/116] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/116] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/116] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/116] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/116] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0xc
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/116] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/116] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/116] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/116] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/116] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/116] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/116] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/116] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/116] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/116] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/116] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/116] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/116] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/116] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/116] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/116] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/116] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/116] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/116] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/116] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/116] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/116] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/116] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/116] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[81/116] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/116] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[83/116] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/116] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[85/116] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/116] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/116] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/116] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/116] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/116] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[91/116] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[92/116] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x20000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[93/116] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[94/116] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[95/116] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/116] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/116] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/116] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/116] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xd
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/116] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/116] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xf
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/116] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xb
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/116] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
[104/116] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/116] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[106/116] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[107/116] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[108/116] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/116] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/116] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[111/116] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
[112/116] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[113/116] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[114/116] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[115/116] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[116/116] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5016/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
[1/116] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/116] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/116] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/116] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/116] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x4
+CONFIG_IRQ_SLOT_COUNT = 0x6
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/116] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
[7/116] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/116] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/116] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/116] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x1
+CONFIG_ACPI_SSDTX_NUM = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/116] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/116] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/116] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/116] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/116] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GENERATE_MP_TABLE = 0x0
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/116] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/116] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/116] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/116] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/116] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/116] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/116] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_AGP_APERTURE_SIZE = 0x4000000
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_ADDR_BITS = 0x24
+CONFIG_CPU_ADDR_BITS = 0x28
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc0000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_ID_SECTION_OFFSET = 0x10
+CONFIG_ID_SECTION_OFFSET = 0x80
-CONFIG_IRQ_SLOT_COUNT = 0x7
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x0
+CONFIG_MEM_TRAIN_SEQ = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x40000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_USE_DCACHE_RAM = 0x0
+CONFIG_USE_DCACHE_RAM = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x0
+CONFIG_USE_PRINTK_IN_CAR = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/116] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/116] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/116] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/116] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/116] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/116] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/116] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[30/116] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/116] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/116] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/116] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x1
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/116] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/116] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/116] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x7
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/116] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/116] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/116] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x6
+CONFIG_IRQ_SLOT_COUNT = 0x5
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/116] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/116] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/116] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/116] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[44/116] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/116] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/116] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/116] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/116] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/116] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GENERATE_ACPI_TABLES = 0x1
+CONFIG_GENERATE_ACPI_TABLES = 0x0
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HAVE_SMI_HANDLER = 0x1
+CONFIG_HAVE_SMI_HANDLER = 0x0
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/116] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x12
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/116] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x12
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/116] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/116] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/116] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/116] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/116] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0xc
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/116] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/116] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/116] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/116] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/116] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/116] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/116] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/116] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/116] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/116] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/116] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/116] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/116] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/116] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/116] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/116] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/116] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/116] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/116] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/116] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/116] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/116] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/116] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/116] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[81/116] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/116] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[83/116] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/116] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[85/116] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/116] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/116] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/116] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/116] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/116] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[91/116] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[92/116] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x20000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[93/116] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[94/116] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[95/116] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/116] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/116] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/116] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/116] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xd
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/116] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/116] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xf
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/116] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xb
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/116] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
[104/116] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/116] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[106/116] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[107/116] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[108/116] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/116] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/116] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[111/116] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
[112/116] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[113/116] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[114/116] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[115/116] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[116/116] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5015/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info(a)coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
2
1
16 Jan '10
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info(a)coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
2
1
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info(a)coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
2
1
[PATCH 2/2] msrtool: Read both MSR values in diff mode from file, if available
by Peter Stuge 16 Jan '10
by Peter Stuge 16 Jan '10
16 Jan '10
Previously, msrtool would assume that MSR values should be compared
between stored value in file and current value in hardware which msrtool
was running on. This does not always fit the use case and with this
change msrtool can now compare two sets of MSR values stored in a file.
If only one MSR value is stored in the file, msrtool will behave as
previously and read the second MSR value from hardware.
This change means that msrtool does not always need access to the system
MSR functions so it can now be run as a regular user when using diff
mode with both MSR values stored in the file.
Signed-off-by: Peter Stuge <peter(a)stuge.se>
---
msrtool.c | 59 +++++++++++++++++++++++++++++++++++++----------------------
1 files changed, 37 insertions(+), 22 deletions(-)
diff --git a/msrtool.c b/msrtool.c
index 41e7e2c..47b4938 100644
--- a/msrtool.c
+++ b/msrtool.c
@@ -93,6 +93,16 @@ static void *add_target(const struct targetdef *t) {
return targets;
}
+static int found_system() {
+ if (!sys || (sys && !sys->name)) {
+ fprintf(stderr, "Unable to detect the current operating system!\n");
+ fprintf(stderr, "On Linux, please run 'modprobe msr' and try again.\n");
+ fprintf(stderr, "Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help!\n");
+ fprintf(stderr, "\n");
+ }
+ return (sys && sys->name);
+}
+
int do_stream(const char *streamfn, uint8_t ignoreinput) {
char tmpfn[20], line[256];
uint8_t tn;
@@ -132,6 +142,8 @@ int do_stream(const char *streamfn, uint8_t ignoreinput) {
}
}
+ if (!found_system())
+ goto done;
if (!sys->open(cpu, SYS_RDONLY))
goto done;
if (ignoreinput) {
@@ -180,9 +192,9 @@ done:
}
int do_diff(const char *difffn) {
- char tmpfn[20], line[512], *m1start;
+ char tmpfn[20], line[512], *m1start, *m2start;
size_t len;
- int ret = 1, tmp, m1pos;
+ int ret = 1, tmp, m1pos, sys_opened = 0;
FILE *fin = NULL, *fout = stdout;
uint8_t rev = 0;
uint32_t addr, linenum;
@@ -199,8 +211,6 @@ int do_diff(const char *difffn) {
return 1;
}
- if (!sys->open(cpu, SYS_RDONLY))
- goto done;
for (linenum = 1; NULL != fgets(line, sizeof(line), fin); ++linenum) {
tmp = strncmp("0x", line, 2) ? 0 : 2;
if (sscanf(line + tmp, "%8x %n%*x", &addr, &m1pos) < 1)
@@ -208,12 +218,24 @@ int do_diff(const char *difffn) {
m1start = line + tmp + m1pos;
for (len = strlen(m1start) - 1; NULL != strchr("\r\n", m1start[len]); --len)
m1start[len] = 0;
- if (!str2msr(m1start, &m1, NULL)) {
- fprintf(stderr, "%s:%d: invalid MSR value '%s'\n", difffn, linenum, m1start);
+ if (!str2msr(m1start, &m1, &m2start)) {
+ fprintf(stderr, "%s:%d: invalid MSR1 value '%s'\n", difffn, linenum, m1start);
continue;
}
- if (!sys->rdmsr(cpu, addr, &m2))
- goto done;
+ while (' ' == *m2start)
+ ++m2start;
+ if (!str2msr(m2start, &m2, NULL)) {
+ fprintf(stderr, "%s:%d: invalid MSR2 value '%s' - reading from hardware!\n", difffn, linenum, m2start);
+ if (!sys_opened) {
+ if (!found_system())
+ goto done;
+ sys_opened = sys->open(cpu, SYS_RDONLY);
+ if (!sys_opened)
+ goto done;
+ }
+ if (!sys->rdmsr(cpu, addr, &m2))
+ goto done;
+ }
if (diff_msr(fout, addr, rev ? m2 : m1, rev ? m1 : m2))
fprintf(fout, "\n");
}
@@ -222,7 +244,8 @@ int do_diff(const char *difffn) {
else
ret = 0;
done:
- sys->close(cpu);
+ if (sys_opened)
+ sys->close(cpu);
if (strcmp(difffn, "-")) {
if (ret)
unlink(tmpfn);
@@ -351,13 +374,6 @@ int main(int argc, char *argv[]) {
return 0;
}
- if (sys && !sys->name) {
- fprintf(stderr, "Unable to detect the current operating system!\n");
- fprintf(stderr, "On Linux, please do 'modprobe msr' and retry.\n");
- fprintf(stderr, "Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help!\n");
- fprintf(stderr, "\n");
- }
-
if (!targets_found || !targets) {
fprintf(stderr, "Unable to detect a known target; can not decode any MSRs! (Use -t to force)\n");
fprintf(stderr, "Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help!\n");
@@ -370,9 +386,6 @@ int main(int argc, char *argv[]) {
return 0;
}
- if (sys && !sys->name)
- return 1;
-
if (listmsrs) {
if (streamfn)
return do_stream(streamfn, 1);
@@ -388,9 +401,6 @@ int main(int argc, char *argv[]) {
if (streamfn)
return do_stream(streamfn, 0);
- if (!sys->open(cpu, SYS_RDONLY))
- return 1;
-
if (difffn) {
ret = do_diff(difffn);
goto done;
@@ -402,6 +412,11 @@ int main(int argc, char *argv[]) {
goto done;
}
+ if (!found_system())
+ return 1;
+ if (!sys->open(cpu, SYS_RDONLY))
+ return 1;
+
for (; optind < argc; optind++) {
addr = msraddrbyname(argv[optind]);
if (!sys->rdmsr(cpu, addr, &msrval))
--
1.6.3.3
--z6Eq5LdranGa6ru8--
1
0
[PATCH 1/2] msrtool: Add endptr to str2msr() showing how many characters were parsed
by Peter Stuge 16 Jan '10
by Peter Stuge 16 Jan '10
16 Jan '10
This also introduces a small change in the user interface for immediate
mode (-i). Previously, whitespace could separate high and low words in
an MSR as such:
msrtool -i 4c00000f='f2f100ff 56960004'
That is no longer allowed, a space character now ends the MSR value. Any
other character can still be used as separator however, so the following
syntax still works as expected:
msrtool -i 4c00000f=f2f100ff:56960004
Signed-off-by: Peter Stuge <peter(a)stuge.se>
---
msrtool.c | 4 ++--
msrtool.h | 2 +-
msrutils.c | 9 +++++----
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/msrtool.c b/msrtool.c
index 570f1fb..41e7e2c 100644
--- a/msrtool.c
+++ b/msrtool.c
@@ -208,7 +208,7 @@ int do_diff(const char *difffn) {
m1start = line + tmp + m1pos;
for (len = strlen(m1start) - 1; NULL != strchr("\r\n", m1start[len]); --len)
m1start[len] = 0;
- if (!str2msr(m1start, &m1)) {
+ if (!str2msr(m1start, &m1, NULL)) {
fprintf(stderr, "%s:%d: invalid MSR value '%s'\n", difffn, linenum, m1start);
continue;
}
@@ -288,7 +288,7 @@ int main(int argc, char *argv[]) {
fprintf(stderr, "missing value in -i argument!\n");
break;
}
- if (!str2msr(++optarg, &msrval))
+ if (!str2msr(++optarg, &msrval, NULL))
fprintf(stderr, "invalid value in -i argument!\n");
break;
case 's':
diff --git a/msrtool.h b/msrtool.h
index d8fc00f..cf77b49 100644
--- a/msrtool.h
+++ b/msrtool.h
@@ -170,7 +170,7 @@ const struct msrdef *findmsrdef(const uint32_t addr);
uint32_t msraddrbyname(const char *name);
void dumpmsrdefs(const struct targetdef *t);
int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu);
-uint8_t str2msr(char *str, struct msr *msr);
+uint8_t str2msr(char *str, struct msr *msr, char **endptr);
void decodemsr(const uint8_t cpu, const uint32_t addr, const struct msr val);
uint8_t diff_msr(FILE *fout, const uint32_t addr, const struct msr a, const struct msr b);
diff --git a/msrutils.c b/msrutils.c
index dfb6617..5a5fbd8 100644
--- a/msrutils.c
+++ b/msrutils.c
@@ -193,7 +193,7 @@ int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu) {
* Parse a hexadecimal string into an MSR value.
*
* Leading 0x or 0X is optional, the string is always parsed as hexadecimal.
- * Any non-hexadecimal character can be used to separate the high 32 bits and
+ * Any non-hexadecimal character except ' ' can separate the high 32 bits and
* the low 32 bits. If there is such a separator, high and low values do not
* need to be zero padded. If there is no separator, the last <=8 digits are
* the low 32 bits and any characters before them are the high 32 bits.
@@ -205,15 +205,16 @@ int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu) {
* @param str The string to parse. The string must be writable but will be
* restored before return.
* @param msr Pointer to the struct msr where the value will be stored.
+ * @param endptr If endpotr is not NULL, *endptr will point to after the MSR.
* @return 1 on success, 0 on parse failure. msr is unchanged on failure.
*/
-uint8_t str2msr(char *str, struct msr *msr) {
+uint8_t str2msr(char *str, struct msr *msr, char **endptr) {
char c;
size_t len, lo;
if (0 == strncmp(str, "0x", 2) || 0 == strncmp(str, "0X", 2))
str += 2;
len = strspn(str, HEXCHARS);
- if (len <= 8 && 0 == str[len]) {
+ if (len <= 8 && (0 == str[len] || ' ' == str[len])) {
msr->hi = 0;
lo = 0;
} else if (len <= 8) {
@@ -231,7 +232,7 @@ uint8_t str2msr(char *str, struct msr *msr) {
msr->hi = strtoul(str, NULL, 16);
str[lo] = c;
}
- msr->lo = strtoul(str + lo, NULL, 16);
+ msr->lo = strtoul(str + lo, endptr, 16);
return 1;
}
--
1.6.3.3
--z6Eq5LdranGa6ru8
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="0002-msrtool-Read-both-MSR-values-in-diff-mode-from-file-.patch"
1
0
[1/116] a-trend/atc-6220 ok.
Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[2/116] a-trend/atc-6240 ok.
Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[3/116] abit/be6-ii_v2_0 ok.
Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[4/116] advantech/pcm-5820 ok.
Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[5/116] amd/db800 ok.
Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x4
+CONFIG_IRQ_SLOT_COUNT = 0x6
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[6/116] amd/dbm690t ok.
Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/amd/dbm690t/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
[7/116] amd/norwich ok.
Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[8/116] amd/pistachio ok.
Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/amd/pistachio/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[9/116] amd/rumba ok.
Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[10/116] amd/serengeti_cheetah ok.
Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/amd/serengeti_cheetah/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x1
+CONFIG_ACPI_SSDTX_NUM = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[11/116] amd/serengeti_cheetah_fam10 ok.
Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[12/116] arima/hdama ok.
Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/arima/hdama/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[13/116] artecgroup/dbe61 ok.
Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[14/116] asi/mb_5blgp ok.
Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[15/116] asi/mb_5blmp ok.
Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_GENERATE_MP_TABLE = 0x0
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[16/116] asus/a8n_e ok.
Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/asus/a8n_e/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[17/116] asus/a8v-e_se ok.
Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[18/116] asus/m2v-mx_se ok.
Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/asus/m2v-mx_se/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x1f00000
+CONFIG_RAMBASE = 0x100000
-CONFIG_RAMTOP = 0x2000000
+CONFIG_RAMTOP = 0x200000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[19/116] asus/mew-am ok.
Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[20/116] asus/mew-vm ok.
Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[21/116] asus/p2b-d ok.
Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[22/116] asus/p2b-ds ok.
Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_AGP_APERTURE_SIZE = 0x4000000
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_ADDR_BITS = 0x24
+CONFIG_CPU_ADDR_BITS = 0x28
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc0000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_ID_SECTION_OFFSET = 0x10
+CONFIG_ID_SECTION_OFFSET = 0x80
-CONFIG_IRQ_SLOT_COUNT = 0x7
+CONFIG_IRQ_SLOT_COUNT = 0xd
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x0
+CONFIG_MEM_TRAIN_SEQ = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x40000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_USE_DCACHE_RAM = 0x0
+CONFIG_USE_DCACHE_RAM = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x0
+CONFIG_USE_PRINTK_IN_CAR = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[23/116] asus/p2b-f ok.
Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[24/116] asus/p2b ok.
Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[25/116] asus/p3b-f ok.
Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[26/116] axus/tc320 ok.
Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[27/116] azza/pt-6ibd ok.
Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[28/116] bcom/winnet100 ok.
Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[29/116] bcom/winnetp680 ok.
Processing mainboard/bcom/winnetp680 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/bcom/winnetp680/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[30/116] biostar/m6tba ok.
Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[31/116] broadcom/blast ok.
Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[32/116] compaq/deskpro_en_sff_p600 ok.
Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[33/116] dell/s1850 ok.
Processing mainboard/dell/s1850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x1
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TTYS0_BAUD = 0x4b00
+CONFIG_TTYS0_BAUD = 0x1c200
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[34/116] digitallogic/adl855pc ok.
Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[35/116] digitallogic/msm586seg ok.
Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/digitallogic/msm586seg/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[36/116] digitallogic/msm800sev ok.
Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x7
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[37/116] eaglelion/5bcm ok.
Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[38/116] emulation/qemu-x86 ok.
Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/emulation/qemu-x86/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_EMULATION_QEMU_X86 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0x8f000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[39/116] gigabyte/ga-6bxc ok.
Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x6
+CONFIG_IRQ_SLOT_COUNT = 0x5
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[40/116] gigabyte/ga_2761gxdk ok.
Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x0
+CONFIG_SMP = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[41/116] gigabyte/m57sli ok.
Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/gigabyte/m57sli/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[42/116] hp/dl145_g3 ok.
Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[43/116] hp/e_vectra_p2706t ok.
Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
[44/116] ibm/e325 ok.
Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[45/116] ibm/e326 ok.
Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/ibm/e326/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[46/116] iei/juki-511p ok.
Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/iei/juki-511p/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[47/116] iei/nova4899r ok.
Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_GX1_VIDEO = 0x1
+CONFIG_GX1_VIDEOMODE = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
+CONFIG_SPLASH_GRAPHIC = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[48/116] iei/pcisa-lx-800-r10 ok.
Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_UDELAY_IO = 0x1
+CONFIG_UDELAY_IO = 0x0
-CONFIG_UDELAY_TSC = 0x0
+CONFIG_UDELAY_TSC = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[49/116] intel/d945gclf ok.
Processing mainboard/intel/d945gclf (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/intel/d945gclf/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xffed8000
+CONFIG_DCACHE_RAM_BASE = 0xffdf8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_GENERATE_ACPI_TABLES = 0x1
+CONFIG_GENERATE_ACPI_TABLES = 0x0
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
-CONFIG_HAVE_ACPI_RESUME = 0x1
+CONFIG_HAVE_ACPI_RESUME = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HAVE_SMI_HANDLER = 0x1
+CONFIG_HAVE_SMI_HANDLER = 0x0
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[50/116] intel/eagleheights ok.
Processing mainboard/intel/eagleheights (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE2 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0x12
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x8086
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[51/116] intel/jarrell ok.
Processing mainboard/intel/jarrell (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x12
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_REBOOT_CNT = 0x8
+CONFIG_MAX_REBOOT_CNT = 0x3
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[52/116] intel/mtarvon ok.
Processing mainboard/intel/mtarvon (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[53/116] intel/truxton ok.
Processing mainboard/intel/truxton (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_EP80579 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LB_CKS_LOC = 0x7e
+CONFIG_LB_CKS_LOC = 0x7b
-CONFIG_LB_CKS_RANGE_END = 0x7d
+CONFIG_LB_CKS_RANGE_END = 0x7a
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[54/116] intel/xe7501devkit ok.
Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[55/116] iwill/dk8_htx ok.
Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/iwill/dk8_htx/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xc4000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_SIZE = 0xc000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HW_MEM_HOLE_SIZEK = 0x80000
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[56/116] iwill/dk8s2 ok.
Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_ATI_RAGE_XL = 0x1
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0xc
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[57/116] iwill/dk8x ok.
Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[58/116] jetway/j7f24 ok.
Processing mainboard/jetway/j7f24 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/jetway/j7f24/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[59/116] kontron/986lcd-m ok.
Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/kontron/986lcd-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_INTEL_CORE = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
[60/116] kontron/kt690 ok.
Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/kontron/kt690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[61/116] lippert/frontrunner ok.
Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[62/116] lippert/roadrunner-lx ok.
Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[63/116] lippert/spacerunner-lx ok.
Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
-CONFIG_DEBUG = 0x1
+CONFIG_DEBUG = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[64/116] mitac/6513wu ok.
Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[65/116] msi/ms6119 ok.
Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[66/116] msi/ms6147 ok.
Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[67/116] msi/ms6156 ok.
Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[68/116] msi/ms6178 ok.
Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[69/116] msi/ms7135 ok.
Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/msi/ms7135/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_DCACHE_RAM_BASE = 0xc8000
+CONFIG_DCACHE_RAM_BASE = 0xcf000
-CONFIG_DCACHE_RAM_SIZE = 0x8000
+CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[70/116] msi/ms7260 ok.
Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/msi/ms7260/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_MEM_TRAIN_SEQ = 0x2
+CONFIG_MEM_TRAIN_SEQ = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[71/116] msi/ms9185 ok.
Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/msi/ms9185/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x8
+CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x6
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[72/116] msi/ms9282 ok.
Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/msi/ms9282/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HW_MEM_HOLE_SIZEK = 0x0
+CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[73/116] nec/powermate2000 ok.
Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I810_VIDEO_MB_1MB = 0x1
+CONFIG_I810_VIDEO_MB_512KB = 0x0
+CONFIG_I810_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[74/116] newisys/khepri ok.
Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x9
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[75/116] nvidia/l1_2pvv ok.
Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/nvidia/l1_2pvv/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[76/116] olpc/btest ok.
Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[77/116] olpc/rev_a ok.
Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[78/116] pcengines/alix1c ok.
Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_LX = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[79/116] rca/rm4100 ok.
Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/rca/rm4100/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[80/116] soyo/sy-6ba-plus-iii ok.
Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[81/116] sunw/ultra40 ok.
Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[82/116] supermicro/h8dme ok.
Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/supermicro/h8dme/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_LOW_TABLES = 0x0
+CONFIG_HAVE_LOW_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[83/116] supermicro/h8dmr ok.
Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/supermicro/h8dmr/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_ROM_SIZE = 0x100000
+CONFIG_ROM_SIZE = 0x80000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[84/116] supermicro/h8dmr_fam10 ok.
Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[85/116] supermicro/x6dai_g ok.
Processing mainboard/supermicro/x6dai_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[86/116] supermicro/x6dhe_g ok.
Processing mainboard/supermicro/x6dhe_g (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[87/116] supermicro/x6dhe_g2 ok.
Processing mainboard/supermicro/x6dhe_g2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[88/116] supermicro/x6dhr_ig ok.
Processing mainboard/supermicro/x6dhr_ig (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[89/116] supermicro/x6dhr_ig2 ok.
Processing mainboard/supermicro/x6dhr_ig2 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[90/116] technexion/tim5690 ok.
Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/technexion/tim5690/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
[91/116] technexion/tim8690 ok.
Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/technexion/tim8690/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x8
-CONFIG_GFXUMA = 0x1
+CONFIG_GFXUMA = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
-CONFIG_HAVE_OPTION_TABLE = 0x0
+CONFIG_HAVE_OPTION_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x0
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
[92/116] technologic/ts5300 ok.
Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/technologic/ts5300/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_AMD_SC520 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x20000
+CONFIG_ROM_SIZE = 0x40000
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
-CONFIG_TTYS0_BASE = 0x2f8
+CONFIG_TTYS0_BASE = 0x3f8
+CONFIG_UDELAY_LAPIC = 0x0
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[93/116] televideo/tc7020 ok.
Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_AMD_GX1 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[94/116] thomson/ip1000 ok.
Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/thomson/ip1000/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
+CONFIG_I830_VIDEO_MB_1MB = 0x0
+CONFIG_I830_VIDEO_MB_512KB = 0x0
+CONFIG_I830_VIDEO_MB_8MB = 0x1
+CONFIG_I830_VIDEO_MB_OFF = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
+CONFIG_MMX = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[95/116] tyan/s1846 ok.
Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_INTEL_SLOT_2 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[96/116] tyan/s2735 ok.
Processing mainboard/tyan/s2735 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_MOVNTI = 0x1
+CONFIG_HAVE_MOVNTI = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
+CONFIG_MMX = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
-CONFIG_USE_PRINTK_IN_CAR = 0x1
+CONFIG_USE_PRINTK_IN_CAR = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[97/116] tyan/s2850 ok.
Processing mainboard/tyan/s2850 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[98/116] tyan/s2875 ok.
Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[99/116] tyan/s2880 ok.
Processing mainboard/tyan/s2880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xd
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAX_CPUS = 0x2
+CONFIG_MAX_CPUS = 0x4
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[100/116] tyan/s2881 ok.
Processing mainboard/tyan/s2881 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[101/116] tyan/s2882 ok.
Processing mainboard/tyan/s2882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0xa
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xf
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[102/116] tyan/s2885 ok.
Processing mainboard/tyan/s2885 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0xb
+CONFIG_IRQ_SLOT_COUNT = 0x9
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[103/116] tyan/s2891 ok.
Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/tyan/s2891/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
[104/116] tyan/s2892 ok.
Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/tyan/s2892/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_APIC_ID_OFFSET = 0x0
+CONFIG_APIC_ID_OFFSET = 0x10
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
[105/116] tyan/s2895 ok.
Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/tyan/s2895/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_BASE = 0xcf000
+CONFIG_DCACHE_RAM_BASE = 0xc8000
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DIMM_SUPPORT = 0x108
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x0
+CONFIG_SERIAL_CPU_INIT = 0x1
[106/116] tyan/s2912 ok.
Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/tyan/s2912/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_ACPI_SSDTX_NUM = 0x3
+CONFIG_ACPI_SSDTX_NUM = 0x0
-CONFIG_APIC_ID_OFFSET = 0x10
+CONFIG_APIC_ID_OFFSET = 0x16
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HEAP_SIZE = 0x8000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_MAX_CPUS = 0x4
+CONFIG_MAX_CPUS = 0x2
-CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_MAX_PHYSICAL_CPUS = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
-CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1
+CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0
[107/116] tyan/s2912_fam10 ok.
Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/tyan/s2912_fam10/Config-abuild.lb ok
Creating builddir...ok
-CONFIG_HAVE_FALLBACK_BOOT = 0x1
+CONFIG_HAVE_FALLBACK_BOOT = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_SERIAL_CPU_INIT = 0x1
+CONFIG_SERIAL_CPU_INIT = 0x0
-CONFIG_USE_FALLBACK_IMAGE = 0x1
+CONFIG_USE_FALLBACK_IMAGE = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[108/116] tyan/s4880 ok.
Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
-CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
-CONFIG_RAMBASE = 0x4000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[109/116] tyan/s4882 ok.
Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
-CONFIG_CPU_SOCKET_TYPE = 0x10
+CONFIG_CPU_SOCKET_TYPE = 0x0
-CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000
-CONFIG_DIMM_SUPPORT = 0x108
-CONFIG_ENABLE_APIC_EXT_ID = 0x1
+CONFIG_ENABLE_APIC_EXT_ID = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20
+CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-CONFIG_HT_CHAIN_UNITID_BASE = 0x1
+CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-CONFIG_IRQ_SLOT_COUNT = 0x16
+CONFIG_IRQ_SLOT_COUNT = 0xb
-CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0
+CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1
-CONFIG_MAX_CPUS = 0x8
+CONFIG_MAX_CPUS = 0x4
-CONFIG_MAX_PHYSICAL_CPUS = 0x4
+CONFIG_MAX_PHYSICAL_CPUS = 0x2
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_RAMBASE = 0x2000
+CONFIG_RAMBASE = 0x100000
-CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0
+CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2
-CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[110/116] via/epia-cn ok.
Processing mainboard/via/epia-cn (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/via/epia-cn/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
[111/116] via/epia-m ok.
Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/via/epia-m/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x1
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
[112/116] via/epia-m700 ok.
Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/via/epia-m700/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_SIZE = 0x2000
+CONFIG_DCACHE_RAM_SIZE = 0x8000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HEAP_SIZE = 0x5000
+CONFIG_HEAP_SIZE = 0x4000
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
[113/116] via/epia-n ok.
Processing mainboard/via/epia-n (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/via/epia-n/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN400_VIDEO_MB_128MB = 0x0
+CONFIG_CN400_VIDEO_MB_16MB = 0x0
+CONFIG_CN400_VIDEO_MB_32MB = 0x1
+CONFIG_CN400_VIDEO_MB_64MB = 0x0
+CONFIG_CN400_VIDEO_MB_8MB = 0x0
+CONFIG_CN400_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_ACPI_TABLES = 0x1
+CONFIG_HAVE_HIGH_TABLES = 0x0
-CONFIG_HAVE_INIT_TIMER = 0x1
+CONFIG_HAVE_INIT_TIMER = 0x0
-CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1
+CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_UDELAY_IO = 0x0
+CONFIG_UDELAY_IO = 0x1
-CONFIG_UDELAY_TSC = 0x1
+CONFIG_UDELAY_TSC = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
[114/116] via/epia ok.
Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler)
Creating config file... ok
Creating builddir...ok
+CONFIG_CPU_VIA_C3 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1
+CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0
+CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0
-CONFIG_PCI_ROM_RUN = 0x0
+CONFIG_PCI_ROM_RUN = 0x1
-CONFIG_VGA_ROM_RUN = 0x0
+CONFIG_VGA_ROM_RUN = 0x1
[115/116] via/pc2500e ok.
Processing mainboard/via/pc2500e (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/via/pc2500e/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CN700_VIDEO_MB_128MB = 0x0
+CONFIG_CN700_VIDEO_MB_16MB = 0x0
+CONFIG_CN700_VIDEO_MB_32MB = 0x1
+CONFIG_CN700_VIDEO_MB_64MB = 0x0
+CONFIG_CN700_VIDEO_MB_8MB = 0x0
+CONFIG_CN700_VIDEO_MB_OFF = 0x0
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DCACHE_RAM_BASE = 0xc0000
-CONFIG_DCACHE_RAM_SIZE = 0x1000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_EPIA_VT8237R_INIT = 0x0
+CONFIG_FALLBACK_SIZE = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x1
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0
+CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1
-CONFIG_USE_OPTION_TABLE = 0x1
+CONFIG_USE_OPTION_TABLE = 0x0
[116/116] via/vt8454c ok.
Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler)
Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5014/targets/via/vt8454c/Config-abuild.lb ok
Creating builddir...ok
+CONFIG_CPU_VIA_C7 = 0x1
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8
+CONFIG_HAVE_ACPI_TABLES = 0x1
-CONFIG_HAVE_HARD_RESET = 0x1
+CONFIG_HAVE_HARD_RESET = 0x0
+CONFIG_HAVE_HIGH_TABLES = 0x0
+CONFIG_HAVE_MP_TABLE = 0x1
+CONFIG_HAVE_PIRQ_TABLE = 0x1
-CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0
-CONFIG_IOAPIC = 0x1
+CONFIG_IOAPIC = 0x0
-CONFIG_LOGICAL_CPUS = 0x0
+CONFIG_LOGICAL_CPUS = 0x1
-CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8
-CONFIG_ROM_SIZE = 0x80000
+CONFIG_ROM_SIZE = 0x100000
-CONFIG_SMP = 0x1
+CONFIG_SMP = 0x0
-CONFIG_USE_DCACHE_RAM = 0x1
+CONFIG_USE_DCACHE_RAM = 0x0
-CONFIG_WRITE_HIGH_TABLES = 0x1
+CONFIG_WRITE_HIGH_TABLES = 0x0
1
0
Author: stuge
Date: 2010-01-16 19:39:35 +0100 (Sat, 16 Jan 2010)
New Revision: 5024
Modified:
trunk/util/msrtool/msrtool.c
Log:
msrtool: More trivial rearrangement
Rename some variables
Remove the 'found' variable which turns out not to be needed anyway
Signed-off-by: Peter Stuge <peter(a)stuge.se>
Acked-by: Peter Stuge <peter(a)stuge.se>
Modified: trunk/util/msrtool/msrtool.c
===================================================================
--- trunk/util/msrtool/msrtool.c 2010-01-16 18:31:34 UTC (rev 5023)
+++ trunk/util/msrtool/msrtool.c 2010-01-16 18:39:35 UTC (rev 5024)
@@ -180,13 +180,13 @@
}
int do_diff(const char *difffn) {
- char tmpfn[20], line[512];
- size_t start, len;
- int ret = 1, found, tmp;
+ char tmpfn[20], line[512], *m1start;
+ size_t len;
+ int ret = 1, tmp, m1pos;
FILE *fin = NULL, *fout = stdout;
uint8_t rev = 0;
uint32_t addr, linenum;
- struct msr mf = MSR1(0), mhw = MSR1(0);
+ struct msr m1 = MSR1(0), m2 = MSR1(0);
if (':' == difffn[0]) {
rev = 1;
@@ -202,20 +202,19 @@
if (!sys->open(cpu, SYS_RDONLY))
goto done;
for (linenum = 1; NULL != fgets(line, sizeof(line), fin); ++linenum) {
- start = (0 == strncmp("0x", line, 2)) ? 2 : 0;
- found = sscanf(line + start, "%8x %n%*x", &addr, &tmp);
- if (found < 1)
+ tmp = strncmp("0x", line, 2) ? 0 : 2;
+ if (sscanf(line + tmp, "%8x %n%*x", &addr, &m1pos) < 1)
continue;
- start += tmp;
- for (len = strlen(line) - 1; NULL != strchr("\r\n", line[len]); --len)
- line[len] = 0;
- if (!str2msr(line + start, &mf)) {
- fprintf(stderr, "%s:%d: invalid MSR value '%s'\n", difffn, linenum, line + start);
+ m1start = line + tmp + m1pos;
+ for (len = strlen(m1start) - 1; NULL != strchr("\r\n", m1start[len]); --len)
+ m1start[len] = 0;
+ if (!str2msr(m1start, &m1)) {
+ fprintf(stderr, "%s:%d: invalid MSR value '%s'\n", difffn, linenum, m1start);
continue;
}
- if (!sys->rdmsr(cpu, addr, &mhw))
+ if (!sys->rdmsr(cpu, addr, &m2))
goto done;
- if (diff_msr(fout, addr, rev ? mhw : mf, rev ? mf : mhw))
+ if (diff_msr(fout, addr, rev ? m2 : m1, rev ? m1 : m2))
fprintf(fout, "\n");
}
if (!feof(fin))
1
0
Author: stepan
Date: 2010-01-16 19:31:34 +0100 (Sat, 16 Jan 2010)
New Revision: 5023
Added:
trunk/src/arch/i386/include/arch/ioapic.h
Modified:
trunk/src/arch/i386/Config.lb
trunk/src/arch/i386/include/arch/acpi.h
trunk/src/arch/i386/smp/Config.lb
trunk/src/arch/i386/smp/Makefile.inc
trunk/src/arch/i386/smp/ioapic.c
trunk/src/mainboard/asi/mb_5blmp/Options.lb
trunk/src/mainboard/bcom/winnetp680/Options.lb
trunk/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
trunk/src/mainboard/jetway/j7f24/Options.lb
trunk/src/mainboard/via/epia-cn/Options.lb
trunk/src/mainboard/via/pc2500e/Options.lb
trunk/src/northbridge/via/cx700/cx700_lpc.c
trunk/src/southbridge/amd/amd8111/amd8111_lpc.c
trunk/src/southbridge/amd/sb600/sb600_sm.c
trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
trunk/src/southbridge/intel/esb6300/esb6300_pic.c
trunk/src/southbridge/intel/i3100/i3100_lpc.c
trunk/src/southbridge/intel/i82801er/i82801er_lpc.c
trunk/src/southbridge/intel/pxhd/pxhd_bridge.c
trunk/src/southbridge/nvidia/ck804/ck804_lpc.c
trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c
trunk/src/southbridge/sis/sis966/sis966_lpc.c
trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
Log:
coreboot has 13 instances of IOAPIC setup distributed across a lot
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de>
Acked-by: Ronald G. Minnich <rminnich(a)gmail.com>
Modified: trunk/src/arch/i386/Config.lb
===================================================================
--- trunk/src/arch/i386/Config.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/arch/i386/Config.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -70,6 +70,4 @@
dir lib
dir boot
-if CONFIG_SMP
- dir smp
-end
+dir smp
Modified: trunk/src/arch/i386/include/arch/acpi.h
===================================================================
--- trunk/src/arch/i386/include/arch/acpi.h 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/arch/i386/include/arch/acpi.h 2010-01-16 18:31:34 UTC (rev 5023)
@@ -425,8 +425,6 @@
gsi_base+=4; \
} while(0);
-#define IO_APIC_ADDR 0xfec00000UL
-
#else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start)
Added: trunk/src/arch/i386/include/arch/ioapic.h
===================================================================
--- trunk/src/arch/i386/include/arch/ioapic.h (rev 0)
+++ trunk/src/arch/i386/include/arch/ioapic.h 2010-01-16 18:31:34 UTC (rev 5023)
@@ -0,0 +1,46 @@
+/*
+ * coreboot IOAPIC support
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __I386_ARCH_IOAPIC_H
+#define __I386_ARCH_IOAPIC_H
+
+#define IO_APIC_ADDR 0xfec00000UL
+#define IO_APIC_INTERRUPTS 24
+
+#define ALL (0xff << 24)
+#define NONE (0)
+#define DISABLED (1 << 16)
+#define ENABLED (0 << 16)
+#define TRIGGER_EDGE (0 << 15)
+#define TRIGGER_LEVEL (1 << 15)
+#define POLARITY_HIGH (0 << 13)
+#define POLARITY_LOW (1 << 13)
+#define PHYSICAL_DEST (0 << 11)
+#define LOGICAL_DEST (1 << 11)
+#define ExtINT (7 << 8)
+#define NMI (4 << 8)
+#define SMI (2 << 8)
+#define INT (1 << 8)
+
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
+void clear_ioapic(u32 ioapic_base);
+
+#endif
Modified: trunk/src/arch/i386/smp/Config.lb
===================================================================
--- trunk/src/arch/i386/smp/Config.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/arch/i386/smp/Config.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -1,8 +1,10 @@
uses CONFIG_GENERATE_MP_TABLE
+uses CONFIG_IOAPIC
if CONFIG_GENERATE_MP_TABLE
object mpspec.o
end
-#object ioapic.o CONFIG_IOAPIC
+if CONFIG_IOAPIC
+ object ioapic.o
+end
-
Modified: trunk/src/arch/i386/smp/Makefile.inc
===================================================================
--- trunk/src/arch/i386/smp/Makefile.inc 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/arch/i386/smp/Makefile.inc 2010-01-16 18:31:34 UTC (rev 5023)
@@ -1,4 +1,3 @@
obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o
-# what about this: how awkward.
-#object ioapic.o CONFIG_IOAPIC
+obj-$(CONFIG_IOAPIC) += ioapic.o
Modified: trunk/src/arch/i386/smp/ioapic.c
===================================================================
--- trunk/src/arch/i386/smp/ioapic.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/arch/i386/smp/ioapic.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -1,85 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/ioapic.h>
#include <console/console.h>
-#include <arch/ioapic.h>
+#include <cpu/x86/lapic.h>
-/* we have to do more than we thought. I assumed Linux would do all the
- * interesting parts, and I was wrong.
- */
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* mask, trigger, polarity, destination, delivery, vector */
- {0x00, DISABLED, NONE},
- {0x01, DISABLED, NONE},
- {0x02, DISABLED, NONE},
- {0x03, DISABLED, NONE},
- {0x04, DISABLED, NONE},
- {0x05, DISABLED, NONE},
- {0x06, DISABLED, NONE},
- {0x07, DISABLED, NONE},
- {0x08, DISABLED, NONE},
- {0x09, DISABLED, NONE},
- {0x0a, DISABLED, NONE},
- {0x0b, DISABLED, NONE},
- {0x0c, DISABLED, NONE},
- {0x0d, DISABLED, NONE},
- {0x0e, DISABLED, NONE},
- {0x0f, DISABLED, NONE},
- {0x10, DISABLED, NONE},
- {0x11, DISABLED, NONE},
- {0x12, DISABLED, NONE},
- {0x13, DISABLED, NONE},
- {0x14, DISABLED, NONE},
- {0x14, DISABLED, NONE},
- {0x15, DISABLED, NONE},
- {0x16, DISABLED, NONE},
- {0x17, DISABLED, NONE},
-};
+static u32 io_apic_read(u32 ioapic_base, u32 reg)
+{
+ write32(ioapic_base, reg);
+ return read32(ioapic_base + 0x10);
+}
-void setup_ioapic(void)
+static void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapicaddr = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
+ write32(ioapic_base, reg);
+ write32(ioapic_base + 0x10, value);
+}
- l = (unsigned long *) ioapicaddr;
-#if defined(i786)
- /* For the pentium 4 and above apic deliver their interrupts
+
+void clear_ioapic(u32 ioapic_base)
+{
+ u32 low, high;
+ u32 i, ioapic_interrupts;
+
+ printk_debug("IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
+
+ /* Read the available number of interrupts */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ if (!ioapic_interrupts || ioapic_interrupts == 0xff)
+ ioapic_interrupts = 24;
+ printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts);
+
+ low = DISABLED;
+ high = NONE;
+
+ for (i = 0; i < ioapic_interrupts; i++) {
+ io_apic_write(ioapic_base, i * 2 + 0x10, low);
+ io_apic_write(ioapic_base, i * 2 + 0x11, high);
+
+ printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ }
+
+ if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
+ printk_warning("IO APIC not responding.\n");
+ return;
+ }
+}
+
+void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
+{
+ u32 bsp_lapicid = lapicid();
+ u32 low, high;
+ u32 i, ioapic_interrupts;
+
+ printk_debug("IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base);
+ printk_debug("IOAPIC: Bootstrap Processor Local APIC = %02x\n",
+ bsp_lapicid);
+
+ if (ioapic_id) {
+ printk_debug("IOAPIC: ID = 0x%02x\n", ioapic_id);
+ /* Set IOAPIC ID if it has been specified */
+ io_apic_write(ioapic_base, 0x00,
+ (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) |
+ (ioapic_id << 24));
+ }
+
+ /* Read the available number of interrupts */
+ ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff;
+ if (!ioapic_interrupts || ioapic_interrupts == 0xff)
+ ioapic_interrupts = 24;
+ printk_debug("IOAPIC: %d interrupts\n", ioapic_interrupts);
+
+
+// XXX this decision should probably be made elsewhere, and
+// it's the C3, not the EPIA this depends on.
+#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
+#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+#else
+#define IOAPIC_INTERRUPTS_ON_FSB
+#endif
+
+#ifdef IOAPIC_INTERRUPTS_ON_FSB
+ /* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
*/
- l[0] = 0x03;
- l[4] = 1;
-#endif /* i786 */
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
+ printk_debug("IOAPIC: Enabling interrupts on FSB\n");
+ io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0));
+#endif
+#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+ printk_debug("IOAPIC: Enabling interrupts on APIC serial bus\n");
+ io_apic_write(ioapic_base, 0x03, 0);
+#endif
+
+ /* Enable Virtual Wire Mode */
+ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
+ high = bsp_lapicid << (56 - 32);
+
+ io_apic_write(ioapic_base, 0x10, low);
+ io_apic_write(ioapic_base, 0x11, high);
+
+ if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
+ printk_warning("IO APIC not responding.\n");
+ return;
}
+
+ printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
+
+ low = DISABLED;
+ high = NONE;
+
+ for (i = 1; i < ioapic_interrupts; i++) {
+ io_apic_write(ioapic_base, i * 2 + 0x10, low);
+ io_apic_write(ioapic_base, i * 2 + 0x11, high);
+
+ printk_spew("IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low);
+ }
}
Modified: trunk/src/mainboard/asi/mb_5blmp/Options.lb
===================================================================
--- trunk/src/mainboard/asi/mb_5blmp/Options.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/mainboard/asi/mb_5blmp/Options.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -1,4 +1,5 @@
uses CONFIG_GENERATE_PIRQ_TABLE
+uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
@@ -70,6 +71,7 @@
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=5
default CONFIG_PIRQ_ROUTE=1
+default CONFIG_GENERATE_MP_TABLE=0
##
## Build code to export a CMOS option table
Modified: trunk/src/mainboard/bcom/winnetp680/Options.lb
===================================================================
--- trunk/src/mainboard/bcom/winnetp680/Options.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/mainboard/bcom/winnetp680/Options.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -62,10 +62,12 @@
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_VIDEO_MB
+uses CONFIG_SMP
uses CONFIG_IOAPIC
default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 0
+default CONFIG_SMP = 1
+default CONFIG_IOAPIC = 1
default CONFIG_VIDEO_MB = 32
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
===================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -181,7 +181,7 @@
## Build code for SMP support
## Only worry about 2 micro processors
##
-default CONFIG_SMP=0
+default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=1
default CONFIG_LOGICAL_CPUS=1
Modified: trunk/src/mainboard/jetway/j7f24/Options.lb
===================================================================
--- trunk/src/mainboard/jetway/j7f24/Options.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/mainboard/jetway/j7f24/Options.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -66,7 +66,7 @@
uses CONFIG_IOAPIC
default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 0
+default CONFIG_IOAPIC = 1
default CONFIG_VIDEO_MB = 32
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
Modified: trunk/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/src/mainboard/via/epia-cn/Options.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/mainboard/via/epia-cn/Options.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -68,7 +68,7 @@
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_IOAPIC = 0
+default CONFIG_IOAPIC = 1
default CONFIG_VIDEO_MB = 32
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
Modified: trunk/src/mainboard/via/pc2500e/Options.lb
===================================================================
--- trunk/src/mainboard/via/pc2500e/Options.lb 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/mainboard/via/pc2500e/Options.lb 2010-01-16 18:31:34 UTC (rev 5023)
@@ -71,7 +71,7 @@
default CONFIG_ROM_SIZE = 512 * 1024
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_IOAPIC = 0
+default CONFIG_IOAPIC = 1
default CONFIG_VIDEO_MB = 32
default CONFIG_CONSOLE_SERIAL8250 = 1
default CONFIG_PCI_ROM_RUN = 0
Modified: trunk/src/northbridge/via/cx700/cx700_lpc.c
===================================================================
--- trunk/src/northbridge/via/cx700/cx700_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/northbridge/via/cx700/cx700_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -31,103 +31,12 @@
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
#include <stdlib.h>
#define ACPI_IO_BASE 0x400
#define HPET_ADDR 0xfe800000UL
-#define IOAPIC_ADDR 0xfec00000ULL
-#if CONFIG_IOAPIC
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
-};
-
-static void setup_ioapic(void)
-{
- int i;
- unsigned long value_low, value_high, val;
- unsigned long ioapic_base = IOAPIC_ADDR;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
- unsigned long bsp_lapicid = lapicid();
-
- l = (unsigned long *)ioapic_base;
-
- /* Set APIC ADDR */
- l[0] = 0;
- val = l[4];
- l[4] = (val & 0xF0FFFF) | (2 << 24); // 2 == ID as programmed elsewhere. should be a define? XXX
-
- /* Set APIC to FSB message bus. */
- l[0] = 0x3;
- val = l[4];
- l[4] = (val & 0xFFFFFE) | 1;
-
- ioapicregvalues[0].value_high = bsp_lapicid << (56 - 32);
-
- printk_debug("IOAPIC: Bootstrap Processor Local APIC ID = %02x\n", bsp_lapicid);
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg * 2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IOAPIC is not responding.\n");
- return;
- }
- printk_debug("IOAPIC: IRQ reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-#endif
-
static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
@@ -369,7 +278,8 @@
cx700_set_lpc_registers(dev);
#if CONFIG_IOAPIC
- setup_ioapic();
+#define IO_APIC_ID 2
+ setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
#endif
/* Initialize interrupts */
Modified: trunk/src/southbridge/amd/amd8111/amd8111_lpc.c
===================================================================
--- trunk/src/southbridge/amd/amd8111/amd8111_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/amd/amd8111/amd8111_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -10,91 +10,12 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
#include <stdlib.h>
#include "amd8111.h"
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(void)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
- unsigned long bsp_apicid = lapicid();
-
- l = (unsigned long *) ioapic_base;
-
- ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
- printk_debug("amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid);
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
@@ -114,7 +35,8 @@
byte = pci_read_config8(dev, 0x4B);
byte |= 1;
pci_write_config8(dev, 0x4B, byte);
- setup_ioapic();
+ /* Don't rename IO APIC */
+ setup_ioapic(IO_APIC_ADDR, 0);
/* posted memory write enable */
byte = pci_read_config8(dev, 0x46);
Modified: trunk/src/southbridge/amd/sb600/sb600_sm.c
===================================================================
--- trunk/src/southbridge/amd/sb600/sb600_sm.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/amd/sb600/sb600_sm.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -27,6 +27,7 @@
#include <bitops.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
+#include <arch/ioapic.h>
#include <stdlib.h>
#include "sb600.h"
#include "sb600_smbus.c"
@@ -40,83 +41,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-struct ioapicreg {
- u32 reg;
- u32 value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, DISABLED, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(u32 ioapic_base)
-{
- int i;
- u32 value_low, value_high;
- volatile u32 *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid() << (56 - 32);
-
- printk_debug("lapicid = %016x\n", ioapicregvalues[0].value_high);
-
- l = (u32 *)ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg * 2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
-}
-
/*
* SB600 enables all USB controllers by default in SMBUS Control.
* SB600 enables SATA by default in SMBUS Control.
@@ -133,7 +57,8 @@
printk_info("sm_init().\n");
ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
- setup_ioapic(ioapic_base);
+ /* Don't rename APIC ID */
+ setup_ioapic(ioapic_base, 0);
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
Modified: trunk/src/southbridge/intel/esb6300/esb6300_lpc.c
===================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/intel/esb6300/esb6300_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "esb6300.h"
#define ACPI_BAR 0x40
@@ -22,52 +23,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%d IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-
- /* Put the ioapic in virtual wire mode */
- l[0] = 0 + 0x10;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
#define SERIRQ_CNTL 0x64
static void esb6300_enable_serial_irqs(device_t dev)
{
@@ -287,7 +242,7 @@
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(dev);
+ setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
Modified: trunk/src/southbridge/intel/esb6300/esb6300_pic.c
===================================================================
--- trunk/src/southbridge/intel/esb6300/esb6300_pic.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/intel/esb6300/esb6300_pic.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -6,50 +6,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <arch/ioapic.h>
#include "esb6300.h"
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec10000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%s IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-}
-
static void pic_init(struct device *dev)
{
@@ -64,7 +23,7 @@
pci_write_config8(dev, 0x3c, 0xff);
/* Setup the ioapic */
- setup_ioapic(dev);
+ clear_ioapic(0xfec10000);
}
static void pic_read_resources(device_t dev)
Modified: trunk/src/southbridge/intel/i3100/i3100_lpc.c
===================================================================
--- trunk/src/southbridge/intel/i3100/i3100_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/intel/i3100/i3100_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -29,6 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i3100.h"
#define ACPI_BAR 0x40
@@ -49,60 +50,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- u32 value_low, value_high;
- u32 ioapic_base = 0xfec00000;
- volatile u32 *l;
- u32 interrupts;
- struct resource *res;
-
- /* Enable IO APIC */
- res = find_resource(dev, RCBA);
- if (!res) {
- return;
- }
- *((u8 *)(res->base + 0x31ff)) |= (1 << 0);
-
- l = (u32 *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("%d IO APIC not responding.\n",
- dev_path(dev));
- return;
- }
- }
-
- /* Put the APIC in virtual wire mode */
- l[0] = 0x12;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
static void i3100_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
@@ -363,8 +310,20 @@
static void lpc_init(struct device *dev)
{
- setup_ioapic(dev);
+ struct resource *res;
+ /* Enable IO APIC */
+ res = find_resource(dev, RCBA);
+ if (!res) {
+ return;
+ }
+ *((u8 *)(res->base + 0x31ff)) |= (1 << 0);
+
+ // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
+ // (register 0x10/0x11) while the old code used int 1 (register 0x12)
+ // ... Why?
+ setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
+
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
pci_write_config32(dev, 0xd0, 0x00000000);
Modified: trunk/src/southbridge/intel/i82801er/i82801er_lpc.c
===================================================================
--- trunk/src/southbridge/intel/i82801er/i82801er_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/intel/i82801er/i82801er_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -9,6 +9,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801er.h"
#define ACPI_BAR 0x40
@@ -22,51 +23,6 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
-static void setup_ioapic(void)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- unsigned interrupts;
-
- l = (unsigned long *) ioapic_base;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
-
- /* Put the ioapic in virtual wire mode */
- l[0] = 0 + 0x10;
- l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
#define SERIRQ_CNTL 0x64
static void i82801er_enable_serial_irqs(device_t dev)
{
@@ -292,7 +248,7 @@
value = pci_read_config32(dev, 0xd4);
value |= (1<<1);
pci_write_config32(dev, 0xd4, value);
- setup_ioapic();
+ setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
i82801er_enable_serial_irqs(dev);
Modified: trunk/src/southbridge/intel/pxhd/pxhd_bridge.c
===================================================================
--- trunk/src/southbridge/intel/pxhd/pxhd_bridge.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/intel/pxhd/pxhd_bridge.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -8,6 +8,7 @@
#include <device/pci_ops.h>
#include <device/pcix.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include <delay.h>
#include "pxhd.h"
@@ -159,63 +160,17 @@
.device = 0x032a,
};
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
-
-static void setup_ioapic(device_t dev)
-{
- int i;
- unsigned long value_low, value_high;
- unsigned long ioapic_base;
- volatile unsigned long *l;
- unsigned interrupts;
-
- ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- l = (unsigned long *) ioapic_base;
-
- /* Enable front side bus delivery */
- l[0] = 0x03;
- l[4] = 1;
-
- l[0] = 0x01;
- interrupts = (l[04] >> 16) & 0xff;
- for (i = 0; i < interrupts; i++) {
- l[0] = (i * 2) + 0x10;
- l[4] = DISABLED;
- value_low = l[4];
- l[0] = (i * 2) + 0x11;
- l[4] = NONE; /* Should this be an address? */
- value_high = l[4];
- if (value_low == 0xffffffff) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
-}
-
static void ioapic_init(device_t dev)
{
- uint32_t value;
+ uint32_t value, ioapic_base;
/* Enable bus mastering so IOAPICs work */
value = pci_read_config16(dev, PCI_COMMAND);
value |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, value);
- setup_ioapic(dev);
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+ setup_ioapic(ioapic_base, 0); // Don't rename IOAPIC ID
}
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
Modified: trunk/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- trunk/src/southbridge/nvidia/ck804/ck804_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/nvidia/ck804/ck804_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -15,6 +15,7 @@
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "ck804.h"
@@ -23,83 +24,6 @@
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base)
-{
- int i;
- unsigned long value_low, value_high;
- /* unsigned long ioapic_base = 0xfec00000; */
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid() << (56 - 32);
-
- l = (unsigned long *)ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg * 2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i == 0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
@@ -123,7 +47,7 @@
pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
- setup_ioapic(dword);
+ setup_ioapic(dword, 0); // Don't rename IOAPIC ID
#if 1
dword = pci_read_config32(dev, 0xe4);
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -33,97 +33,13 @@
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "mcp55.h"
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base, int master)
-{
- int i;
- unsigned long value_low, value_high;
-// unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- if (master) {
- ioapicregvalues[0].value_high = lapicid()<<(56-32);
- ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
- }
- else {
- ioapicregvalues[0].value_high = NONE;
- ioapicregvalues[0].value_low = DISABLED;
- }
-
- l = (unsigned long *) ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
@@ -139,15 +55,18 @@
static void lpc_common_init(device_t dev, int master)
{
uint8_t byte;
- uint32_t dword;
+ uint32_t ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
- setup_ioapic(dword, master);
+ if (master)
+ setup_ioapic(ioapic_base, 0);
+ else
+ clear_ioapic(ioapic_base);
}
static void lpc_slave_init(device_t dev)
Modified: trunk/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- trunk/src/southbridge/sis/sis966/sis966_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/sis/sis966/sis966_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -35,6 +35,7 @@
#include <pc80/isa-dma.h>
#include <bitops.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include "sis966.h"
@@ -42,84 +43,6 @@
#define NMI_OFF 0
-struct ioapicreg {
- unsigned int reg;
- unsigned int value_low, value_high;
-};
-
-static struct ioapicreg ioapicregvalues[] = {
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
- /* IO-APIC virtual wire mode configuration */
- /* mask, trigger, polarity, destination, delivery, vector */
- { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
- { 1, DISABLED, NONE},
- { 2, DISABLED, NONE},
- { 3, DISABLED, NONE},
- { 4, DISABLED, NONE},
- { 5, DISABLED, NONE},
- { 6, DISABLED, NONE},
- { 7, DISABLED, NONE},
- { 8, DISABLED, NONE},
- { 9, DISABLED, NONE},
- { 10, DISABLED, NONE},
- { 11, DISABLED, NONE},
- { 12, DISABLED, NONE},
- { 13, DISABLED, NONE},
- { 14, DISABLED, NONE},
- { 15, DISABLED, NONE},
- { 16, DISABLED, NONE},
- { 17, DISABLED, NONE},
- { 18, DISABLED, NONE},
- { 19, DISABLED, NONE},
- { 20, DISABLED, NONE},
- { 21, DISABLED, NONE},
- { 22, DISABLED, NONE},
- { 23, DISABLED, NONE},
- /* Be careful and don't write past the end... */
-};
-
-static void setup_ioapic(unsigned long ioapic_base)
-{
- int i;
- unsigned long value_low, value_high;
-// unsigned long ioapic_base = 0xfec00000;
- volatile unsigned long *l;
- struct ioapicreg *a = ioapicregvalues;
-
- ioapicregvalues[0].value_high = lapicid()<<(56-32);
-
- l = (unsigned long *) ioapic_base;
-
- for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
- i++, a++) {
- l[0] = (a->reg * 2) + 0x10;
- l[4] = a->value_low;
- value_low = l[4];
- l[0] = (a->reg *2) + 0x11;
- l[4] = a->value_high;
- value_high = l[4];
- if ((i==0) && (value_low == 0xffffffff)) {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
- a->reg, a->value_low, a->value_high);
- }
-}
-
// 0x7a or e3
#define PREVIOUS_POWER_STATE 0x7A
@@ -135,16 +58,15 @@
static void lpc_common_init(device_t dev)
{
uint8_t byte;
- uint32_t dword;
+ uint32_t ioapic_base;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
- dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
- setup_ioapic(dword);
-
+ setup_ioapic(ioapic_base, 0); // Don't rename IO APIC ID
}
static void lpc_slave_init(device_t dev)
Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-01-16 17:53:38 UTC (rev 5022)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-01-16 18:31:34 UTC (rev 5023)
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <pc80/keyboard.h>
#include <pc80/i8259.h>
@@ -33,21 +34,6 @@
#include "vt8237r.h"
#include "chip.h"
-#define ALL (0xff << 24)
-#define NONE (0)
-#define DISABLED (1 << 16)
-#define ENABLED (0 << 16)
-#define TRIGGER_EDGE (0 << 15)
-#define TRIGGER_LEVEL (1 << 15)
-#define POLARITY_HIGH (0 << 13)
-#define POLARITY_LOW (1 << 13)
-#define PHYSICAL_DEST (0 << 11)
-#define LOGICAL_DEST (1 << 11)
-#define ExtINT (7 << 8)
-#define NMI (4 << 8)
-#define SMI (2 << 8)
-#define INT (1 << 8)
-
extern void dump_south(device_t dev);
static void southbridge_init_common(struct device *dev);
@@ -75,85 +61,6 @@
}
#endif
-static struct ioapicreg {
- u32 reg;
- u32 value_low;
- u32 value_high;
-} ioapic_table[] = {
- /* IO-APIC virtual wire mode configuration. */
- /* mask, trigger, polarity, destination, delivery, vector */
- {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST |
- ExtINT, NONE},
- {1, DISABLED, NONE},
- {2, DISABLED, NONE},
- {3, DISABLED, NONE},
- {4, DISABLED, NONE},
- {5, DISABLED, NONE},
- {6, DISABLED, NONE},
- {7, DISABLED, NONE},
- {8, DISABLED, NONE},
- {9, DISABLED, NONE},
- {10, DISABLED, NONE},
- {11, DISABLED, NONE},
- {12, DISABLED, NONE},
- {13, DISABLED, NONE},
- {14, DISABLED, NONE},
- {15, DISABLED, NONE},
- {16, DISABLED, NONE},
- {17, DISABLED, NONE},
- {18, DISABLED, NONE},
- {19, DISABLED, NONE},
- {20, DISABLED, NONE},
- {21, DISABLED, NONE},
- {22, DISABLED, NONE},
- {23, DISABLED, NONE},
-};
-
-static void setup_ioapic(u32 ioapic_base)
-{
- u32 value_low, value_high, val;
- volatile u32 *l;
- int i;
-
- /* All delivered to CPU0. */
- ioapic_table[0].value_high = (lapicid()) << (56 - 32);
- l = (u32 *)ioapic_base;
-
-#if CONFIG_EPIA_VT8237R_INIT
- /* Set APIC to APIC Serial bus. */
- l[0] = 0x3;
- l[4] = 0;
-#else
- /* Set APIC to FSB message bus. */
- l[0] = 0x3;
- val = l[4];
- l[4] = (val & 0xFFFFFE) | 1;
-#endif
-
- /* Set APIC ADDR - this will be VT8237R_APIC_ID. */
- l[0] = 0;
- val = l[4];
- l[4] = (val & 0xF0FFFF) | (VT8237R_APIC_ID << 24);
-
- for (i = 0; i < ARRAY_SIZE(ioapic_table); i++) {
- l[0] = (ioapic_table[i].reg * 2) + 0x10;
- l[4] = ioapic_table[i].value_low;
- value_low = l[4];
- l[0] = (ioapic_table[i].reg * 2) + 0x11;
- l[4] = ioapic_table[i].value_high;
- if (i == 0) {
- l[0] = (ioapic_table[i].reg * 2) + 0x10;
- value_low = l[4];
- if (value_low == 0xffffffff)
- {
- printk_warning("IO APIC not responding.\n");
- return;
- }
- }
- }
-}
-
-
/** Set up PCI IRQ routing, route everything through APIC. */
static void pci_routing_fixup(struct device *dev)
{
@@ -622,7 +529,7 @@
{
vt8237_common_init(dev);
pci_routing_fixup(dev);
- setup_ioapic(VT8237R_APIC_BASE);
+ setup_ioapic(VT8237R_APIC_BASE, VT8237R_APIC_ID);
setup_i8259();
init_keyboard(dev);
}
1
0