coreboot January 2010

coreboot@coreboot.org

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[commit] r5035 - trunk/src/mainboard/tyan/s2912_fam10
by svn＠coreboot.org 18 Jan '10

18 Jan '10

Author: stepan Date: 2010-01-18 12:09:24 +0100 (Mon, 18 Jan 2010) New Revision: 5035 Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig Log: get rid of Kconfig warning. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig 2010-01-17 21:59:27 UTC (rev 5034) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig 2010-01-18 11:09:24 UTC (rev 5035) @@ -154,8 +154,8 @@ depends on BOARD_TYAN_S2912_FAM10 config ACPI_SSDTX_NUM - hex - default 0x1f + int + default 31 depends on BOARD_TYAN_S2912_FAM10 config RAMBASE

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[PATCH] [3/7] Roda RK886EX support: SMSC LPC47N227
by Stefan Reinauer 18 Jan '10

18 Jan '10

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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KBuild Report [r5034]
by coresystems autobuild service 18 Jan '10

18 Jan '10

[1/117] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/117] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/117] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/117] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/117] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/117] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/117] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/117] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/117] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/117] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/117] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/117] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/117] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/117] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/117] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/117] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/117] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/117] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/117] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/117] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/117] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/117] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/117] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/117] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/117] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/117] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/117] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/117] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/117] bcom/winnetp680 fail. [30/117] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/117] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/117] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/117] dell/s1850 fail. [34/117] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/117] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/117] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/117] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/117] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/117] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/117] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/117] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/117] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/117] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/117] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/117] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/117] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/117] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/117] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/117] intel/d945gclf fail. [50/117] intel/eagleheights fail. [51/117] intel/jarrell fail. [52/117] intel/mtarvon fail. [53/117] intel/truxton fail. [54/117] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/117] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/117] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/117] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/117] jetway/j7f24 fail. [59/117] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/117] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/117] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/117] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/117] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/117] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/117] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/117] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/117] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/117] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/117] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/117] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/117] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/117] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/117] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/117] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/117] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/117] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/117] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/117] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/117] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/117] roda/rk886ex ok. Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/roda/rk886ex/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x6886 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x4352 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0 [81/117] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/117] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [83/117] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/117] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [85/117] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/117] supermicro/x6dai_g fail. [87/117] supermicro/x6dhe_g fail. [88/117] supermicro/x6dhe_g2 fail. [89/117] supermicro/x6dhr_ig fail. [90/117] supermicro/x6dhr_ig2 fail. [91/117] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [92/117] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [93/117] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [94/117] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [95/117] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/117] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/117] tyan/s2735 fail. [98/117] tyan/s2850 fail. [99/117] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/117] tyan/s2880 fail. [101/117] tyan/s2881 fail. [102/117] tyan/s2882 fail. [103/117] tyan/s2885 fail. [104/117] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [105/117] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [106/117] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [107/117] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [108/117] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/117] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/117] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [111/117] via/epia-cn fail. [112/117] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [113/117] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [114/117] via/epia-n fail. [115/117] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [116/117] via/pc2500e fail. [117/117] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5034/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

[PATCH] [4/7] Roda RK886EX support: EC Renesas M3885X
by Stefan Reinauer 18 Jan '10

18 Jan '10

3 3

KBuild Report [r5033]
by coresystems autobuild service 18 Jan '10

18 Jan '10

[1/117] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/117] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/117] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/117] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/117] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/117] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/117] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/117] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/117] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/117] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/117] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/117] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/117] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/117] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/117] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/117] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/117] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/117] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/117] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/117] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/117] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/117] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/117] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/117] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/117] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/117] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/117] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/117] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/117] bcom/winnetp680 fail. [30/117] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/117] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/117] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/117] dell/s1850 fail. [34/117] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/117] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/117] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/117] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/117] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/117] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/117] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/117] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/117] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/117] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/117] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/117] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/117] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/117] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/117] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/117] intel/d945gclf fail. [50/117] intel/eagleheights fail. [51/117] intel/jarrell fail. [52/117] intel/mtarvon fail. [53/117] intel/truxton fail. [54/117] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/117] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/117] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/117] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/117] jetway/j7f24 fail. [59/117] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/117] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/117] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/117] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/117] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/117] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/117] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/117] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/117] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/117] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/117] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/117] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/117] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/117] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/117] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/117] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/117] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/117] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/117] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/117] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/117] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/117] roda/rk886ex ok. Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/roda/rk886ex/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x6886 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x4352 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0 [81/117] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/117] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [83/117] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/117] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [85/117] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/117] supermicro/x6dai_g fail. [87/117] supermicro/x6dhe_g fail. [88/117] supermicro/x6dhe_g2 fail. [89/117] supermicro/x6dhr_ig fail. [90/117] supermicro/x6dhr_ig2 fail. [91/117] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [92/117] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [93/117] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [94/117] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [95/117] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/117] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/117] tyan/s2735 fail. [98/117] tyan/s2850 fail. [99/117] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/117] tyan/s2880 fail. [101/117] tyan/s2881 fail. [102/117] tyan/s2882 fail. [103/117] tyan/s2885 fail. [104/117] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [105/117] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [106/117] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [107/117] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [108/117] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/117] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/117] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [111/117] via/epia-cn fail. [112/117] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [113/117] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [114/117] via/epia-n fail. [115/117] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [116/117] via/pc2500e fail. [117/117] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5033/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

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Re: [coreboot] #15: fix abuild for all boards that use the "three images solution
by coreboot 17 Jan '10

17 Jan '10

#15: fix abuild for all boards that use the "three images solution ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: yhlu Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: wontfix Keywords: abuild | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * status: reopened => closed * resolution: => wontfix Comment: Closing. As of r5000 we are trying to obsolete the "newconfig" build method, and Kconfig is replacing the "3 images solution" with "tinybootblock". -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/15#comment:5> coreboot <http://www.coreboot.org/>

1 0

Re: [coreboot] #12: Make coreboot work on a laptop
by coreboot 17 Jan '10

17 Jan '10

#12: Make coreboot work on a laptop ---------------------------------+------------------------------------------ Reporter: uwe | Owner: stepan Type: task | Status: closed Priority: major | Milestone: Going mainstream Component: coreboot | Resolution: fixed Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * status: assigned => closed * resolution: => fixed Comment: r5031. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/12#comment:5> coreboot <http://www.coreboot.org/>

1 0

KBuild Report [r5032]
by coresystems autobuild service 17 Jan '10

17 Jan '10

[1/117] a-trend/atc-6220 ok. Processing mainboard/a-trend/atc-6220 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [2/117] a-trend/atc-6240 ok. Processing mainboard/a-trend/atc-6240 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [3/117] abit/be6-ii_v2_0 ok. Processing mainboard/abit/be6-ii_v2_0 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [4/117] advantech/pcm-5820 ok. Processing mainboard/advantech/pcm-5820 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [5/117] amd/db800 ok. Processing mainboard/amd/db800 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x4 +CONFIG_IRQ_SLOT_COUNT = 0x6 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [6/117] amd/dbm690t ok. Processing mainboard/amd/dbm690t (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/amd/dbm690t/Config-abuild.lb ok Creating builddir...ok -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 [7/117] amd/norwich ok. Processing mainboard/amd/norwich (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [8/117] amd/pistachio ok. Processing mainboard/amd/pistachio (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/amd/pistachio/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [9/117] amd/rumba ok. Processing mainboard/amd/rumba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [10/117] amd/serengeti_cheetah ok. Processing mainboard/amd/serengeti_cheetah (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/amd/serengeti_cheetah/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x1 +CONFIG_ACPI_SSDTX_NUM = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [11/117] amd/serengeti_cheetah_fam10 ok. Processing mainboard/amd/serengeti_cheetah_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [12/117] arima/hdama ok. Processing mainboard/arima/hdama (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/arima/hdama/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [13/117] artecgroup/dbe61 ok. Processing mainboard/artecgroup/dbe61 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [14/117] asi/mb_5blgp ok. Processing mainboard/asi/mb_5blgp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [15/117] asi/mb_5blmp ok. Processing mainboard/asi/mb_5blmp (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [16/117] asus/a8n_e ok. Processing mainboard/asus/a8n_e (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/asus/a8n_e/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [17/117] asus/a8v-e_se ok. Processing mainboard/asus/a8v-e_se (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_EPIA_VT8237R_INIT = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [18/117] asus/m2v-mx_se ok. Processing mainboard/asus/m2v-mx_se (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/asus/m2v-mx_se/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_EPIA_VT8237R_INIT = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x1f00000 +CONFIG_RAMBASE = 0x100000 -CONFIG_RAMTOP = 0x2000000 +CONFIG_RAMTOP = 0x200000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [19/117] asus/mew-am ok. Processing mainboard/asus/mew-am (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [20/117] asus/mew-vm ok. Processing mainboard/asus/mew-vm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [21/117] asus/p2b-d ok. Processing mainboard/asus/p2b-d (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [22/117] asus/p2b-ds ok. Processing mainboard/asus/p2b-ds (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_AGP_APERTURE_SIZE = 0x4000000 -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_ADDR_BITS = 0x24 +CONFIG_CPU_ADDR_BITS = 0x28 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc0000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_ID_SECTION_OFFSET = 0x10 +CONFIG_ID_SECTION_OFFSET = 0x80 -CONFIG_IRQ_SLOT_COUNT = 0x7 +CONFIG_IRQ_SLOT_COUNT = 0xd -CONFIG_LB_CKS_LOC = 0x7e +CONFIG_LB_CKS_LOC = 0x7b -CONFIG_LB_CKS_RANGE_END = 0x7d +CONFIG_LB_CKS_RANGE_END = 0x7a -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x0 +CONFIG_MEM_TRAIN_SEQ = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x40000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_USE_DCACHE_RAM = 0x0 +CONFIG_USE_DCACHE_RAM = 0x1 -CONFIG_USE_PRINTK_IN_CAR = 0x0 +CONFIG_USE_PRINTK_IN_CAR = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [23/117] asus/p2b-f ok. Processing mainboard/asus/p2b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [24/117] asus/p2b ok. Processing mainboard/asus/p2b (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [25/117] asus/p3b-f ok. Processing mainboard/asus/p3b-f (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [26/117] axus/tc320 ok. Processing mainboard/axus/tc320 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [27/117] azza/pt-6ibd ok. Processing mainboard/azza/pt-6ibd (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [28/117] bcom/winnet100 ok. Processing mainboard/bcom/winnet100 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [29/117] bcom/winnetp680 fail. [30/117] biostar/m6tba ok. Processing mainboard/biostar/m6tba (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [31/117] broadcom/blast ok. Processing mainboard/broadcom/blast (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [32/117] compaq/deskpro_en_sff_p600 ok. Processing mainboard/compaq/deskpro_en_sff_p600 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [33/117] dell/s1850 fail. [34/117] digitallogic/adl855pc ok. Processing mainboard/digitallogic/adl855pc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SMP = 0x0 +CONFIG_SMP = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [35/117] digitallogic/msm586seg ok. Processing mainboard/digitallogic/msm586seg (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/digitallogic/msm586seg/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [36/117] digitallogic/msm800sev ok. Processing mainboard/digitallogic/msm800sev (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0x7 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [37/117] eaglelion/5bcm ok. Processing mainboard/eaglelion/5bcm (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [38/117] emulation/qemu-x86 ok. Processing mainboard/emulation/qemu-x86 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/emulation/qemu-x86/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_EMULATION_QEMU_X86 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0x8f000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [39/117] gigabyte/ga-6bxc ok. Processing mainboard/gigabyte/ga-6bxc (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x6 +CONFIG_IRQ_SLOT_COUNT = 0x5 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [40/117] gigabyte/ga_2761gxdk ok. Processing mainboard/gigabyte/ga_2761gxdk (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/gigabyte/ga_2761gxdk/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [41/117] gigabyte/m57sli ok. Processing mainboard/gigabyte/m57sli (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/gigabyte/m57sli/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL = 0x1 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [42/117] hp/dl145_g3 ok. Processing mainboard/hp/dl145_g3 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [43/117] hp/e_vectra_p2706t ok. Processing mainboard/hp/e_vectra_p2706t (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 [44/117] ibm/e325 ok. Processing mainboard/ibm/e325 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [45/117] ibm/e326 ok. Processing mainboard/ibm/e326 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/ibm/e326/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [46/117] iei/juki-511p ok. Processing mainboard/iei/juki-511p (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/iei/juki-511p/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [47/117] iei/nova4899r ok. Processing mainboard/iei/nova4899r (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_GX1_VIDEO = 0x1 +CONFIG_GX1_VIDEOMODE = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 +CONFIG_SPLASH_GRAPHIC = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [48/117] iei/pcisa-lx-800-r10 ok. Processing mainboard/iei/pcisa-lx-800-r10 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_UDELAY_IO = 0x1 +CONFIG_UDELAY_IO = 0x0 -CONFIG_UDELAY_TSC = 0x0 +CONFIG_UDELAY_TSC = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [49/117] intel/d945gclf fail. [50/117] intel/eagleheights fail. [51/117] intel/jarrell fail. [52/117] intel/mtarvon fail. [53/117] intel/truxton fail. [54/117] intel/xe7501devkit ok. Processing mainboard/intel/xe7501devkit (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MOVNTI = 0x1 +CONFIG_HAVE_MOVNTI = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_MMX = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [55/117] iwill/dk8_htx ok. Processing mainboard/iwill/dk8_htx (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/iwill/dk8_htx/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xc4000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_SIZE = 0xc000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HW_MEM_HOLE_SIZEK = 0x80000 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [56/117] iwill/dk8s2 ok. Processing mainboard/iwill/dk8s2 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_ATI_RAGE_XL = 0x1 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0xc +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [57/117] iwill/dk8x ok. Processing mainboard/iwill/dk8x (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAX_CPUS = 0x2 +CONFIG_MAX_CPUS = 0x4 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [58/117] jetway/j7f24 fail. [59/117] kontron/986lcd-m ok. Processing mainboard/kontron/986lcd-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/kontron/986lcd-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 [60/117] kontron/kt690 ok. Processing mainboard/kontron/kt690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/kontron/kt690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [61/117] lippert/frontrunner ok. Processing mainboard/lippert/frontrunner (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [62/117] lippert/roadrunner-lx ok. Processing mainboard/lippert/roadrunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [63/117] lippert/spacerunner-lx ok. Processing mainboard/lippert/spacerunner-lx (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 -CONFIG_DEBUG = 0x1 +CONFIG_DEBUG = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [64/117] mitac/6513wu ok. Processing mainboard/mitac/6513wu (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [65/117] msi/ms6119 ok. Processing mainboard/msi/ms6119 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [66/117] msi/ms6147 ok. Processing mainboard/msi/ms6147 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [67/117] msi/ms6156 ok. Processing mainboard/msi/ms6156 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [68/117] msi/ms6178 ok. Processing mainboard/msi/ms6178 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [69/117] msi/ms7135 ok. Processing mainboard/msi/ms7135 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/msi/ms7135/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_DCACHE_RAM_BASE = 0xc8000 +CONFIG_DCACHE_RAM_BASE = 0xcf000 -CONFIG_DCACHE_RAM_SIZE = 0x8000 +CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [70/117] msi/ms7260 ok. Processing mainboard/msi/ms7260 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/msi/ms7260/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MEM_TRAIN_SEQ = 0x2 +CONFIG_MEM_TRAIN_SEQ = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [71/117] msi/ms9185 ok. Processing mainboard/msi/ms9185 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/msi/ms9185/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x8 +CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x6 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1022 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1462 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [72/117] msi/ms9282 ok. Processing mainboard/msi/ms9282 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/msi/ms9282/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HW_MEM_HOLE_SIZEK = 0x0 +CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [73/117] nec/powermate2000 ok. Processing mainboard/nec/powermate2000 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I810_VIDEO_MB_1MB = 0x1 +CONFIG_I810_VIDEO_MB_512KB = 0x0 +CONFIG_I810_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [74/117] newisys/khepri ok. Processing mainboard/newisys/khepri (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x9 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [75/117] nvidia/l1_2pvv ok. Processing mainboard/nvidia/l1_2pvv (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/nvidia/l1_2pvv/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [76/117] olpc/btest ok. Processing mainboard/olpc/btest (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [77/117] olpc/rev_a ok. Processing mainboard/olpc/rev_a (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [78/117] pcengines/alix1c ok. Processing mainboard/pcengines/alix1c (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_LX = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [79/117] rca/rm4100 ok. Processing mainboard/rca/rm4100 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/rca/rm4100/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [80/117] roda/rk886ex ok. Processing mainboard/roda/rk886ex (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/roda/rk886ex/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_INTEL_CORE = 0x1 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 -CONFIG_HAVE_ACPI_RESUME = 0x1 +CONFIG_HAVE_ACPI_RESUME = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x6886 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x4352 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES = 0x0 [81/117] soyo/sy-6ba-plus-iii ok. Processing mainboard/soyo/sy-6ba-plus-iii (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [82/117] sunw/ultra40 ok. Processing mainboard/sunw/ultra40 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [83/117] supermicro/h8dme ok. Processing mainboard/supermicro/h8dme (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/supermicro/h8dme/Config-abuild.lb ok Creating builddir...ok -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_LOW_TABLES = 0x0 +CONFIG_HAVE_LOW_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [84/117] supermicro/h8dmr ok. Processing mainboard/supermicro/h8dmr (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/supermicro/h8dmr/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_ROM_SIZE = 0x100000 +CONFIG_ROM_SIZE = 0x80000 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [85/117] supermicro/h8dmr_fam10 ok. Processing mainboard/supermicro/h8dmr_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/supermicro/h8dmr_fam10/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1511 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x0 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x15d9 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [86/117] supermicro/x6dai_g fail. [87/117] supermicro/x6dhe_g fail. [88/117] supermicro/x6dhe_g2 fail. [89/117] supermicro/x6dhr_ig fail. [90/117] supermicro/x6dhr_ig2 fail. [91/117] technexion/tim5690 ok. Processing mainboard/technexion/tim5690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/technexion/tim5690/Config-abuild.lb ok Creating builddir...ok +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 [92/117] technexion/tim8690 ok. Processing mainboard/technexion/tim8690 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/technexion/tim8690/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x8 -CONFIG_GFXUMA = 0x1 +CONFIG_GFXUMA = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_MAINBOARD_RESOURCES = 0x1 +CONFIG_HAVE_MAINBOARD_RESOURCES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 -CONFIG_HAVE_OPTION_TABLE = 0x0 +CONFIG_HAVE_OPTION_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x6 -CONFIG_HT_CHAIN_UNITID_BASE = 0x0 +CONFIG_HT_CHAIN_UNITID_BASE = 0xa -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x1 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 [93/117] technologic/ts5300 ok. Processing mainboard/technologic/ts5300 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/technologic/ts5300/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_AMD_SC520 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x20000 +CONFIG_ROM_SIZE = 0x40000 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 -CONFIG_TTYS0_BASE = 0x2f8 +CONFIG_TTYS0_BASE = 0x3f8 +CONFIG_UDELAY_LAPIC = 0x0 +CONFIG_UDELAY_TSC = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [94/117] televideo/tc7020 ok. Processing mainboard/televideo/tc7020 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_AMD_GX1 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x6 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x6 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0 [95/117] thomson/ip1000 ok. Processing mainboard/thomson/ip1000 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/thomson/ip1000/Config-abuild.lb ok Creating builddir...ok -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 +CONFIG_I830_VIDEO_MB_1MB = 0x0 +CONFIG_I830_VIDEO_MB_512KB = 0x0 +CONFIG_I830_VIDEO_MB_8MB = 0x1 +CONFIG_I830_VIDEO_MB_OFF = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 +CONFIG_MMX = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [96/117] tyan/s1846 ok. Processing mainboard/tyan/s1846 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_INTEL_SLOT_2 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x0 +CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [97/117] tyan/s2735 fail. [98/117] tyan/s2850 fail. [99/117] tyan/s2875 ok. Processing mainboard/tyan/s2875 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [100/117] tyan/s2880 fail. [101/117] tyan/s2881 fail. [102/117] tyan/s2882 fail. [103/117] tyan/s2885 fail. [104/117] tyan/s2891 ok. Processing mainboard/tyan/s2891 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/tyan/s2891/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 [105/117] tyan/s2892 ok. Processing mainboard/tyan/s2892 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/tyan/s2892/Config-abuild.lb ok Creating builddir...ok -CONFIG_APIC_ID_OFFSET = 0x0 +CONFIG_APIC_ID_OFFSET = 0x10 -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 [106/117] tyan/s2895 ok. Processing mainboard/tyan/s2895 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/tyan/s2895/Config-abuild.lb ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_BASE = 0xcf000 +CONFIG_DCACHE_RAM_BASE = 0xc8000 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DIMM_SUPPORT = 0x108 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x0 +CONFIG_SERIAL_CPU_INIT = 0x1 [107/117] tyan/s2912 ok. Processing mainboard/tyan/s2912 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/tyan/s2912/Config-abuild.lb ok Creating builddir...ok -CONFIG_ACPI_SSDTX_NUM = 0x3 +CONFIG_ACPI_SSDTX_NUM = 0x0 -CONFIG_APIC_ID_OFFSET = 0x10 +CONFIG_APIC_ID_OFFSET = 0x16 -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HEAP_SIZE = 0x8000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_MAX_CPUS = 0x4 +CONFIG_MAX_CPUS = 0x2 -CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_MAX_PHYSICAL_CPUS = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 -CONFIG_WAIT_BEFORE_CPUS_INIT = 0x1 +CONFIG_WAIT_BEFORE_CPUS_INIT = 0x0 [108/117] tyan/s2912_fam10 ok. Processing mainboard/tyan/s2912_fam10 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/tyan/s2912_fam10/Config-abuild.lb ok Creating builddir...ok -CONFIG_HAVE_FALLBACK_BOOT = 0x1 +CONFIG_HAVE_FALLBACK_BOOT = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_SERIAL_CPU_INIT = 0x1 +CONFIG_SERIAL_CPU_INIT = 0x0 -CONFIG_USE_FALLBACK_IMAGE = 0x1 +CONFIG_USE_FALLBACK_IMAGE = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [109/117] tyan/s4880 ok. Processing mainboard/tyan/s4880 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 -CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 -CONFIG_RAMBASE = 0x4000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [110/117] tyan/s4882 ok. Processing mainboard/tyan/s4882 (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok -CONFIG_CPU_SOCKET_TYPE = 0x10 +CONFIG_CPU_SOCKET_TYPE = 0x0 -CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x0 +CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x1000 -CONFIG_DIMM_SUPPORT = 0x108 -CONFIG_ENABLE_APIC_EXT_ID = 0x1 +CONFIG_ENABLE_APIC_EXT_ID = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HT_CHAIN_END_UNITID_BASE = 0x20 +CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 -CONFIG_HT_CHAIN_UNITID_BASE = 0x1 +CONFIG_HT_CHAIN_UNITID_BASE = 0x0 -CONFIG_IRQ_SLOT_COUNT = 0x16 +CONFIG_IRQ_SLOT_COUNT = 0xb -CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x0 +CONFIG_K8_HT_FREQ_1G_SUPPORT = 0x1 -CONFIG_MAX_CPUS = 0x8 +CONFIG_MAX_CPUS = 0x4 -CONFIG_MAX_PHYSICAL_CPUS = 0x4 +CONFIG_MAX_PHYSICAL_CPUS = 0x2 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_RAMBASE = 0x2000 +CONFIG_RAMBASE = 0x100000 -CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x0 +CONFIG_SB_HT_CHAIN_ON_BUS0 = 0x2 -CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x1 +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0x0 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [111/117] via/epia-cn fail. [112/117] via/epia-m ok. Processing mainboard/via/epia-m (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/via/epia-m/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x1 -CONFIG_HAVE_INIT_TIMER = 0x1 +CONFIG_HAVE_INIT_TIMER = 0x0 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_UDELAY_IO = 0x0 +CONFIG_UDELAY_IO = 0x1 -CONFIG_UDELAY_TSC = 0x1 +CONFIG_UDELAY_TSC = 0x0 [113/117] via/epia-m700 ok. Processing mainboard/via/epia-m700 (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/via/epia-m700/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DCACHE_RAM_SIZE = 0x2000 +CONFIG_DCACHE_RAM_SIZE = 0x8000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x9 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_ACPI_TABLES = 0x1 +CONFIG_HAVE_HIGH_TABLES = 0x0 -CONFIG_HEAP_SIZE = 0x5000 +CONFIG_HEAP_SIZE = 0x4000 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x9 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 [114/117] via/epia-n fail. [115/117] via/epia ok. Processing mainboard/via/epia (i386: ok, we're amd64 with a cross compiler) Creating config file... ok Creating builddir...ok +CONFIG_CPU_VIA_C3 = 0x1 -CONFIG_DCACHE_RAM_BASE = 0xc0000 -CONFIG_DCACHE_RAM_SIZE = 0x1000 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x7 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_FALLBACK_SIZE = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_REALMODE = 0x1 +CONFIG_PCI_OPTION_ROM_RUN_X86EMU = 0x0 +CONFIG_PCI_OPTION_ROM_RUN_YABEL = 0x0 -CONFIG_PCI_ROM_RUN = 0x0 +CONFIG_PCI_ROM_RUN = 0x1 -CONFIG_VGA_ROM_RUN = 0x0 +CONFIG_VGA_ROM_RUN = 0x1 [116/117] via/pc2500e fail. [117/117] via/vt8454c ok. Processing mainboard/via/vt8454c (i386: ok, we're amd64 with a cross compiler) Using existing test target /srv/svn/coreboot-extra/tmp/coreboot-v2-5032/targets/via/vt8454c/Config-abuild.lb ok Creating builddir...ok +CONFIG_CPU_VIA_C7 = 0x1 -CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x5 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 0x8 +CONFIG_HAVE_ACPI_TABLES = 0x1 -CONFIG_HAVE_HARD_RESET = 0x1 +CONFIG_HAVE_HARD_RESET = 0x0 +CONFIG_HAVE_HIGH_TABLES = 0x0 +CONFIG_HAVE_MP_TABLE = 0x1 +CONFIG_HAVE_PIRQ_TABLE = 0x1 -CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x1 +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 0x0 -CONFIG_IOAPIC = 0x1 +CONFIG_IOAPIC = 0x0 -CONFIG_LOGICAL_CPUS = 0x0 +CONFIG_LOGICAL_CPUS = 0x1 -CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x0 +CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 -CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x5 +CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 0x8 -CONFIG_ROM_SIZE = 0x80000 +CONFIG_ROM_SIZE = 0x100000 -CONFIG_SMP = 0x1 +CONFIG_SMP = 0x0 -CONFIG_USE_DCACHE_RAM = 0x1 +CONFIG_USE_DCACHE_RAM = 0x0 -CONFIG_WRITE_HIGH_TABLES = 0x1 +CONFIG_WRITE_HIGH_TABLES = 0x0

1 0

[PATCH] typo: s/endpotr/endptr/ (was: [commit] r5032 - trunk/util/msrtool)
by Paul Menzel 17 Jan '10

17 Jan '10

Am Sonntag, den 17.01.2010, 19:33 +0100 schrieb svn(a)coreboot.org: […] > Modified: trunk/util/msrtool/msrutils.c > =================================================================== > --- trunk/util/msrtool/msrutils.c 2010-01-17 14:08:17 UTC (rev 5031) > +++ trunk/util/msrtool/msrutils.c 2010-01-17 18:33:53 UTC (rev 5032) > @@ -193,7 +193,7 @@ > * Parse a hexadecimal string into an MSR value. > * > * Leading 0x or 0X is optional, the string is always parsed as hexadecimal. > - * Any non-hexadecimal character can be used to separate the high 32 bits and > + * Any non-hexadecimal character except ' ' can separate the high 32 bits and > * the low 32 bits. If there is such a separator, high and low values do not > * need to be zero padded. If there is no separator, the last <=8 digits are > * the low 32 bits and any characters before them are the high 32 bits. > @@ -205,15 +205,16 @@ > * @param str The string to parse. The string must be writable but will be > * restored before return. > * @param msr Pointer to the struct msr where the value will be stored. > + * @param endptr If endpotr is not NULL, *endptr will point to after the MSR. s/endpotr/endptr/ […] Please find the diff attached. Trivial! Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> I did not get the messages with your patches over the list. Just Stefan’s replies.

2 1

[commit] r5034 - trunk/util/msrtool
by svn＠coreboot.org 17 Jan '10

17 Jan '10

Author: stuge Date: 2010-01-17 22:59:27 +0100 (Sun, 17 Jan 2010) New Revision: 5034 Modified: trunk/util/msrtool/msrutils.c Log: msrtool: Fix typo Trivial! Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/msrtool/msrutils.c =================================================================== --- trunk/util/msrtool/msrutils.c 2010-01-17 18:34:00 UTC (rev 5033) +++ trunk/util/msrtool/msrutils.c 2010-01-17 21:59:27 UTC (rev 5034) @@ -205,7 +205,7 @@ * @param str The string to parse. The string must be writable but will be * restored before return. * @param msr Pointer to the struct msr where the value will be stored. - * @param endptr If endpotr is not NULL, *endptr will point to after the MSR. + * @param endptr If endptr is not NULL, *endptr will point to after the MSR. * @return 1 on success, 0 on parse failure. msr is unchanged on failure. */ uint8_t str2msr(char *str, struct msr *msr, char **endptr) {

1 0

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coreboot January 2010