coreboot June 2009

coreboot@coreboot.org

84 participants
500 discussions

[superiotool][PATCH] : fix W83977TF CR index value in ACPI LDN v4
by Noone Nowhere 13 Jun '09

13 Jun '09

From: Ioannis Barkas <tripl3fault(a)yahoo.com> and Nikos Barkas <levelwol(a)gmail.com> Index: util/superiotool/winbond.c =================================================================== --- util/superiotool/winbond.c (revision 4355) +++ util/superiotool/winbond.c (working copy) @@ -285,7 +285,7 @@ 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,EOT}}, {0xa, "ACPI", {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0xe0,0xe1, - 0x02,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, + 0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6, 0xf7,0xfe,0xff,EOT}, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, NANA,MISC,RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00, Signed-off-by: Ioannis Barkas <tripl3fault(a)yahoo.com> Signed-off-by: Nikos Barkas <levelwol(a)gmail.com> --- More interesting things will be posted soon... ...but we will need at least one wiki account for sure this time at coreboot.org (we have already contacted Stefan Reinauer and Ronald Minnich for an account but got nothing after 2 e-mails quite some time ago...). The patching procedure is undocumented: How do you receive patches, from svn, from the mailiing list, or by any other means? How do we get an svn account or something similar. If patches are received from the list, why on earth do we need to subscribe to the list in order to contribute? Update: v4 is compared for svn revision 4355 (the only change was the revision number though...)

4 3

flashrom: some cleanup
by Mateusz Murawski 12 Jun '09

12 Jun '09

Hi Some work from http://www.coreboot.org/Easy_projects

2 7

[flashrom] r588 - trunk
by svn＠coreboot.org 12 Jun '09

12 Jun '09

Author: hailfinger Date: 2009-06-12 23:29:36 +0200 (Fri, 12 Jun 2009) New Revision: 588 Modified: trunk/flashchips.c Log: Add bus type and timing info for some flash chips. Signed-off-by: Mateusz Murawski <matowy(a)tlen.pl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-12 14:49:10 UTC (rev 587) +++ trunk/flashchips.c 2009-06-12 21:29:36 UTC (rev 588) @@ -466,7 +466,7 @@ .page_size = 256, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10000, /* 10ms */ .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -482,7 +482,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10000, /* 10 ms */ .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2690,7 +2690,7 @@ .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2706,7 +2706,7 @@ .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_jedec, .read = read_memmapped, @@ -2731,14 +2731,14 @@ { .vendor = "Winbond", .name = "W39V040A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, .model_id = W_39V040A, .total_size = 512, .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2747,14 +2747,14 @@ { .vendor = "Winbond", .name = "W39V040B", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, .model_id = W_39V040B, .total_size = 512, .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2763,7 +2763,7 @@ { .vendor = "Winbond", .name = "W39V040C", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, .model_id = W_39V040C, .total_size = 512, @@ -2779,14 +2779,14 @@ { .vendor = "Winbond", .name = "W39V040FA", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = WINBOND_ID, .model_id = W_39V040FA, .total_size = 512, .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2795,14 +2795,14 @@ { .vendor = "Winbond", .name = "W39V080A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, .model_id = W_39V080A, .total_size = 1024, .page_size = 64*1024, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2827,14 +2827,14 @@ { .vendor = "Winbond", .name = "W49V002A", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, .model_id = W_49V002A, .total_size = 256, .page_size = 128, .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = TIMING_FIXME, + .probe_timing = 10, .erase = erase_chip_jedec, .write = write_49f002, .read = read_memmapped, @@ -2843,7 +2843,7 @@ { .vendor = "Winbond", .name = "W49V002FA", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = WINBOND_ID, .model_id = W_49V002FA, .total_size = 256, @@ -2859,7 +2859,7 @@ { .vendor = "Winbond", .name = "W39V080FA", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = WINBOND_ID, .model_id = W_39V080FA, .total_size = 1024, @@ -2875,7 +2875,7 @@ { .vendor = "Winbond", .name = "W39V080FA (dual mode)", - .bustype = CHIP_BUSTYPE_NONSPI, + .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = WINBOND_ID, .model_id = W_39V080FA_DM, .total_size = 512,

1 0

Found information on i810 ram init
by Joseph Smith 12 Jun '09

12 Jun '09

Hello, I found a doc that explains ram init on the Intel 810 chipset, thought it may be of use to someone. MEMORY DETECTION AND CONFIGURATION This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM configuration. The BIOS communicates with an EEPROM on each DIMM through an I2C-type bus to obtain data on the following DIMM parameters: * Presence * Size * Type * Timing/CAS latency NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM data specific to this system. The BIOS performs memory detection and configuration with the following steps: 1. Set Memory Buffer Strength – The memory controller must be configured for correct buffer drive strength. The BIOS provides this function by reading the number of module banks, ECC enable/disable status, and SDRAM width data from the DIMMs and transferring that data to the memory controller. SPD bytes checked: 5, 11, 13 2. Determine DIMM Presence/Type – The BIOS checks each memory socket for DIMM presence. If present, the DIMM type and CAS latency is determined. SPD bytes checked: 2, 9, 10, 18, 23, 24. Check Sequence: a. SPD byte 2 is read for all slots first. A failed read or returned value of other than 02h (EDO) or 04h (SDRAM) results in the slot marked as empty. If mixed types are detected then only SDRAMs are used (see chapter 3 for details). b. SPD byte 18 is read for maximum CAS latency, followed by reads of bytes 9 and 10 for bus speed compatibility. A DIMM detected as too-slow results in an error. c. If the DIMM can handle the memory bus speed at maximum CAS latency then bytes 23 and 24 are checked to see if the DIMM can work maximum CAS latency minus 1. Once all slots are checked, the greatest CAS latency (2 or 3) is used. A DIMM detected as incompatible will result in a bit in CMOS being set and the Num Lock LED on the keyboard will blink for a short time. Depending on the progress of the BIOS routine a POST message may be displayed before the system locks up. 3. Initialize SDRAM – If SDRAM are installed then each row containing SDRAM will be initialized. This step includes pre-charging all banks, sending a CAS-before-RAS command, sending a Mode-Register-Set-Enable command, reading DIMM location/CAS latency data, and sending a Normal Op command. 4. Memory Sizing – The SPD bytes 3, 4, and 17 are checked for number of row and column addresses and (for SDRAM) the number of internal banks. 5. Memory Timing – For SDRAM, the memory controller requires the RAS pre-charge time and the RAS-to-CAS delay time. SPD bytes checked: 27and 29. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

Re: [coreboot] write/verify bug
by Paul Fox 12 Jun '09

12 Jun '09

[responding to earlier private mail from carl-daniel, when i initially sent the patch directly to him.] carl-daniel wrote: > Hi Paul, > > could you include coreboot(a)coreboot.org in your reply? That will allow > the other developers to chime in. Thanks. > > On 11.06.2009 15:46, Paul Fox wrote: > > given the way the options are parsed, i expected to be able > > to run "flashrom -Ewv myfile.img" and have the chip erased, > > written, and verified in one pass. > > > > Heh. I heard from people who expected first write, then erase. But I > admit your interpretation follows the principle of least surprise. it also matches the behavior of every chip-level programmer i've ever used. > > > > this doesn't currently work, and in fact, will zero the chip > > without telling you, and tell you that the operation succeeded. > > much hilarity ensues. :-) > > > > Ouch. This is a long-standing user interface bug. I'm arguing that > 1. flashrom should auto-verify all operations by default. > 2. read/erase and read/write and probably even erase/write should be > rejected by flashrom because it is not clear in which order the user > wants to run them. well, i'll have to allow as how given the primary usage of flashrom, i.e., re-flashing one's expensive new motherboard, that one might want the option parsing to be as bullet- and idiot-proof as possible. but speaking as someone who programs flash chips for a living (at least, it seems like that sometimes), i'd like to reduce the length of my edit/compile/erase/write/verify/debug/edit cycle as much as possible. i can barely imagine using a programmer in anything but erase/write/verify mode, and i certainly want to invoke them all at once. > > > > because of the else-if at line 767, specifying -E along -w used > > to bypass the file open and read, leaving buf[] empty. the chip > > would then be programmed with nulls. worse, if -v was also used, > > it would verify correctly. > > > > That needs to be fixed. > > > > with this patch (which makes the usage message match the actual > > arg parsing) the above command invocation now works correctly. > > > > for real robustness, the verify step should probably re-read the file, > > in case one of the many worker routines accidentally writes to the > > buffer. but that's a different patch.. > > > > Hm true. Then again, marking the buffer const except in the read-file > routine should be a pretty good protection against buffer writing, > considering that we tell gcc to error out on any warning. not really good enough. the code in the ft2232 programmer currently memcpys the user's write data at least once, maybe twice, before it reaches the programmer. those buffers aren't const, of course. (it might be possible to rewrite so the original data never moves, but i think my point remains.) re-reading the file (or, re-copying from an initial "read-only" buffer) should be pretty cheap. paul =--------------------- paul fox, pgf(a)foxharp.boston.ma.us (arlington, ma, where it's 55.8 degrees)

7 15

Re: [coreboot] Hosed ms-7032, I foolishly flashed the bios with a .700
by Phil Neary 12 Jun '09

12 Jun '09

Thanks for the reply, I used Flashrom as the utility and am quite comfortable using Linux and the command line. I got shot of my virally infected copy of Win98 sometime ago, I have my hard drive with Fedora 9 on my friends PC, it has the Flashrom utility and my backup.bin. It also has the same type of bios chip (PLCC), And its socketed! My bios chip is a PLCC (not socketed unfortunately) and the info on the chip is; Winbond W39V040AP 240515401 415GGAA I've thought about unsoldering the chip but don't really have the proper tools. I could do it though, it will take ages because I'll have to take it real slow so and find something to use to take the heat away from the chip so I don't fry it, but I'm very patient and I think could do it (getting it back on might be a bit more problematic). My thought was to purchase another chip and 'kind of' place it on top of the other chip, but I'm not sure how this would go? I'd hope it would be a little like hot flashing, and the good chip would be recognized by the CPU and I could boot-up. It would then be a case of removing the new chip (making sure the bios is set to cashable first) and refashing with my backup.bin. But I don't know the 'bad' chip could interfere with it booting and cause it not to work. Another thought is this computer has something in the bios about 'booting' 'rom' and 'lan' I haven't fully looked into it yet, but if its what I think it is, its something to do with booting over a network, is it possible to do this with a CPU that has no bios? I'm open and confident in trying all suggestions, and I love to learn. Thank you --- On Thu, 11/6/09, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Subject: Re: [coreboot] Hosed ms-7032, I foolishly flashed the bios with a .700 > To: "Phil Neary" <philneary(a)yahoo.co.uk> > Cc: coreboot(a)coreboot.org > Date: Thursday, 11 June, 2009, 10:20 AM > Hi Phil, > > On 11.06.2009 11:49, Phil Neary wrote: > > Hi all, I'm not really sure how this works, I'm > guessing its a bit similar to a forum, but in lieu of > creating threads and posting posts, you email instead? > > > > Correct. Please make sure to use the "reply to all" button > in your > mailer. That will ensure the individual developers and the > list see your > mails. > > > > [...] I messed up when flashing my bios and flashed it > with A7032VMS.700 instead of a .rom or a .bin. > > > > Which application did you use for reflashing? In theory, > the > A7032VMS.700 may just be a renamed .bin file. > > > > [...] I tried the AMIBOOT.ROM recovery with the .700 > and a few other bios' for my board [...], but they haven't > worked.[...] I was able to get the backup.bin from my hard > drive > > Actually, the backup.bin may be key to reviving your > board. > > > > and tried renaming it AMIBOOT.ROM and saving it to > floppy, but Fedora named it amiboot.rom[...]. Does Amiboot > have to be capitalized? > > > > AFAIK DOS doesn't care about name capitalization. > > > > Is there anything I haven't tried yet? > > > > It all depends on how adventurous you feel. > Can you try to locate the ROM chip on your board and peel > off the > sticker? It might look similar to this: > http://www.coreboot.org/File:Plcc32_chip.jpg and it is > probably in a > socket. Write down all text you see on the chip (not the > sticker) and > mail it to us. Then we can tell you which chips are > compatible and how > to recover. > One way to recover is to hotflash the chip in another board > with > compatible flash bus (sounds complicated, but once we know > the chip > model, we can tell you which boards are compatible). That > would save you > the hassle of buying a new chip. > > > > I can get a replacement chip for a fiver, but before I > do I'd like to find out if that will defiantly work? > > It should work, but it's not guaranteed. Ah yes, and there > is the risk > that your onboard network won't work anymore if you buy a > preflashed > chip because sometimes the old chip stores the MAC address > of your > onboard network card. > > How experienced are you with Linux or *BSD? Our emergency > recovery tools > don't work under Windows (well, very old versions of our > tools work > under Windows). > > Regards, > Carl-Daniel > > -- > http://www.hailfinger.org/ > >

5 10

HP NetServer E 800
by Andrew Morgan 12 Jun '09

12 Jun '09

Hi, I've just joined the list. Coreboot looks quite interesting, although I don't know if I know enough to understand how it works yet. :) I have tried flashrom on my server, to see if it would work, and apparently it doesn't. I was asked on the IRC channel to post on the mailing list so here I am... Attached is the output from running the following commands: 'lspci -tvnn' 'superiotool -deV' 'flashrom -V' The SiI 3112 SATA controller is a plug-in card, as is the gigabit ethernet adaptor. The rest, from what I remember, are on board. I'm pretty sure the SiI 3112 and Symbios SCSI have their own flash ROM, I remember doing updates to them. The NetServer is my main e-mail server so I really don't want to break it (not until I get the e-mail server running as a VM and can move it to another machine!) but if I can help getting the chipset information, etc. I'll try. I also have 4 older 'scrap' machines which I can have a play with. Two of them have very similar, socketed, ROM chips so that looks good. -- Andrew. -+-[0000:05]-+-02.0 D-Link System Inc DGE-528T Gigabit Ethernet Adapter [1186:4300] | +-05.0 LSI Logic / Symbios Logic 53C896/897 [1000:000b] | \-05.1 LSI Logic / Symbios Logic 53C896/897 [1000:000b] \-[0000:00]-+-00.0 Broadcom CNB20LE Host Bridge [1166:0009] +-00.1 Broadcom CNB20LE Host Bridge [1166:0009] +-02.0 Intel Corporation 82557/8/9/0/1 Ethernet Pro 100 [8086:1229] +-04.0 Silicon Image, Inc. SiI 3112 [SATALink/SATARaid] Serial ATA Controller [1095:3112] +-07.0 ATI Technologies Inc Rage XL [1002:4752] +-0f.0 Broadcom OSB4 South Bridge [1166:0200] +-0f.1 Broadcom OSB4 IDE Controller [1166:0211] \-0f.2 Broadcom OSB4/CSB5 OHCI USB Controller [1166:0220] flashrom v0.9.0-r581 No coreboot table found. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... 265M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0x53, id2 0x17, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0x53, id2 0x17, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xff, id2 0xff Probing for Macronix MX29LV040C, 512 KB: probe_29f002: id1 0xff, id2 0xff Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0xff, id2 0xff Probing for SST SST29EE010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0x53, id2 0x17, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020C, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040P, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040FA, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. superiotool r4356 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found

1 0

[PATCH] flashrom: Make packagers happy
by Carl-Daniel Hailfinger 12 Jun '09

12 Jun '09

This patch introduces two new targets which are designed to make the life of packagers easier. In particular, it should no longer be necessary to patch the makefile for hassle-free compilation. The two new targets are: make export make tarball Both preserve svn revisions and the exported tree does not depend on subversion in any way or shape. Documentation for this feature has been added to README. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-packaging_export/Makefile =================================================================== --- flashrom-packaging_export/Makefile (Revision 505) +++ flashrom-packaging_export/Makefile (Arbeitskopie) @@ -41,9 +41,15 @@ # Set the flashrom version string from the highest revision number # of the checked out flashrom files. -SVNDEF := -D'FLASHROM_VERSION="0.9.0-r$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +# Note to packagers: Any tree exported with "make export" or "make tarball" +# will not require any working subversion command. +SVNVERSION := $(shell (LANG=C svnversion -cn . | grep -v exported || cat .svnversion) \ + | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/") +VERSION := 0.9.0-r$(SVNVERSION) + +SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' + $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) $(STRIP) $(STRIP_ARGS) $(PROGRAM) @@ -78,6 +84,15 @@ mkdir -p $(PREFIX)/share/man/man8 $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 +export: + @svn export . flashrom-$(VERSION) + @echo -n $(SVNVERSION) >flashrom-$(VERSION)/.svnversion + @echo Exported flashrom repository contents to flashrom-$(VERSION)/ + +tarball: export + @tar cfz flashrom-$(VERSION).tar.gz flashrom-$(VERSION)/ + @echo Created tarball of repository contents at flashrom-$(VERSION).tar.gz + .PHONY: all clean distclean dep pciutils -include .dependencies Index: flashrom-packaging_export/README =================================================================== --- flashrom-packaging_export/README (Revision 505) +++ flashrom-packaging_export/README (Arbeitskopie) @@ -12,6 +12,21 @@ (see http://coreboot.org for details on coreboot) +Packaging +--------- + +To package flashrom and remove dependencies on subversion, either use +make export +or +make tarball + +make export will export all flashrom files from the subversion repository into +a directory named flashrom-$VERSION-r$SVNREVISION and will additionally create +a file .svnversion in that directory which stores the svn revision of the tree. + +make tarball will simply tar up the result of make export and gzip compress it. + + Build Requirements ------------------ -- http://www.hailfinger.org/ Index: flashrom-packaging_export/Makefile =================================================================== --- flashrom-packaging_export/Makefile (Revision 505) +++ flashrom-packaging_export/Makefile (Arbeitskopie) @@ -41,9 +41,15 @@ # Set the flashrom version string from the highest revision number # of the checked out flashrom files. -SVNDEF := -D'FLASHROM_VERSION="0.9.0-r$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +# Note to packagers: Any tree exported with "make export" or "make tarball" +# will not require any working subversion command. +SVNVERSION := $(shell (LANG=C svnversion -cn . | grep -v exported || cat .svnversion) \ + | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/") +VERSION := 0.9.0-r$(SVNVERSION) + +SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' + $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) $(STRIP) $(STRIP_ARGS) $(PROGRAM) @@ -78,6 +84,15 @@ mkdir -p $(PREFIX)/share/man/man8 $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 +export: + @svn export . flashrom-$(VERSION) + @echo -n $(SVNVERSION) >flashrom-$(VERSION)/.svnversion + @echo Exported flashrom repository contents to flashrom-$(VERSION)/ + +tarball: export + @tar cfz flashrom-$(VERSION).tar.gz flashrom-$(VERSION)/ + @echo Created tarball of repository contents at flashrom-$(VERSION).tar.gz + .PHONY: all clean distclean dep pciutils -include .dependencies Index: flashrom-packaging_export/README =================================================================== --- flashrom-packaging_export/README (Revision 505) +++ flashrom-packaging_export/README (Arbeitskopie) @@ -12,6 +12,21 @@ (see http://coreboot.org for details on coreboot) +Packaging +--------- + +To package flashrom and remove dependencies on subversion, either use +make export +or +make tarball + +make export will export all flashrom files from the subversion repository into +a directory named flashrom-$VERSION-r$SVNREVISION and will additionally create +a file .svnversion in that directory which stores the svn revision of the tree. + +make tarball will simply tar up the result of make export and gzip compress it. + + Build Requirements ------------------

3 15

[flashrom] r587 - trunk
by svn＠coreboot.org 12 Jun '09

12 Jun '09

Author: hailfinger Date: 2009-06-12 16:49:10 +0200 (Fri, 12 Jun 2009) New Revision: 587 Modified: trunk/Makefile trunk/README Log: This patch introduces two new targets which are designed to make the life of packagers easier. In particular, it should no longer be necessary to patch the makefile for hassle-free compilation. The targets are: make export make tarball Both preserve svn revisions and the exported tree does not depend on subversion in any way or shape. Documentation for this feature has been added to README. We need this for five reasons: 1. Packagers currently have to patch flashrom source to compile it on systems without subversion. We should make it easier for them. 2. Snapshot tarballs currently have a .svn 1.5 directory included but this will cause errors for users with older svn 1.4. Not requiring subversion for snapshot compilation is best. 3. Since packagers seldom the svn revision in their fixup patches, some packages out there have incorrect or no revision, only major version numbers. 4. Releasing a new version of flashrom needs too many changes to the makefile which have to be reverted instantly after the release. That is unnecessary churn. 5. Making a release is easy with the change. Update the major version, then run "make tarball". Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-06-12 14:05:25 UTC (rev 586) +++ trunk/Makefile 2009-06-12 14:49:10 UTC (rev 587) @@ -25,6 +25,7 @@ PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man CFLAGS ?= -Os -Wall -Werror +EXPORTDIR ?= . OS_ARCH = $(shell uname) ifneq ($(OS_ARCH), SunOS) @@ -53,9 +54,14 @@ # Set the flashrom version string from the highest revision number # of the checked out flashrom files. -SVNDEF := -D'FLASHROM_VERSION="0.9.0-r$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +# Note to packagers: Any tree exported with "make export" or "make tarball" +# will not require subversion. The downloadable snapshots are already exported. +SVNVERSION := $(shell LANG=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) +VERSION := 0.9.0-r$(SVNVERSION) + +SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' + $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) @@ -93,6 +99,17 @@ $(INSTALL) -m 0755 $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin $(INSTALL) -m 0644 $(PROGRAM).8 $(DESTDIR)$(MANDIR)/man8 -.PHONY: all clean distclean dep pciutils +export: + @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) + @svn export -r BASE . $(EXPORTDIR)/flashrom-$(VERSION) + @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(VERSION)/Makefile + @echo Exported $(EXPORTDIR)/flashrom-$(VERSION)/ +tarball: export + @tar cfz $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -C $(EXPORTDIR)/ flashrom-$(VERSION)/ + @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) + @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz + +.PHONY: all clean distclean dep pciutils export tarball + -include .dependencies Modified: trunk/README =================================================================== --- trunk/README 2009-06-12 14:05:25 UTC (rev 586) +++ trunk/README 2009-06-12 14:49:10 UTC (rev 587) @@ -15,6 +15,25 @@ (see http://coreboot.org for details on coreboot) +Packaging +--------- + +To package flashrom and remove dependencies on subversion, either use +make export +or +make tarball + +make export will export all flashrom files from the subversion repository at +revision BASE into a directory named $EXPORTDIR/flashrom-$VERSION-r$SVNREVISION +and will additionally modify the Makefile in that directory to contain the svn +revision of the exported tree. + +make tarball will simply tar up the result of make export and gzip compress it. + +The snapshot tarballs are the result of make tarball and require no further +processing. + + Build Instructions ------------------

1 0

build service results for r4356
by coreboot information 12 Jun '09

12 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4356 to the coreboot repository. This caused the following changes: Change Log: Fix typo in Winbond W83977TF register listing. Signed-off-by: Ioannis Barkas <tripl3fault(a)yahoo.com> Signed-off-by: Nikos Barkas <levelwol(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4356&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

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coreboot June 2009