coreboot June 2009

coreboot@coreboot.org

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500 discussions

Fwd: Re: ACPI support on M57SLI
by Florentin Demetrescu 15 Jun '09

15 Jun '09

----- Forwarded message from Florentin Demetrescu <echelon(a)free.fr> ----- Date: Mon, 15 Jun 2009 01:36:40 +0200 From: Florentin Demetrescu <echelon(a)free.fr> Reply-To: Florentin Demetrescu <echelon(a)free.fr> Subject: Re: [coreboot] ACPI support on M57SLI To: Harald Gutmann <harald.gutmann(a)gmx.net> Quoting Harald Gutmann <harald.gutmann(a)gmx.net>: > 1. check dmesg for error related to acpi. 1) output of "dmesg | grep -i acpi" : [ 0.000000] ACPI: RSDP (v002 CORE ) @ 0x00000000000f0400 [ 0.000000] ACPI: RSDT (v001 CORE RSDT 0x00000000 CORE 0x00000000) @ 0x00000000000f0424 [ 0.000000] ACPI: FADT (v001 GBT COREBOOT 0x00000000 iasl 0x00000000) @ 0x00000000000f0ea1 [ 0.000000] ACPI: HPET (v001 CORE AMD64 0x00000000 CORE 0x00000000) @ 0x00000000000f0f95 [ 0.000000] ACPI: MADT (v001 CORE MADT 0x00000000 CORE 0x00000000) @ 0x00000000000f0fcd [ 0.000000] ACPI: MCFG (v001 CORE MCFG 0x00000000 CORE 0x00000000) @ 0x00000000000f1035 [ 0.000000] ACPI: SRAT (v001 CORE SRAT 0x00000000 CORE 0x00000000) @ 0x00000000000f1061 [ 0.000000] ACPI: SLIT (v001 CORE SLIT 0x00000000 CORE 0x00000000) @ 0x00000000000f1101 [ 0.000000] ACPI: SSDT (v002 CORE DYNADATA 0x0000002a GENA 0x0000002a) @ 0x00000000000f112e [ 0.000000] ACPI: DSDT (v001 LXBIOS LXB-DSDT 0x00000001 INTL 0x20061109) @ 0x0000000000000000 [ 0.000000] ACPI: PM-Timer IO Port: 0x2008 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xf4144000] gsi_base[0]) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ2 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000 [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 62.311421] ACPI: Core revision 20060707 [ 62.315513] ACPI: Looking for DSDT in initramfs... file /DSDT.aml not found, using machine DSDT. [ 63.283765] ACPI: bus type pci registered [ 63.293822] ACPI: Interpreter enabled [ 63.297542] ACPI: Using IOAPIC for interrupt routing [ 63.302810] ACPI: PCI Root Bridge [PCI0] (0000:00) [ 63.313534] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 63.315525] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBF._PRT] [ 63.315600] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBE._PRT] [ 63.315656] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBD._PRT] [ 63.315713] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBC._PRT] [ 63.315772] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBB._PRT] [ 63.315830] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PEBA._PRT] [ 63.315888] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCID._PRT] [ 63.321951] pnp: PnP ACPI init [ 63.325291] pnp: PnP ACPI: found 3 devices [ 63.329495] PCI: Using ACPI for IRQ routing [ 66.951600] ACPI: (supports S0 S5) [ 67.605130] ACPI: PCI Interrupt 0000:00:02.1[B] -> GSI 23 (level, low) -> IRQ 23 [ 68.611707] ACPI: PCI Interrupt 0000:01:0a.0[A] -> GSI 18 (level, low) -> IRQ 18 [ 68.681455] ACPI: PCI Interrupt 0000:00:08.0[A] -> GSI 20 (level, low) -> IRQ 20 [ 69.219295] ACPI: PCI Interrupt 0000:00:02.0[A] -> GSI 22 (level, low) -> IRQ 22 [ 69.436130] ACPI: PCI Interrupt 0000:01:07.0[A] -> GSI 19 (level, low) -> IRQ 19 [ 69.504130] ACPI: PCI Interrupt 0000:00:05.0[A] -> <6>eth1: Digital DS21142/DS21143 Tulip rev 48 at Port 0x1000, 08:00:2B:C3:50:3B, IRQ 19. [ 70.228005] ACPI: PCI Interrupt 0000:00:05.1[B] -> GSI 21 (level, low) -> IRQ 21 [ 70.934620] ACPI: PCI Interrupt 0000:00:05.2[C] -> GSI 22 (level, low) -> IRQ 22 [ 81.373687] ACPI: PCI Interrupt 0000:00:06.1[B] -> GSI 23 (level, low) -> IRQ 23 [ 89.176132] ibm_acpi: ec object not found [ 89.368539] ACPI: Power Button (FF) [PWRF] [ 89.753690] pcc_acpi: loading... > 2. check soft-power-off 2) It works! > 3. check PowerNow! (modprobe powernow-k8) > http://www.twibble.org/Articles/amd-x2-powernow (overview) 3) output of "dmesg | grep -i power" : [ 89.368516] input: Power Button (FF) as /class/input/input3 [ 89.368539] ACPI: Power Button (FF) [PWRF] [ 90.021841] powernow-k8: Found 2 AMD Athlon(tm) 64 X2 Dual Core Processor 3800+ processors (version 2.00.00) [ 90.021890] powernow-k8: 0 : fid 0xc (2000 MHz), vid 0xa [ 90.021894] powernow-k8: 1 : fid 0xa (1800 MHz), vid 0xc [ 90.021897] powernow-k8: 2 : fid 0x2 (1000 MHz), vid 0x12 [ 90.021935] powernow-k8: ph2 null fid transition 0xc Moreover, when monitoring the CPU frequency with ksysguard (I have a KDE desktop), after launching a CPU-intensive process (like a "dd if=/dev/urandom of=/dev/null"), one can see the CPU frequency jump from 1000 MHz to 2000 MHhz. > 4. check HPET (works with coreboot, but not with proprietary bios ;)) 4) Dunno how to (functionaly) test this.. Anyway dmesg says : [ 0.000000] ACPI: HPET (v001 CORE AMD64 0x00000000 CORE 0x00000000) @ 0x00000000000f0f95 [ 0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000 > 5. review my patch Done. No remarks. :) I did all these tests with an old ubuntu (feisty 7.04), with a 2.6.20 kernel. If more tests are needed in order to validate the Harald's patch, tell me and I will upgrade my kernel next week. Regards, Florentin ----- End forwarded message -----

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[PATCH] flashrom: Add PMC Pm29F002T/B support
by Uwe Hermann 15 Jun '09

15 Jun '09

See patch. I didn't find timing info in the datasheet after quick glace. Also, the 8192 is pretty arbitrary as we only do byte-wise programming on this chip. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[flashrom] r590 - trunk
by svn＠coreboot.org 14 Jun '09

14 Jun '09

Author: uwe Date: 2009-06-14 23:53:26 +0200 (Sun, 14 Jun 2009) New Revision: 590 Added: trunk/pm29f002.c Modified: trunk/Makefile trunk/flash.h trunk/flashchips.c Log: Add support for the PMC Pm29F002T/B chips. I sucessfully tested all operations on a Pm29F002T chip. The Pm29F002B is untested but I assume it should also work. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-06-13 12:04:03 UTC (rev 589) +++ trunk/Makefile 2009-06-14 21:53:26 UTC (rev 590) @@ -43,7 +43,7 @@ LIBS += -lpci -lz OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ - sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o \ + sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.c \ w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-13 12:04:03 UTC (rev 589) +++ trunk/flash.h 2009-06-14 21:53:26 UTC (rev 590) @@ -453,6 +453,8 @@ #define PMC_25LV040 0x7E #define PMC_25LV080B 0x13 #define PMC_25LV016B 0x14 +#define PMC_29F002T 0x1D +#define PMC_29F002B 0x2D #define PMC_39LV512 0x1B #define PMC_39F010 0x1C /* also Pm39LV010 */ #define PMC_39LV020 0x3D @@ -783,6 +785,9 @@ int erase_29f040b(struct flashchip *flash); int write_29f040b(struct flashchip *flash, uint8_t *buf); +/* pm29f002.c */ +int write_pm29f002(struct flashchip *flash, uint8_t *buf); + /* en29f002a.c */ int probe_en29f002a(struct flashchip *flash); int erase_en29f002a(struct flashchip *flash); Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-13 12:04:03 UTC (rev 589) +++ trunk/flashchips.c 2009-06-14 21:53:26 UTC (rev 590) @@ -1514,6 +1514,38 @@ { .vendor = "PMC", + .name = "Pm29F0002T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = PMC_ID_NOPREFIX, + .model_id = PMC_29F002T, + .total_size = 256, + .page_size = 8192, + .tested = TEST_OK_PREW, + .probe = probe_29f040b, + .probe_timing = TIMING_FIXME, + .erase = erase_29f040b, + .write = write_pm29f002, + .read = read_memmapped, + }, + + { + .vendor = "PMC", + .name = "Pm29F0002B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = PMC_ID_NOPREFIX, + .model_id = PMC_29F002B, + .total_size = 256, + .page_size = 8192, + .tested = TEST_UNTESTED, + .probe = probe_29f040b, + .probe_timing = TIMING_FIXME, + .erase = erase_29f040b, + .write = write_pm29f002, + .read = read_memmapped, + }, + + { + .vendor = "PMC", .name = "Pm39LV010", .bustype = CHIP_BUSTYPE_NONSPI, .manufacture_id = PMC_ID_NOPREFIX, Added: trunk/pm29f002.c =================================================================== --- trunk/pm29f002.c (rev 0) +++ trunk/pm29f002.c 2009-06-14 21:53:26 UTC (rev 590) @@ -0,0 +1,53 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" + +int write_pm29f002(struct flashchip *flash, uint8_t *buf) +{ + int i, total_size = flash->total_size * 1024; + chipaddr bios = flash->virtual_memory; + chipaddr dst = bios; + + /* Pm29F002T/B use the same erase method... */ + erase_29f040b(flash); + + printf("Programming page: "); + for (i = 0; i < total_size; i++) { + if ((i & 0xfff) == 0) + printf("address: 0x%08lx", (unsigned long)i); + + /* Pm29F002T/B only support byte-wise programming. */ + chip_writeb(0xAA, bios + 0x555); + chip_writeb(0x55, bios + 0x2AA); + chip_writeb(0xA0, bios + 0x555); + chip_writeb(*buf++, dst++); + + /* Wait for Toggle bit ready. */ + toggle_ready_jedec(dst); + + if ((i & 0xfff) == 0) + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + } + + printf("\n"); + + return 0; +}

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Sucessfully flashed an Asrock AOD790GX/128M
by Mag. Erhard F. 14 Jun '09

14 Jun '09

Hi all! Just wanted to confirm that I successfully flashed an Asrock AOD790GX/128M with flashrom v0.9.0. It's an AMD Socket AM2+ Board witch 790GX Chipseit and Southbridge SB750. See http://www.asrock.com/mb/overview.asp?Model=AOD790GX/128M flashrom's output was: Calibrating delay loop... OK. No coreboot table found. Found chipset "ATI(AMD) SB700", enabling flash write... OK. Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Reading flash... done. Verifying flash... FAILED at 0x00000000! Expected=0x00, Read=0x4d Though flashrom reports that verifying fails, flashing BIOS versions 1.40 and 1.50 worked perfectly allright. regards Erhard F.

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[flashrom] [patch] Replace chip_readb in a loop with chip_readn in jedec.c
by Urja Rannikko 14 Jun '09

14 Jun '09

Replace calls to chip_readb in a loop with chip_readn in jedec.c. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- patch inlined too: Index: jedec.c =================================================================== --- jedec.c (revision 580) +++ jedec.c (working copy) @@ -21,6 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdlib.h> +#include <stdio.h> +#include <string.h> #include "flash.h" #define MAX_REFLASH_TRIES 0x10 @@ -251,6 +254,7 @@ int i, tried = 0, start_index = 0, ok; chipaddr d = dst; uint8_t *s = src; + uint8_t *tmpbuf = NULL; retry: /* Issue JEDEC Data Unprotect comand */ @@ -272,14 +276,14 @@ dst = d; src = s; ok = 1; - for (i = 0; i < page_size; i++) { - if (chip_readb(dst) != *src) { - ok = 0; - break; + tmpbuf = malloc(page_size); + if (!tmpbuf) { + fprintf(stderr,"Error: cannot allocate memory\n"); + exit(1); } - dst++; - src++; - } + chip_readn(tmpbuf,dst,page_size); + if (memcmp(tmpbuf,src,page_size) != 0) ok = 0; + free(tmpbuf); if (!ok && tried++ < MAX_REFLASH_TRIES) { start_index = i; @@ -341,15 +345,29 @@ int total_size = flash->total_size * 1024; int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; + uint8_t *tmpbuf; erase_chip_jedec(flash); // dumb check if erase was successful. - for (i = 0; i < total_size; i++) { - if (chip_readb(bios + i) != 0xff) { - printf("ERASE FAILED @%d, val %02x!\n", i, chip_readb(bios + i)); - return -1; + // We'll do that in page_size chunks to detect failure earlier on slow links + + tmpbuf = malloc(page_size); + if (!tmpbuf) { + fprintf(stderr,"Error: cannot allocate memory\n"); + exit(1); } + for (i = 0; i < total_size; i+=page_size) { + int n; + chip_readn(tmpbuf,bios+i,page_size); + for(n=0;n<page_size;n++) { + if (tmpbuf[n] != 0xff) { + printf("ERASE FAILED @%d, val %02x!\n", i+n, tmpbuf[n]); + free(tmpbuf); + return -1; + } + } } + free(tmpbuf); printf("Programming page: "); for (i = 0; i < total_size / page_size; i++) { -- urjaman

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Re: [coreboot] Gigabyte M57SLI-S4 Interrupt Fix
by Harald Gutmann 14 Jun '09

14 Jun '09

On Thursday 11 June 2009 10:28:51 you wrote: > Hi Harald, Hello Florentin! Thanks for testing this patch, but it seems to me, that you did somewhere a mistake. > I begun to test your patch (against the coreboot revision 4350) but > unfortunately linux crashes after booting with your coreboot patch on my > machine. :/ > Unfortunately I cannot send you any debug logs right now, but I will do it > this evening when I return home (Im at work right now). The only > informations that I can give you is that I used a 64 bit kernel (2.6.20) > and the behaviour of the kernel seems like an "IRQ storm" to me.. (the > acpi was not activated in linux, but in coreboot I dont know..) You need to test this patch against a clean coreboot tree, without any ACPI support for M57SLI. The problem which I also ran into with this patch is: When ACPI is activated in Coreboot with the vendors dstd.asl the interrupt routing is different to the interrupts set in mptable.c. This means that Linux is not able to boot, because it normally prefers ACPI interrupt routing, and then the IRQ's which are set correctly in the ACPI tables don't fit to what is set in the interrupt registers. If you are interested in the details have a look at http://www.coreboot.org/Nvidia_MCP55_Porting_Notes. The registers from 0x7c-0x84 in mptable.c are set up with pci_write_config32 in mptable.c. There you can assign the IRQ's like you want to the different devices on the mainboard. This can be done as you like, but you have to adjust all the PCI_INT (for mptable) and ACPI IRQ routing stuff so that it fits to those registers. The wiring is in that case what you need to look at. (Porting Notes) Problem with activated ACPI: The ACPI IRQ routing does not fit to the patched 0x7c-0x84 registers, and therefore you get what you called "IRQ Storm" (which means that no device get's is IRQ like it should; keep in mind that linux always prefers ACPI tables instead of falling back to a correct mptable it gives you those errors.) I didn't miss that you wrote "acpi was not activated in linux", but i strongly believe that it was not completle deactivated. So, please try my patch with a clean coreboot tree, and it should work well! > Regards, > Florentin Demetrescu Regards, Harald PS: Please be so kindly and CC the list at least when talking about patches of coreboot. > Quoting Harald Gutmann <harald.gutmann(a)gmx.net>: > > Hello, > > > > after a few tries of me to fix the interrupt problems which occurred on > > the M57SLI here is the final patch from me. > > > > The Patch fixes the following issues on M57SLI: > > * Interrupt routing in the MPTable > > > > which affects the following hardware parts: > > * PCI-E 16x Slots (blue and black) - both are working now like a charm > > * PCI-E 1x Slots - all three should be fine, but I have no card to test. > > (untested) > > * PCI Slots - both work fine now. > > > > This is the first and (hopefully) the last patch on this issue which gets > > a > > > > Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> > > > > from me. > > > > I'm really looking forward to commit this patch (which is my first one) > > and mark the interrupt issues on the wiki page to the M57SLI as solved. > > :) > > > > > > Kind regards, > > Harald Gutmann

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Re: [coreboot] Hosed ms-7032, I foolishly flashed the bios with a .700
by Phil Neary 14 Jun '09

14 Jun '09

Flashrom finds the chipset to be VIA VT8237, and the actual chip it finds is a PMC Pm49FL004 512KB @ 0xfff80000. This is what I get now, I'm going to try your suggestion and have a look in the scrapyard, I think there's one quite close by. kind Regards Phil --- On Sun, 14/6/09, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Subject: Re: [coreboot] Hosed ms-7032, I foolishly flashed the bios with a .700 > To: philneary(a)yahoo.co.uk > Cc: coreboot(a)coreboot.org > Date: Sunday, 14 June, 2009, 12:26 AM > On 12.06.2009 13:47, philneary(a)yahoo.co.uk > wrote: > > So if I ask for a "4mb PLCC32 LPC Flash-ROM" I should > get what I'm after? > > > > Yes, that should work. Make sure that what you get is a 4 > Mbit chip, not > a 4 MByte chip. > As an alternative, you could look in a scrapyard for broken > boards which > have compatible LPC chips in a socket. As a rough > guideline, probably > all AMD64 capable boards should have compatible chips > (except for the > most recent boards which have 8-pin SPI chips). > > > > [...] hot flash it with the correct bios. I'm using my > friends PC to do this and it has a Foxconn P4M8907MA-KRS2H > motherboard. > > > > I'm only 90% sure about this. It has a VIA chipset as well, > but to be > sure it would be nice if you could run flashrom on that > board and tell > us which chip it detects. > > Regards, > Carl-Daniel > > -- > http://www.hailfinger.org/ > >

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Re: [coreboot] Hosed ms-7032, I foolishly flashed the bios with a .700
by philneary＠yahoo.co.uk 14 Jun '09

14 Jun '09

Hi all, I'm wanting to try the suggestion of putting a new ROM chip on top of the old one (W39V040AP) with a bit of soldering, so I can use both chips. I'm just wondering what chip to ask for? I've been warned about Winbond chips and the technical specs for my chip are: 4mb PLCC32 LPC. So if I ask for a "4mb PLCC32 LPC Flash-ROM" I should get what I'm after? Also once I get the chip I'm going to have to hot flash it with the correct bios. I'm using my friends PC to do this and it has a Foxconn P4M8907MA-KRS2H motherboard. I'll be using Flashrom to do this. Should this be okay? Many thanks for all your help, it won't be long before I'm back up and running.

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[PATCH] flashrom: Refactor SPI reads
by Carl-Daniel Hailfinger 13 Jun '09

13 Jun '09

Every SPI host controller implemented its own way to read flash chips. This was partly due to a design problem in the abstraction layer. There should be exactly two different functions for reading SPI chips: - memory mapped reads - SPI command reads. Each of them should be contained in a separate function, optionally taking parameters where needed. This patch solves the problems mentioned above, shortens the code and makes the code logic a lot more obvious. Since open-coding the min() function leads to errors, include it in this patch as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_read_refactor/flash.h =================================================================== --- flashrom-spi_read_refactor/flash.h (Revision 563) +++ flashrom-spi_read_refactor/flash.h (Arbeitskopie) @@ -679,6 +679,7 @@ extern int verbose; #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); +int min(int a, int b); int read_memmapped(struct flashchip *flash, uint8_t *buf); extern char *pcidev_bdf; @@ -726,6 +727,7 @@ int spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_read_generic(struct flashchip *flash, uint8_t *buf, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Index: flashrom-spi_read_refactor/it87spi.c =================================================================== --- flashrom-spi_read_refactor/it87spi.c (Revision 563) +++ flashrom-spi_read_refactor/it87spi.c (Arbeitskopie) @@ -260,18 +260,12 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; fast_spi = 0; if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - for (i = 0; i < total_size; i += 3) { - int toread = 3; - if (total_size - i < toread) - toread = total_size - i; - spi_nbyte_read(i, buf + i, toread); - } + spi_read_generic(flash, buf, 3); } else { - memcpy(buf, (const char *)flash->virtual_memory, total_size); + read_memmapped(flash, buf); } return 0; Index: flashrom-spi_read_refactor/spi.c =================================================================== --- flashrom-spi_read_refactor/spi.c (Revision 563) +++ flashrom-spi_read_refactor/spi.c (Arbeitskopie) @@ -652,6 +652,33 @@ return spi_command(sizeof(cmd), len, cmd, bytes); } +/* + * Read a complete flash chip. + * Each page is read separately in chunks with a maximum size of chunksize. + */ +int spi_read_generic(struct flashchip *flash, uint8_t *buf, int chunksize) +{ + int rc = 0; + int i, j; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + int toread; + + for (j = 0; j < total_size / page_size; j++) { + for (i = 0; i < page_size; i += chunksize) { + toread = min(chunksize, page_size - i); + rc = spi_nbyte_read(j * page_size + i, + buf + j * page_size + i, toread); + if (rc) + break; + } + if (rc) + break; + } + + return rc; +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf) { switch (spi_controller) { Index: flashrom-spi_read_refactor/wbsio_spi.c =================================================================== --- flashrom-spi_read_refactor/wbsio_spi.c (Revision 563) +++ flashrom-spi_read_refactor/wbsio_spi.c (Arbeitskopie) @@ -177,12 +177,12 @@ { int size = flash->total_size * 1024; - if (flash->total_size > 1024) { + if (size > 1024 * 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - memcpy(buf, (const char *)flash->virtual_memory, size); + read_memmapped(flash, buf); return 0; } Index: flashrom-spi_read_refactor/sb600spi.c =================================================================== --- flashrom-spi_read_refactor/sb600spi.c (Revision 563) +++ flashrom-spi_read_refactor/sb600spi.c (Arbeitskopie) @@ -41,14 +41,8 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; - int total_size = flash->total_size * 1024; - int page_size = 8; - - for (i = 0; i < total_size / page_size; i++) - spi_nbyte_read(i * page_size, (void *)(buf + i * page_size), - page_size); - return rc; + /* Maximum read length is 8 bytes. */ + return spi_read_generic(flash, buf, 8); } uint8_t sb600_read_status_register(void) Index: flashrom-spi_read_refactor/flashrom.c =================================================================== --- flashrom-spi_read_refactor/flashrom.c (Revision 563) +++ flashrom-spi_read_refactor/flashrom.c (Arbeitskopie) @@ -174,6 +174,11 @@ return 0; } +int min(int a, int b) +{ + return (a < b) ? a : b; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); Index: flashrom-spi_read_refactor/ichspi.c =================================================================== --- flashrom-spi_read_refactor/ichspi.c (Revision 563) +++ flashrom-spi_read_refactor/ichspi.c (Arbeitskopie) @@ -148,8 +148,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, - int offset, int maxdata); static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); @@ -614,38 +612,6 @@ return -1; } -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, - int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = flash->page_size; - int a; - - printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, buf); - - for (a = 0; a < page_size; a += maxdata) { - if (remaining < maxdata) { - - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], remaining)) { - printf_debug("Error reading"); - return 1; - } - remaining = 0; - } else { - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], maxdata)) { - printf_debug("Error reading"); - return 1; - } - remaining -= maxdata; - } - } - - return 0; -} - static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata) { @@ -683,21 +649,12 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf) { - int i, rc = 0; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) { + if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; - } - for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { - rc = ich_spi_read_page(flash, (void *)(buf + i * page_size), - i * page_size, maxdata); - } - - return rc; + return spi_read_generic(flash, buf, maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) -- http://www.hailfinger.org/ Index: flashrom-spi_read_refactor/flash.h =================================================================== --- flashrom-spi_read_refactor/flash.h (Revision 563) +++ flashrom-spi_read_refactor/flash.h (Arbeitskopie) @@ -679,6 +679,7 @@ extern int verbose; #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); +int min(int a, int b); int read_memmapped(struct flashchip *flash, uint8_t *buf); extern char *pcidev_bdf; @@ -726,6 +727,7 @@ int spi_disable_blockprotect(void); void spi_byte_program(int address, uint8_t byte); int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_read_generic(struct flashchip *flash, uint8_t *buf, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Index: flashrom-spi_read_refactor/it87spi.c =================================================================== --- flashrom-spi_read_refactor/it87spi.c (Revision 563) +++ flashrom-spi_read_refactor/it87spi.c (Arbeitskopie) @@ -260,18 +260,12 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; fast_spi = 0; if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - for (i = 0; i < total_size; i += 3) { - int toread = 3; - if (total_size - i < toread) - toread = total_size - i; - spi_nbyte_read(i, buf + i, toread); - } + spi_read_generic(flash, buf, 3); } else { - memcpy(buf, (const char *)flash->virtual_memory, total_size); + read_memmapped(flash, buf); } return 0; Index: flashrom-spi_read_refactor/spi.c =================================================================== --- flashrom-spi_read_refactor/spi.c (Revision 563) +++ flashrom-spi_read_refactor/spi.c (Arbeitskopie) @@ -652,6 +652,33 @@ return spi_command(sizeof(cmd), len, cmd, bytes); } +/* + * Read a complete flash chip. + * Each page is read separately in chunks with a maximum size of chunksize. + */ +int spi_read_generic(struct flashchip *flash, uint8_t *buf, int chunksize) +{ + int rc = 0; + int i, j; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + int toread; + + for (j = 0; j < total_size / page_size; j++) { + for (i = 0; i < page_size; i += chunksize) { + toread = min(chunksize, page_size - i); + rc = spi_nbyte_read(j * page_size + i, + buf + j * page_size + i, toread); + if (rc) + break; + } + if (rc) + break; + } + + return rc; +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf) { switch (spi_controller) { Index: flashrom-spi_read_refactor/wbsio_spi.c =================================================================== --- flashrom-spi_read_refactor/wbsio_spi.c (Revision 563) +++ flashrom-spi_read_refactor/wbsio_spi.c (Arbeitskopie) @@ -177,12 +177,12 @@ { int size = flash->total_size * 1024; - if (flash->total_size > 1024) { + if (size > 1024 * 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - memcpy(buf, (const char *)flash->virtual_memory, size); + read_memmapped(flash, buf); return 0; } Index: flashrom-spi_read_refactor/sb600spi.c =================================================================== --- flashrom-spi_read_refactor/sb600spi.c (Revision 563) +++ flashrom-spi_read_refactor/sb600spi.c (Arbeitskopie) @@ -41,14 +41,8 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; - int total_size = flash->total_size * 1024; - int page_size = 8; - - for (i = 0; i < total_size / page_size; i++) - spi_nbyte_read(i * page_size, (void *)(buf + i * page_size), - page_size); - return rc; + /* Maximum read length is 8 bytes. */ + return spi_read_generic(flash, buf, 8); } uint8_t sb600_read_status_register(void) Index: flashrom-spi_read_refactor/flashrom.c =================================================================== --- flashrom-spi_read_refactor/flashrom.c (Revision 563) +++ flashrom-spi_read_refactor/flashrom.c (Arbeitskopie) @@ -174,6 +174,11 @@ return 0; } +int min(int a, int b) +{ + return (a < b) ? a : b; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); Index: flashrom-spi_read_refactor/ichspi.c =================================================================== --- flashrom-spi_read_refactor/ichspi.c (Revision 563) +++ flashrom-spi_read_refactor/ichspi.c (Arbeitskopie) @@ -148,8 +148,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, - int offset, int maxdata); static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); @@ -614,38 +612,6 @@ return -1; } -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, - int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = flash->page_size; - int a; - - printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, buf); - - for (a = 0; a < page_size; a += maxdata) { - if (remaining < maxdata) { - - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], remaining)) { - printf_debug("Error reading"); - return 1; - } - remaining = 0; - } else { - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], maxdata)) { - printf_debug("Error reading"); - return 1; - } - remaining -= maxdata; - } - } - - return 0; -} - static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata) { @@ -683,21 +649,12 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf) { - int i, rc = 0; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) { + if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; - } - for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { - rc = ich_spi_read_page(flash, (void *)(buf + i * page_size), - i * page_size, maxdata); - } - - return rc; + return spi_read_generic(flash, buf, maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)

2 4

[flashrom] r589 - trunk
by svn＠coreboot.org 13 Jun '09

13 Jun '09

Author: hailfinger Date: 2009-06-13 14:04:03 +0200 (Sat, 13 Jun 2009) New Revision: 589 Modified: trunk/flash.h trunk/flashrom.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Every SPI host controller implemented its own way to read flash chips. This was partly due to a design problem in the abstraction layer. There should be exactly two different functions for reading SPI chips: - memory mapped reads - SPI command reads. Each of them should be contained in a separate function, optionally taking parameters where needed. This patch solves the problems mentioned above, shortens the code and makes the code logic a lot more obvious. Since open-coding the min() function leads to errors, include it in this patch as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/flash.h 2009-06-13 12:04:03 UTC (rev 589) @@ -721,6 +721,7 @@ #define printf_debug(x...) { if (verbose) printf(x); } void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf); +int min(int a, int b); extern char *pcidev_bdf; /* layout.c */ @@ -768,6 +769,7 @@ void spi_byte_program(int address, uint8_t byte); int spi_nbyte_program(int address, uint8_t *bytes, int len); int spi_nbyte_read(int address, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); uint32_t spi_get_valid_read_addr(void); Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/flashrom.c 2009-06-13 12:04:03 UTC (rev 589) @@ -200,6 +200,11 @@ return 0; } +int min(int a, int b) +{ + return (a < b) ? a : b; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/ichspi.c 2009-06-13 12:04:03 UTC (rev 589) @@ -148,8 +148,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, - int offset, int maxdata); static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata); @@ -614,38 +612,6 @@ return -1; } -static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, - int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = flash->page_size; - int a; - - printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, buf); - - for (a = 0; a < page_size; a += maxdata) { - if (remaining < maxdata) { - - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], remaining)) { - printf_debug("Error reading"); - return 1; - } - remaining = 0; - } else { - if (spi_nbyte_read(offset + (page_size - remaining), - &buf[page_size - remaining], maxdata)) { - printf_debug("Error reading"); - return 1; - } - remaining -= maxdata; - } - } - - return 0; -} - static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, int offset, int maxdata) { @@ -683,21 +649,12 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf) { - int i, rc = 0; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) { + if (spi_controller == SPI_CONTROLLER_VIA) maxdata = 16; - } - for (i = 0; (i < total_size / page_size) && (rc == 0); i++) { - rc = ich_spi_read_page(flash, (void *)(buf + i * page_size), - i * page_size, maxdata); - } - - return rc; + return spi_read_chunked(flash, buf, maxdata); } int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/it87spi.c 2009-06-13 12:04:03 UTC (rev 589) @@ -260,18 +260,12 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; fast_spi = 0; if ((programmer == PROGRAMMER_IT87SPI) || (total_size > 512 * 1024)) { - for (i = 0; i < total_size; i += 3) { - int toread = 3; - if (total_size - i < toread) - toread = total_size - i; - spi_nbyte_read(i, buf + i, toread); - } + spi_read_chunked(flash, buf, 3); } else { - memcpy(buf, (const char *)flash->virtual_memory, total_size); + read_memmapped(flash, buf); } return 0; Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/sb600spi.c 2009-06-13 12:04:03 UTC (rev 589) @@ -41,14 +41,8 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf) { - int rc = 0, i; - int total_size = flash->total_size * 1024; - int page_size = 8; - - for (i = 0; i < total_size / page_size; i++) - spi_nbyte_read(i * page_size, (void *)(buf + i * page_size), - page_size); - return rc; + /* Maximum read length is 8 bytes. */ + return spi_read_chunked(flash, buf, 8); } uint8_t sb600_read_status_register(void) Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/spi.c 2009-06-13 12:04:03 UTC (rev 589) @@ -673,6 +673,33 @@ return spi_command(sizeof(cmd), len, cmd, bytes); } +/* + * Read a complete flash chip. + * Each page is read separately in chunks with a maximum size of chunksize. + */ +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int chunksize) +{ + int rc = 0; + int i, j; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + int toread; + + for (j = 0; j < total_size / page_size; j++) { + for (i = 0; i < page_size; i += chunksize) { + toread = min(chunksize, page_size - i); + rc = spi_nbyte_read(j * page_size + i, + buf + j * page_size + i, toread); + if (rc) + break; + } + if (rc) + break; + } + + return rc; +} + int spi_chip_read(struct flashchip *flash, uint8_t *buf) { switch (spi_controller) { Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-06-12 21:29:36 UTC (rev 588) +++ trunk/wbsio_spi.c 2009-06-13 12:04:03 UTC (rev 589) @@ -177,12 +177,12 @@ { int size = flash->total_size * 1024; - if (flash->total_size > 1024) { + if (size > 1024 * 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); return 1; } - memcpy(buf, (const char *)flash->virtual_memory, size); + read_memmapped(flash, buf); return 0; }

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coreboot June 2009