coreboot June 2009

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[flashrom] r613 - trunk
by svn＠coreboot.org 19 Jun '09

19 Jun '09

Author: uwe Date: 2009-06-19 17:54:39 +0200 (Fri, 19 Jun 2009) New Revision: 613 Modified: trunk/flashchips.c trunk/flashchips.h trunk/satasii.c Log: Add support for the AMD Am29F010A/B chips. Also, add support for the Silicon Image 3112(A) SATA controller. Both have been tested by Andrew Morgan <ziltro(a)ziltro.com> on hardware and work fine. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Andrew Morgan <ziltro(a)ziltro.com> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-06-19 14:22:16 UTC (rev 612) +++ trunk/flashchips.c 2009-06-19 15:54:39 UTC (rev 613) @@ -41,6 +41,22 @@ { .vendor = "AMD", + .name = "Am29F010A/B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = AMD_ID, + .model_id = AM_29F010B, /* Same as Am29F010A */ + .total_size = 128, + .page_size = 16 * 1024, + .tested = TEST_OK_PREW, + .probe = probe_29f040b, + .probe_timing = TIMING_FIXME, + .erase = erase_29f040b, + .write = write_pm29f002, + .read = read_memmapped, + }, + + { + .vendor = "AMD", .name = "Am29F002(N)BB", .bustype = CHIP_BUSTYPE_NONSPI, .manufacture_id = AMD_ID, Modified: trunk/flashchips.h =================================================================== --- trunk/flashchips.h 2009-06-19 14:22:16 UTC (rev 612) +++ trunk/flashchips.h 2009-06-19 15:54:39 UTC (rev 613) @@ -39,6 +39,7 @@ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ +#define AM_29F010B 0x20 /* Same as Am29F010A */ #define AM_29F002BT 0xB0 #define AM_29F002BB 0x34 #define AM_29F040B 0xA4 Modified: trunk/satasii.c =================================================================== --- trunk/satasii.c 2009-06-19 14:22:16 UTC (rev 612) +++ trunk/satasii.c 2009-06-19 15:54:39 UTC (rev 613) @@ -35,6 +35,7 @@ struct pcidev_status satas_sii[] = { {0x1095, 0x0680, PCI_OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, + {0x1095, 0x3112, PCI_OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"}, {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},

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[PATCH] v2: Enable CBFS and HIGH_TABLES for MSI MS-6178
by Uwe Hermann 19 Jun '09

19 Jun '09

See patch. The trouble I was having earlier with CBFS seems to come from removing the "normal" image (to get more space in the ROM). I'll investigate. The attached patch works fine though. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4365 - in trunk/coreboot-v2: src/mainboard/msi/ms6178 src/northbridge/intel/i82810 targets/msi/ms6178
by svn＠coreboot.org 19 Jun '09

19 Jun '09

Author: uwe Date: 2009-06-19 17:41:49 +0200 (Fri, 19 Jun 2009) New Revision: 4365 Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c trunk/coreboot-v2/targets/msi/ms6178/Config.lb Log: Convert the MSI MS-6178 board to CBFS. Also, enable HIGH_TABLES support for this board. The HIGH_TABLES failed with: No matching ram area found for range: [0x00000000000f0000, 0x0000000000100000) Ram areas [0x0000000000000000, 0x0000000000001000) Reserved [0x0000000000001000, 0x00000000000a0000) RAM [0x0000000000100000, 0x000000000fff0000) RAM [0x000000000fff0000, 0x0000000010000000) Reserved SELFBOOT RETURNED! Boot failed. The fix was to change northbridge.c as follows: - ram_resource(dev, idx++, 1024, tolmk - 1024); + ram_resource(dev, idx++, 768, tolmk - 768); This is build-tested and tested on hardware by me. It boots fine, for instace with SeaBIOS and the standard GRUB1 from my disk. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2009-06-19 12:03:40 UTC (rev 4364) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2009-06-19 15:41:49 UTC (rev 4365) @@ -65,6 +65,7 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses HAVE_HIGH_TABLES default ROM_SIZE = 512 * 1024 default HAVE_FALLBACK_BOOT = 1 @@ -75,7 +76,7 @@ default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +default FALLBACK_SIZE = ROM_IMAGE_SIZE default STACK_SIZE = 8 * 1024 default HEAP_SIZE = 16 * 1024 default HAVE_OPTION_TABLE = 0 @@ -96,10 +97,6 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 - -# -# CBFS -# -# -default CONFIG_CBFS=0 +default CONFIG_CBFS = 1 +default HAVE_HIGH_TABLES = 1 end Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-06-19 12:03:40 UTC (rev 4364) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/northbridge.c 2009-06-19 15:41:49 UTC (rev 4365) @@ -170,7 +170,7 @@ /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, tolmk - 1024); + ram_resource(dev, idx++, 768, tolmk - 768); #if HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ Modified: trunk/coreboot-v2/targets/msi/ms6178/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms6178/Config.lb 2009-06-19 12:03:40 UTC (rev 4364) +++ trunk/coreboot-v2/targets/msi/ms6178/Config.lb 2009-06-19 15:41:49 UTC (rev 4365) @@ -22,7 +22,6 @@ mainboard msi/ms6178 option ROM_SIZE = 512 * 1024 -# option ROM_SIZE = (512 * 1024) - (32 * 1024) option MAINBOARD_VENDOR = "MSI" option MAINBOARD_PART_NUMBER = "MS-6178" @@ -48,3 +47,6 @@ end buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + +# pci_rom i810.vga vendor_id=0x8086 device_id=0x7120 +

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r4315, CBFS, supermicro H8DME -> boom
by Ward Vandewege 19 Jun '09

19 Jun '09

So, yesterday I spent some quality time tracking down a rather odd issue I saw with svn head (r4362): http://ward.vandewege.net/coreboot/h8dme/minicom-20090618b.cap As you can see, coreboot somehow garbles serial output right after printing Clearing initial memory region: Done and then finally soft resets after entering a CBFS stage: Stage: load @ 819200/28672 bytes, enter @ c8000 I tracked this down to r4315. Here's a boot log with r4315: http://ward.vandewege.net/coreboot/h8dme/minicom-20090618q.cap And here's r4314, which works: http://ward.vandewege.net/coreboot/h8dme/minicom-20090618q.cap The weird thing is that I don't have this problem on an h8dmr with K10 cpus (though I'm still tracking down other issues there, so perhaps they mask this problem), nor on an m57sli with a dual core AM2 CPU. I talked to Patrick (the author of r4315) about this yesterday on IRC, and he said he could not reproduce this on SimNow with amd/serengeti_cheetah. So, if anyone has thoughts on what might be causing this, they would be very welcome :) Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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[flashrom] VIA VT8233 support
by Mateusz Murawski 19 Jun '09

19 Jun '09

Hi Small patch to support VIA VT8233 Signed-off-by: Mateusz Murawski <matowy(a)tlen.pl>

3 4

Flashrom test results for VIA EPIA-EX15000
by Clark Rawlins 19 Jun '09

19 Jun '09

I noticed that the EPIA-EX15000 and EPIA-NX15000 weren't mentioned on the flashrom page and since we are using it successfully to flash propitiatory images I wanted to send in a report. VIA EPIA-EX15000 # flashrom -wv EX15000-VIAVELOCITY.BIN Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA CX700", enabling flash write... OK. Found chip "SST SST49LF040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 Verifying flash... VERIFIED. VIA EPIA-NX15000 # flashrom -wv NX15000-VIAVELOCITY.BIN Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA CX700", enabling flash write... OK. Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 Verifying flash... VERIFIED.

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[flashrom] r612 - trunk
by svn＠coreboot.org 19 Jun '09

19 Jun '09

Author: uwe Date: 2009-06-19 16:22:16 +0200 (Fri, 19 Jun 2009) New Revision: 612 Modified: trunk/board_enable.c Log: Mark VIA EPIA-EX15000 and VIA EPIA-NX15000 as working (trivial). Thanks Clark Rawlins <clark(a)bit63.org> for the report! Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-19 14:20:34 UTC (rev 611) +++ trunk/board_enable.c 2009-06-19 14:22:16 UTC (rev 612) @@ -923,6 +923,8 @@ { "Tyan", "S5376G2NR/S5376WAG2NR", }, { "Tyan", "S5377", }, { "Tyan", "S5397", }, + { "VIA", "EPIA-EX15000", }, + { "VIA", "EPIA-NX15000", }, { "VIA", "EPIA-LN", }, { "VIA", "NAB74X0", }, { "VIA", "pc2500e", },

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[PATCH] flashrom: Prevent spurious runs of make features
by Carl-Daniel Hailfinger 19 Jun '09

19 Jun '09

Prevent spurious runs of make features introduced by the FT2232 patch. The new makefile structure uses indirection (.features->features) to work around a gmake bug which resulted in immediate premature evaluation of variable definitions with deferred evaluation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ftdi2232_spi_newmakefile/Makefile =================================================================== --- flashrom-ftdi2232_spi_newmakefile/Makefile (Revision 602) +++ flashrom-ftdi2232_spi_newmakefile/Makefile (Arbeitskopie) @@ -51,7 +51,7 @@ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ dummyflasher.o pcidev.o nic3com.o satasii.o ft2232_spi.o print.o -all: pciutils .features dep $(PROGRAM) +all: pciutils features dep $(PROGRAM) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. @@ -66,7 +66,11 @@ $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) -flashrom.o: flashrom.c +FEATURE_CFLAGS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") + +FEATURE_LIBS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") + +flashrom.o: flashrom.c .features $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) -c -o $@ $< $(SVNDEF) %.o: %.c .features @@ -93,9 +97,7 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -# We don't specify compiler as requirement because the compiler is already -# checked during makefile remake through .features -pciutils: +pciutils: compiler @printf "Checking for pciutils and zlib... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ @@ -108,16 +110,18 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -.features: compiler +.features: features + +features: compiler + @echo "FEATURES := yes" > .features.tmp @printf "Checking for FTDI support... " @$(shell ( echo "#include <ftdi.h>"; \ echo "struct ftdi_context *ftdic = NULL;"; \ echo "int main(int argc, char **argv)"; \ echo "{ return ftdi_init(ftdic); }"; ) > .featuretest.c ) @$(CC) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest $(LIBS) -lftdi >/dev/null 2>&1 && \ - ( echo "found."; echo FEATURE_CFLAGS := -D'FT2232_SPI_SUPPORT=1' > .features.tmp; \ - echo FEATURE_LIBS := -lftdi >> .features.tmp) || \ - ( echo "not found."; echo "" > .features.tmp ) + ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ + ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest @@ -138,7 +142,6 @@ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -.PHONY: all clean distclean dep compiler pciutils export tarball +.PHONY: all clean distclean dep compiler pciutils features export tarball -include .dependencies --include .features -- http://www.hailfinger.org/ Index: flashrom-ftdi2232_spi_newmakefile/Makefile =================================================================== --- flashrom-ftdi2232_spi_newmakefile/Makefile (Revision 602) +++ flashrom-ftdi2232_spi_newmakefile/Makefile (Arbeitskopie) @@ -51,7 +51,7 @@ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ dummyflasher.o pcidev.o nic3com.o satasii.o ft2232_spi.o print.o -all: pciutils .features dep $(PROGRAM) +all: pciutils features dep $(PROGRAM) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. @@ -66,7 +66,11 @@ $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) -flashrom.o: flashrom.c +FEATURE_CFLAGS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") + +FEATURE_LIBS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") + +flashrom.o: flashrom.c .features $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) -c -o $@ $< $(SVNDEF) %.o: %.c .features @@ -93,9 +97,7 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -# We don't specify compiler as requirement because the compiler is already -# checked during makefile remake through .features -pciutils: +pciutils: compiler @printf "Checking for pciutils and zlib... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ @@ -108,16 +110,18 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -.features: compiler +.features: features + +features: compiler + @echo "FEATURES := yes" > .features.tmp @printf "Checking for FTDI support... " @$(shell ( echo "#include <ftdi.h>"; \ echo "struct ftdi_context *ftdic = NULL;"; \ echo "int main(int argc, char **argv)"; \ echo "{ return ftdi_init(ftdic); }"; ) > .featuretest.c ) @$(CC) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest $(LIBS) -lftdi >/dev/null 2>&1 && \ - ( echo "found."; echo FEATURE_CFLAGS := -D'FT2232_SPI_SUPPORT=1' > .features.tmp; \ - echo FEATURE_LIBS := -lftdi >> .features.tmp) || \ - ( echo "not found."; echo "" > .features.tmp ) + ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ + ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest @@ -138,7 +142,6 @@ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -.PHONY: all clean distclean dep compiler pciutils export tarball +.PHONY: all clean distclean dep compiler pciutils features export tarball -include .dependencies --include .features

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[flashrom] r611 - trunk
by svn＠coreboot.org 19 Jun '09

19 Jun '09

Author: hailfinger Date: 2009-06-19 16:20:34 +0200 (Fri, 19 Jun 2009) New Revision: 611 Modified: trunk/Makefile Log: Prevent spurious runs of make features introduced by the FT2232 patch. The new makefile structure uses indirection (.features->features) to work around a gmake bug which resulted in immediate premature evaluation of variable definitions with deferred evaluation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-06-19 13:53:59 UTC (rev 610) +++ trunk/Makefile 2009-06-19 14:20:34 UTC (rev 611) @@ -51,7 +51,7 @@ ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ dummyflasher.o pcidev.o nic3com.o satasii.o ft2232_spi.o print.o -all: pciutils .features dep $(PROGRAM) +all: pciutils features dep $(PROGRAM) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. @@ -66,7 +66,11 @@ $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) -flashrom.o: flashrom.c +FEATURE_CFLAGS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") + +FEATURE_LIBS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") + +flashrom.o: flashrom.c .features $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) -c -o $@ $< $(SVNDEF) %.o: %.c .features @@ -93,9 +97,7 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -# We don't specify compiler as requirement because the compiler is already -# checked during makefile remake through .features -pciutils: +pciutils: compiler @printf "Checking for pciutils and zlib... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ @@ -108,16 +110,18 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -.features: compiler +.features: features + +features: compiler + @echo "FEATURES := yes" > .features.tmp @printf "Checking for FTDI support... " @$(shell ( echo "#include <ftdi.h>"; \ echo "struct ftdi_context *ftdic = NULL;"; \ echo "int main(int argc, char **argv)"; \ echo "{ return ftdi_init(ftdic); }"; ) > .featuretest.c ) @$(CC) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest $(LIBS) -lftdi >/dev/null 2>&1 && \ - ( echo "found."; echo FEATURE_CFLAGS := -D'FT2232_SPI_SUPPORT=1' > .features.tmp; \ - echo FEATURE_LIBS := -lftdi >> .features.tmp) || \ - ( echo "not found."; echo "" > .features.tmp ) + ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ + ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest @@ -138,7 +142,6 @@ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -.PHONY: all clean distclean dep compiler pciutils export tarball +.PHONY: all clean distclean dep compiler pciutils features export tarball -include .dependencies --include .features

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[flashrom] r610 - trunk
by svn＠coreboot.org 19 Jun '09

19 Jun '09

Author: libv Date: 2009-06-19 15:53:59 +0200 (Fri, 19 Jun 2009) New Revision: 610 Modified: trunk/board_enable.c Log: Board enable for EPIA-N(L). Signed-off-by: Jon Harrison <bothlyn(a)blueyonder.co.uk> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-06-19 13:00:24 UTC (rev 609) +++ trunk/board_enable.c 2009-06-19 13:53:59 UTC (rev 610) @@ -182,17 +182,22 @@ uint16_t base; uint8_t val, bit; - if ((gpio < 12) || (gpio > 15)) { + if ((gpio >= 12) && (gpio <= 15)) { + /* GPIO12-15 -> output */ + val = pci_read_byte(dev, 0xE4); + val |= 0x10; + pci_write_byte(dev, 0xE4, val); + } else if (gpio == 9) { + /* GPIO9 -> Output */ + val = pci_read_byte(dev, 0xE4); + val |= 0x20; + pci_write_byte(dev, 0xE4, val); + } else { fprintf(stderr, "\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); return; } - /* GPIO12-15 -> output */ - val = pci_read_byte(dev, 0xE4); - val |= 0x10; - pci_write_byte(dev, 0xE4, val); - /* Now raise/drop the GPIO line itself. */ bit = 0x01 << (gpio - 8); @@ -270,6 +275,28 @@ } /** + * Suited for VIAs EPIA N & NL. + */ +static int board_via_epia_n(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); + return -1; + } + + /* All memory cycles, not just ROM ones, go to LPC */ + vt823x_set_all_writes_to_lpc(dev); + + /* GPIO9 -> output */ + vt823x_gpio_set(dev, 9, 1); + + return 0; +} + +/** * Suited for EPoX EP-8K5A2 and Albatron PM266A. */ static int board_epox_ep_8k5a2(const char *name) @@ -819,6 +846,7 @@ {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */ {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, "via", "pc3500g", "VIA", "PC3500G", it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */

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coreboot June 2009