coreboot May 2009

coreboot@coreboot.org

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571 discussions

[flashrom] r456 - tags
by svn＠coreboot.org 04 May '09

04 May '09

Author: hailfinger Date: 2009-05-04 14:23:25 +0200 (Mon, 04 May 2009) New Revision: 456 Added: tags/flashrom-0.9.0/ Log: flashrom 0.9.0 tag Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se>

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[flashrom] r455 - /
by svn＠coreboot.org 04 May '09

04 May '09

Author: hailfinger Date: 2009-05-04 14:22:27 +0200 (Mon, 04 May 2009) New Revision: 455 Added: tags/ Log: Create a tags directory for flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>

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[flashrom] r454 - trunk
by svn＠coreboot.org 04 May '09

04 May '09

Author: hailfinger Date: 2009-05-04 14:18:10 +0200 (Mon, 04 May 2009) New Revision: 454 Modified: trunk/Makefile trunk/flashrom.c Log: flashrom 0.9.0 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-05-03 23:33:05 UTC (rev 453) +++ trunk/Makefile 2009-05-04 12:18:10 UTC (rev 454) @@ -38,10 +38,8 @@ all: pciutils dep $(PROGRAM) -# Set the flashrom version string from the highest revision number -# of the checked out flashrom files. -SVNDEF := -D'FLASHROM_VERSION="$(shell svnversion -cn . \ - | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' +# Set the flashrom version string +SVNDEF := -D'FLASHROM_VERSION="0.9.0"' $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-03 23:33:05 UTC (rev 453) +++ trunk/flashrom.c 2009-05-04 12:18:10 UTC (rev 454) @@ -326,7 +326,7 @@ void print_version(void) { - printf("flashrom r%s\n", FLASHROM_VERSION); + printf("flashrom v%s\n", FLASHROM_VERSION); } int main(int argc, char *argv[])

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[flashrom] r453 - trunk
by svn＠coreboot.org 04 May '09

04 May '09

Author: stuge Date: 2009-05-04 01:33:05 +0200 (Mon, 04 May 2009) New Revision: 453 Modified: trunk/README Log: Complement the README file with build instructions for the platforms it currently compiles on. Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/README =================================================================== --- trunk/README 2009-05-01 16:34:32 UTC (rev 452) +++ trunk/README 2009-05-03 23:33:05 UTC (rev 453) @@ -15,12 +15,21 @@ Build Requirements ------------------ -To build the flashrom utility you need to install the following packages: +To build the flashrom utility you need to install the following packages or +ports: +Linux et al: * pciutils * pciutils-devel / pciutils-dev / libpci-dev * zlib-devel / zlib1g-dev +On FreeBSD, you need the following ports: +* devel/gmake +* devel/libpci + +To compile on FreeBSD, use the command below: +gmake + To compile on Solaris, use the commands below: gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" CFLAGS=-O2

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coreboot-sdk
by Roger Treat 03 May '09

03 May '09

Is there anywhere to get the sdk software other than cwlinux?

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linux OS installation through FILO/coreboot
by Baski 03 May '09

03 May '09

Hi, Has anyone tried Linux OS installation on coreboot with FILO? If yes, any hints or how-to? TIA - Baski

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[BuildROM] r265 - buildrom-devel/config/platforms
by svn＠coreboot.org 03 May '09

03 May '09

Author: ward Date: 2009-05-03 16:27:08 +0200 (Sun, 03 May 2009) New Revision: 265 Modified: buildrom-devel/config/platforms/alix2c3.conf Log: Bump up v3 rev to head. Boot tested. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/alix2c3.conf =================================================================== --- buildrom-devel/config/platforms/alix2c3.conf 2009-05-03 14:25:54 UTC (rev 264) +++ buildrom-devel/config/platforms/alix2c3.conf 2009-05-03 14:27:08 UTC (rev 265) @@ -18,7 +18,7 @@ COREBOOT_VENDOR=pcengines COREBOOT_BOARD=alix2c3 -CBV3_TAG=682 +CBV3_TAG=1165 # FILO configuration

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[BuildROM] r264 - buildrom-devel/packages/filo
by svn＠coreboot.org 03 May '09

03 May '09

Author: ward Date: 2009-05-03 16:25:54 +0200 (Sun, 03 May 2009) New Revision: 264 Modified: buildrom-devel/packages/filo/filo.mk Log: Bump up filo to the latest rev. Boot tested on alix.2c3. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/packages/filo/filo.mk =================================================================== --- buildrom-devel/packages/filo/filo.mk 2009-04-08 15:26:59 UTC (rev 263) +++ buildrom-devel/packages/filo/filo.mk 2009-05-03 14:25:54 UTC (rev 264) @@ -1,5 +1,5 @@ FILO_URL=svn://coreboot.org/filo/trunk/filo -FILO_TAG=85 +FILO_TAG=94 FILO_DIR=$(BUILD_DIR)/filo FILO_SRC_DIR=$(FILO_DIR)/svn

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[PATCH] i82801xx assign PIRQs in mainboard Config.lb or use default
by Joseph Smith 02 May '09

02 May '09

This patch lets you assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c. Once and if everyone converts to the better way of assign PIRQs in mainboard Config.lb the option of using the defaults can be removed. The patch enables a margin of time to do so. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[v2] r4251 - trunk/coreboot-v2/src/southbridge/intel/i82801xx
by svn＠coreboot.org 02 May '09

02 May '09

Author: linux_junkie Date: 2009-05-02 23:30:57 +0200 (Sat, 02 May 2009) New Revision: 4251 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c Log: Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-02 12:42:30 UTC (rev 4250) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-05-02 21:30:57 UTC (rev 4251) @@ -31,6 +31,18 @@ #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H struct southbridge_intel_i82801xx_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; }; extern struct chip_operations southbridge_intel_i82801xx_ops; Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-05-02 12:42:30 UTC (rev 4250) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-05-02 21:30:57 UTC (rev 4251) @@ -36,6 +36,8 @@ #define NMI_OFF 0 +typedef struct southbridge_intel_i82801xx_config config_t; + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -66,7 +68,11 @@ #define PIRQG 0x0A #define PIRQH 0x0B -/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */ +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. + * Use the defined IRQ values above or set mainboard + * specific IRQ values in your mainboards Config.lb. +*/ void i82801xx_enable_apic(struct device *dev) { @@ -114,18 +120,59 @@ static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) { - /* Route PIRQA - PIRQD. */ - pci_write_config8(dev, PIRQA_ROUT, PIRQA); - pci_write_config8(dev, PIRQB_ROUT, PIRQB); - pci_write_config8(dev, PIRQC_ROUT, PIRQC); - pci_write_config8(dev, PIRQD_ROUT, PIRQD); + /* Get the chip configuration */ + config_t *config = dev->chip_info; + if (config->pirqa_routing) { + pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); + } else { + pci_write_config8(dev, PIRQA_ROUT, PIRQA); + } + + if (config->pirqb_routing) { + pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); + } else { + pci_write_config8(dev, PIRQB_ROUT, PIRQB); + } + + if (config->pirqc_routing) { + pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); + } else { + pci_write_config8(dev, PIRQC_ROUT, PIRQC); + } + + if (config->pirqd_routing) { + pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); + } else { + pci_write_config8(dev, PIRQD_ROUT, PIRQD); + } + /* Route PIRQE - PIRQH (for ICH2-ICH9). */ if (ich_model >= 0x2440) { - pci_write_config8(dev, PIRQE_ROUT, PIRQE); - pci_write_config8(dev, PIRQF_ROUT, PIRQF); - pci_write_config8(dev, PIRQG_ROUT, PIRQG); - pci_write_config8(dev, PIRQH_ROUT, PIRQH); + + if (config->pirqe_routing) { + pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); + } else { + pci_write_config8(dev, PIRQE_ROUT, PIRQE); + } + + if (config->pirqf_routing) { + pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); + } else { + pci_write_config8(dev, PIRQF_ROUT, PIRQF); + } + + if (config->pirqg_routing) { + pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); + } else { + pci_write_config8(dev, PIRQG_ROUT, PIRQG); + } + + if (config->pirqh_routing) { + pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); + } else { + pci_write_config8(dev, PIRQH_ROUT, PIRQH); + } } }

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coreboot May 2009