coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

[flashrom] r447 - trunk
by svn＠coreboot.org 01 May '09

01 May '09

Author: hailfinger Date: 2009-05-01 12:53:49 +0200 (Fri, 01 May 2009) New Revision: 447 Modified: trunk/flashrom.8 trunk/flashrom.c Log: Since the command line interface for flashrom will change for 1.0 (all-caps or no-caps for short options, exclude range syntax, etc.) we should tell users in the man page and the usage message about this. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-04-29 23:22:33 UTC (rev 446) +++ trunk/flashrom.8 2009-05-01 10:53:49 UTC (rev 447) @@ -17,6 +17,11 @@ .B http://coreboot.org for details on coreboot) .SH OPTIONS +Please note that the command line interface for flashrom will change before +flashrom 1.0. Do not use flashrom in scripts or other automated tools without +checking that your flashrom version won't interpret them in a totally different +way. +.PP If no file is specified, then all that happens is that flash info is dumped and the flash chip is set to writable. .TP Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-04-29 23:22:33 UTC (rev 446) +++ trunk/flashrom.c 2009-05-01 10:53:49 UTC (rev 447) @@ -306,6 +306,10 @@ printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n", name); printf(" [-e exclude_end] [-m [vendor:]part] [-l file.layout] [-i imagename] [file]\n"); + printf("Please note that the command line interface for flashrom will " + "change before flashrom 1.0. Do not use flashrom in scripts or " + "other automated tools without checking that your flashrom " + "version won't interpret them in a totally different way.\n\n"); printf (" -r | --read: read flash and save into file\n" " -w | --write: write file into flash\n"

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Re: [coreboot] SeaBIOS and hp dl145g3
by Myles Watson 01 May '09

01 May '09

On Thu, Apr 30, 2009 at 9:07 AM, samuel <samuel.verstraete(a)gmail.com> wrote: > On Thu, Apr 30, 2009 at 2:43 AM, Kevin O'Connor <kevin(a)koconnor.net> wrote: >> On Wed, Apr 29, 2009 at 04:53:13PM +0200, samuel wrote: >>> Hi Kevin, >>> >>> I have tried Seabios on my hp dl145 g3 (the patches from mondrian) and >>> it works really well now >>> I was able to load the vga rom and i have output on the screen. >> >> Great! >> >>> One single problem... It doesn't seem to find the sata controller... >>> >>> bootlog with coreboot and seabios: >>> http://merlin.ugent.be/~samuel/dl145g3/corebootwithseabios.log >> >> There isn't much SeaBIOS info in that log - can you recompile with >> CONFIG_DEBUG_LEVEL set to 6? > > did that: see http://merlin.ugent.be/~samuel/dl145g3/coreboot_seabios_DEBUG6.log > >> >>> >>> lspci -vnn : http://merlin.ugent.be/~samuel/dl145g3/info/lspci-vnn.txt 01:0e.0 RAID bus controller [0104]: Broadcom BCM5785 [HT1000] SATA (Native SATA Mode) [1166:024a] (prog-if 05) http://pci-ids.ucw.cz/read/PC/1166/024b says: The device starts as 024a, and changes to 024b if set to PATA mode in BIOS >>> You have any ideas how i could quickly add support for the hp dl145 g3 >>> to SeaBIOS?? >> >> The equivalent patch in SeaBIOS would look like: >> >> --- a/src/ata.c >> +++ b/src/ata.c >> @@ -841,7 +845,8 @@ ata_init() >> int count=0; >> int bdf, max; >> foreachpci(bdf, max) { >> - if (pci_config_readw(bdf, PCI_CLASS_DEVICE) != PCI_CLASS_STORAGE_IDE) >> + u16 class = pci_config_readw(bdf, PCI_CLASS_DEVICE); >> + if (class != PCI_CLASS_STORAGE_IDE && class != PCI_CLASS_STORAGE_RAID) >> continue; >> if (count >= ARRAY_SIZE(ATA.channels)) >> break; This forces SeaBIOS to see it as a PATA controller, but it's in SATA mode. Kevin, Is there an easy way to add SATA support to SeaBIOS? It sounds like a bit of work. It looks like you could force the device to be in PATA mode, but once it's booted that's not ideal. Maybe there's another option we haven't thought of. Thanks, Myles

3 3

Re: [coreboot] unexpected exception errors loading vga rom
by Joseph Smith 01 May '09

01 May '09

On Mon, 27 Apr 2009 10:14:02 +0200, Stefan Reinauer <stepan(a)coresystems.de> wrote: > On 27.04.2009 9:55 Uhr, Joseph Smith wrote: >> Well, I have confirmed the problem. Looks there is something crazy about >> how the ethernet and modem (even though the IP1000 doesn't actually have > a >> modem) are setup. If I disable the ICH4 ethernet and enable the AC97 > ICH4 >> modem, sure as shit it boots up everytime (VGA too) and all IRQS look >> great. If I enable both of them EVERYTHING gets IRQ 0, and I have > issues. >> If I enable ethernet and disable the modem (this is the way it should > be) >> EVERYTHING gets IRQ 0, and I have issues..... >> >> Anyone seen this kind of thing before? I have no idea how to fix this >> one.... >> >> Well now were getting somewhere. It is as I thought. The modem and Ethernet were not playing nice causing io read/write issues under 0x200, hence the unexpected exception errors. The IRQ 0 problems also make sense because the interrupt controllers live in that io area correct? I guess on this board they were not designed to coincide...there isn't an actual on-board modem anyways. So here is what I did to get it working, and this is the part I need help with. 1. In auto.c I disabled the modem right off through the LPC device: /* Set the LPC device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x0); /* Disable Modem. */ pci_write_config8(dev, 0xf2, 0x40); 2. I completely removed the modem code from src/mainboard/thomson/ip1000/Config.lb - device pci 1f.6 off end # AC'97 modem 3. Then I completely removed the modem code from src/southbridge/intel/i82801xx/i82801xx_ac97.c -static const struct pci_driver i82801db_ac97_modem __pci_driver = { - .ops = &ac97_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM, -}; And boom :-) I am booting like a rocket ship in action:-) I have tried Just step 1 with no luck, and step 1 & 2 with no luck. So even with the device disabled via the LPC and coreboot something from the i82801db_ac97_modem() is still partially initializing causing this io crazyness. I can submit a patch for steps 1-2 but....my question is how can I completely disable the i82801db_ac97_modem() driver without having to manually delete code every time I use a new revision??? Maybe a #ifdef to global disable modem define??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

5 25

[v2] r4246 - trunk/coreboot-v2/src/southbridge/intel/i82801xx
by svn＠coreboot.org 01 May '09

01 May '09

Author: linux_junkie Date: 2009-05-01 06:53:58 +0200 (Fri, 01 May 2009) New Revision: 4246 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c Log: This is a patch to use another IRQ besides IRQ12 to fix conflicts with i8042 - PS/2 Mouse. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-05-01 04:44:36 UTC (rev 4245) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2009-05-01 04:53:58 UTC (rev 4246) @@ -58,14 +58,16 @@ */ #define PIRQA 0x03 -#define PIRQB 0x05 -#define PIRQC 0x06 -#define PIRQD 0x07 -#define PIRQE 0x09 -#define PIRQF 0x0A -#define PIRQG 0x0B -#define PIRQH 0x0C +#define PIRQB 0x04 +#define PIRQC 0x05 +#define PIRQD 0x06 +#define PIRQE 0x07 +#define PIRQF 0x09 +#define PIRQG 0x0A +#define PIRQH 0x0B +/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */ + void i82801xx_enable_apic(struct device *dev) { uint32_t reg32;

1 0

[PATCH] Change default rom emulator to VM86 on IP1000 and RM4100
by Joseph Smith 01 May '09

01 May '09

This patch changes the default rom emulator to VM86 on IP1000 and RM4100 (it is much faster than x86emu or YABEL). Signed-off-by: Joesph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 2

[v2] r4245 - in trunk/coreboot-v2: src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/rca/rm4100 targets/thomson/ip1000
by svn＠coreboot.org 01 May '09

01 May '09

Author: linux_junkie Date: 2009-05-01 06:44:36 +0200 (Fri, 01 May 2009) New Revision: 4245 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb trunk/coreboot-v2/targets/rca/rm4100/Config.lb trunk/coreboot-v2/targets/thomson/ip1000/Config.lb Log: This patch changes the default rom emulator to VM86. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-05-01 04:37:13 UTC (rev 4244) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-05-01 04:44:36 UTC (rev 4245) @@ -24,6 +24,7 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_IOAPIC +uses CONFIG_PCI_OPTION_ROM_RUN_VM86 uses CONFIG_PCI_ROM_RUN uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START @@ -78,6 +79,7 @@ default HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0 default CONFIG_VIDEO_MB = 0 default STACK_SIZE = 0x2000 default HEAP_SIZE = 0x4000 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-05-01 04:37:13 UTC (rev 4244) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-05-01 04:44:36 UTC (rev 4245) @@ -24,6 +24,7 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_IOAPIC +uses CONFIG_PCI_OPTION_ROM_RUN_VM86 uses CONFIG_PCI_ROM_RUN uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START @@ -78,6 +79,7 @@ default HAVE_OPTION_TABLE = 0 default CONFIG_CONSOLE_VGA = 0 default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_PCI_OPTION_ROM_RUN_VM86 = 0 default CONFIG_VIDEO_MB = 0 default STACK_SIZE = 0x2000 default HEAP_SIZE = 0x4000 Modified: trunk/coreboot-v2/targets/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/targets/rca/rm4100/Config.lb 2009-05-01 04:37:13 UTC (rev 4244) +++ trunk/coreboot-v2/targets/rca/rm4100/Config.lb 2009-05-01 04:44:36 UTC (rev 4245) @@ -37,6 +37,7 @@ ## option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 +option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1 ## ## Choose the amount of memory pre-allocated for VGA Modified: trunk/coreboot-v2/targets/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-01 04:37:13 UTC (rev 4244) +++ trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-01 04:44:36 UTC (rev 4245) @@ -37,6 +37,7 @@ ## option CONFIG_CONSOLE_VGA = 1 option CONFIG_PCI_ROM_RUN = 1 +option CONFIG_PCI_OPTION_ROM_RUN_VM86 = 1 ## ## Choose the amount of memory pre-allocated for VGA

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Set Top Boxes and composite (!) video out
by Gregg C Levine 01 May '09

01 May '09

Hello! Joseph I've been following your progress regarding these examples, both on your site, and here. I have some to ask question: First; have you gotten to the point of being able to present any composite video out on that connector? Second; where did you obtain these units? Every time I check Amazon for them I get shocked by the prices they are quoting, it's as if they are trying to sell me a brand new never been opened first edition of something. And yes I'll accept an answer off list if you feel that's best. -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

2 2

[v2] r4244 - trunk/coreboot-v2/src/northbridge/intel/i82830
by svn＠coreboot.org 01 May '09

01 May '09

Author: linux_junkie Date: 2009-05-01 06:37:13 +0200 (Fri, 01 May 2009) New Revision: 4244 Added: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb Log: This patch allows a custom vga driver that will give the flexibility to run code after vga is initialized for tv-out. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb 2009-05-01 04:36:38 UTC (rev 4243) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/Config.lb 2009-05-01 04:37:13 UTC (rev 4244) @@ -23,5 +23,6 @@ config chip.h driver northbridge.o +driver vga.o default HAVE_HIGH_TABLES=1 Added: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c 2009-05-01 04:37:13 UTC (rev 4244) @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Joseph Smith <joe(a)settoplinux.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void vga_init(device_t dev) { + + printk_info("Starting Graphics Initialization\n"); + pci_dev_init(dev); + printk_info("Graphics Initialization Complete\n"); + /* Future TV-OUT code will be called from here. */ +} + +static const struct device_operations vga_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vga_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver vga_driver __pci_driver = { + .ops = &vga_operations, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x3577, +}; Property changes on: trunk/coreboot-v2/src/northbridge/intel/i82830/vga.c ___________________________________________________________________ Added: svn:executable + *

1 0

[v2] r4243 - in trunk/coreboot-v2/src/mainboard: amd/pistachio amd/serengeti_cheetah arima/hdama asus/a8n_e asus/a8v-e_se asus/m2v-mx_se broadcom/blast gigabyte/m57sli ibm/e325 ibm/e326 iwill/dk8_htx iwill/dk8s2 iwill/dk8x newisys/khepri supermicro/h8dme supermicro/h8dmr tyan/s2735 tyan/s2875 tyan/s2882 tyan/s2885 tyan/s2895 tyan/s4882
by svn＠coreboot.org 01 May '09

01 May '09

Author: myles Date: 2009-05-01 06:36:38 +0200 (Fri, 01 May 2009) New Revision: 4243 Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout Log: Trivial patch to make #defines generated from cmos.layout have unique names. Kills a few more compiler warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -67,7 +67,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -45,7 +45,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers - 1000 24 r 0 reserved_memory + 1000 24 r 0 reserved_memory1 enumerations Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -67,7 +67,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -67,7 +67,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -67,7 +67,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -44,7 +44,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1 Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-05-01 03:04:20 UTC (rev 4242) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cmos.layout 2009-05-01 04:36:38 UTC (rev 4243) @@ -46,7 +46,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 reserved_memory1

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[v2] r4242 - in trunk/coreboot-v2/src/mainboard: rca/rm4100 thomson/ip1000
by svn＠coreboot.org 01 May '09

01 May '09

Author: linux_junkie Date: 2009-05-01 05:04:20 +0200 (Fri, 01 May 2009) New Revision: 4242 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c Log: Trivial cosmetic fixes to IP1000 and RM4100 irq_tables.c Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c 2009-05-01 02:24:40 UTC (rev 4241) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/irq_tables.c 2009-05-01 03:04:20 UTC (rev 4242) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe(a)smittys.pointclark.net> + * Copyright (C) 2008 Joseph Smith <joe(a)settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,13 +34,13 @@ 0xcd, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */ - {0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */ - {0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */ - {0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */ - {0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */ - {0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */ - {0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */ + {0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ + {0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ + {0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ + {0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */ + {0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */ + {0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */ + {0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */ } }; Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c 2009-05-01 02:24:40 UTC (rev 4241) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/irq_tables.c 2009-05-01 03:04:20 UTC (rev 4242) @@ -34,13 +34,13 @@ 0xcd, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */ - {0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */ - {0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */ - {0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */ - {0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */ - {0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */ - {0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */ + {0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ + {0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ + {0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ + {0x01,(0x08<<3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */ + {0x01,(0x00<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */ + {0x01,(0x01<<3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */ + {0x01,(0x02<<3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */ } };

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coreboot May 2009