coreboot May 2009

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[flashrom] r459 - trunk
by svn＠coreboot.org 05 May '09

05 May '09

Author: hailfinger Date: 2009-05-05 00:33:50 +0200 (Tue, 05 May 2009) New Revision: 459 Modified: trunk/chipset_enable.c Log: Force enabling SPI mode for SB600 is a bad idea and leads to hangs. Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we boot via SPI ROM. The code to force enable SPI is commented out in case someone wants to reenable it for a particular board with LPC and SPI flash. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-04 21:03:59 UTC (rev 458) +++ trunk/chipset_enable.c 2009-05-04 22:33:50 UTC (rev 459) @@ -680,8 +680,16 @@ flashbus = BUS_TYPE_SB600_SPI; /* Enable SPI ROM in SB600 PM register. */ + /* If we enable SPI ROM here, we have to disable it after we leave. + * But how can we know which ROM we are going to handle? So we have + * to trade off. We only access LPC ROM if we boot via LPC ROM. And + * only SPI ROM if we boot via SPI ROM. If you want to do it crossly, + * you have to use the code below. + */ + /* OUTB(0x8f, 0xcd6); OUTB(0x0e, 0xcd7); + */ return 0; }

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[flashrom] r458 - trunk
by svn＠coreboot.org 04 May '09

04 May '09

Author: stuge Date: 2009-05-04 23:03:59 +0200 (Mon, 04 May 2009) New Revision: 458 Modified: trunk/flashchips.c Log: SST25VF080B TEST_OK_READ Per report from from Henning Fleddermann. Thanks! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-04 12:29:59 UTC (rev 457) +++ trunk/flashchips.c 2009-05-04 21:03:59 UTC (rev 458) @@ -1204,7 +1204,7 @@ .model_id = SST_25VF080B, .total_size = 1024, .page_size = 256, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PR, .probe = probe_spi_rdid, .erase = spi_chip_erase_60_c7, .write = spi_chip_write,

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Re: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
by ron minnich 04 May '09

04 May '09

> + > +#if HAVE_ACPI_RESUME == 1 > + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ > + clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); > +#else > clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); > - > +#endif > } > here is a suggestion. replace all this with: /* clear the coreboot memory */ clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); /* We need to sync up ECC tags if this is a power-on or reset */ /* we should have a clean way to test this but, for now, we'll just always do it. * Note: fixing this in the right way will speed up resume substantially. */ /* init all non-coreboot memory ECC tags */ memcpy(non-lb-memory-pointer, non-lb-memory-pointer, non-lb-memory-size); I will leave it to you to fill in the blanks. Please, no #ifdef around this very important piece of code. Let's not put in changes that we *know* will break boards :-) ron

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[ANNOUNCE] flashrom 0.9.0 has been released!
by Carl-Daniel Hailfinger 04 May '09

04 May '09

The flashrom developers are happy to announce the release of flashrom 0.9.0. flashrom is a utility for reading, writing, erasing and verifying flash ROM chips. flashrom is often used to flash BIOS/coreboot/firmware images because it allows you to update your BIOS/coreboot/firmware without opening the computer and without any special boot procedures. After nine years of development and constant improvement, we have added support for every BIOS flash ROM technology present on x86 mainboards and every flash ROM chip we ever saw in the wild. Highlights of flashrom include: - Parallel, LPC, FWH and SPI flash interfaces. - 157 flash chip families and half a dozen variants of each family. - Flash chip package agnostic. DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40 and more have all been verified to work. - 75 different chipsets, some with multiple flash controllers. - Special mainboard enabling code for dozens of nonstandard mainboards. - No physical access needed. root access is sufficient. - No bootable floppy disk, bootable CD-ROM or other media needed. - No keyboard or monitor needed. Simply reflash remotely via SSH. - No instant reboot needed. Reflash your ROM in a running system, verify it, be happy. The new firmware will be present next time you boot. - Crossflashing and hotflashing is possible as long as the flash chips are electrically and logically compatible (same protocol). Great for recovery. - Scriptability. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes. - Speed. flashrom is much faster than vendor flash tools. - Supports Linux, FreeBSD, DragonFly BSD, Solaris, Mac OS X. Please refer to the README for build instructions. Thanks go to everyone who contributed to flashrom over the years and especially to Li-Ta Lo for starting this project. Please note that rewriting your flash chip can be dangerous and flashrom developers make no guarantees whatsoever. That said, many users have successfully replaced proprietary tools such as awdflash, amiflash and afudos with flashrom. flashrom has its own home page at http://coreboot.org/flashrom flashrom 0.9.0 can be downloaded in various ways: Anonymous checkout from the subversion repository at svn://coreboot.org/flashrom/tags/flashrom-0.9.0 Tarball download at http://qa.coreboot.org/releases/flashrom-0.9.0.tar.gz http://qa.coreboot.org/releases/flashrom-0.9.0.tar.bz2 with GPG signatures at http://qa.coreboot.org/releases/flashrom-0.9.0.tar.{gz,bz2}.asc

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[PATCH] Build warnings
by Myles Watson 04 May '09

04 May '09

This patch removes these warnings: Makefile:435: warning: overriding commands for target `src/lib/memset.o' And replaces these debug messages: partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8> part pci_domain with: partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part pci_domain The warnings come about because some object files are used INITOBJECTS and OBJECTS. They get written to the makefile twice. I factored out a function that writes the rules, then only write out the rules that haven't been written. The debugging messages is personal taste, so if someone really objects I'll leave that part out. Abuild tested. The makefiles are identical except for the missing duplicates. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4253 - trunk/coreboot-v2/util/newconfig
by svn＠coreboot.org 04 May '09

04 May '09

Author: myles Date: 2009-05-04 22:27:09 +0200 (Mon, 04 May 2009) New Revision: 4253 Modified: trunk/coreboot-v2/util/newconfig/config.g Log: This patch removes these warnings: Makefile:435: warning: overriding commands for target `src/lib/memset.o' And replaces these debug messages: partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8> part pci_domain with: partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part pci_domain Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-05-04 19:26:43 UTC (rev 4252) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-05-04 20:27:09 UTC (rev 4253) @@ -323,6 +323,22 @@ return fatal("No such rule \"%s\" for addmakedepend" % id) + def addmakeobject(self, file, obj): + source = topify(obj[1]) + type = obj[2] + if (type == 'S'): + # for .S, .o depends on .s + file.write("%s: %s.s\n" % (obj[0], obj[3])) + file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n") + # and .s depends on .S + file.write("%s.s: %s\n" % (obj[3], source)) + # Note: next 2 lines are ONE output line! + file.write("\t$(CPP) $(CPPFLAGS) $< ") + file.write(">$@.new && mv $@.new $@\n") + else: + file.write("%s: %s\n" % (obj[0], source)) + file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n") + # this is called with an an object name. # the easiest thing to do is add this object to the current # component. @@ -608,8 +624,12 @@ class partobj: """A configuration part""" def __init__ (self, image, dir, parent, part, type_name, instance_name, chip_or_device): - debug.info(debug.object, "partobj dir %s parent %s part %s" \ - % (dir, parent, part)) + if (parent): + debug.info(debug.object, "partobj dir %s parent %s part %s" \ + % (dir, parent.instance_name, part)) + else: + debug.info(debug.object, "partobj dir %s part %s" \ + % (dir, part)) # romimage that is configuring this part self.image = image @@ -2166,38 +2186,15 @@ file.write("\n# initobjectrules:\n") for irule, init in image.getinitobjectrules().items(): - source = topify(init[1]) - type = init[2] - if (type == 'S'): - # for .S, .o depends on .s - file.write("%s: %s.s\n" % (init[0], init[3])) - file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n") - # and .s depends on .S - file.write("%s.s: %s\n" % (init[3], source)) - # Note: next 2 lines are ONE output line! - file.write("\t$(CPP) $(CPPFLAGS) $< ") - file.write(">$@.new && mv $@.new $@\n") - else: - file.write("%s: %s\n" % (init[0], source)) - file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n") + image.addmakeobject(file, init); - file.write("\n# objectrules:\n") + file.write("\n# objectrules (don't duplicate initobjects):\n") for objrule, obj in image.getobjectrules().items(): - source = topify(obj[1]) - type = obj[2] - if (type == 'S'): - # for .S, .o depends on .s - file.write("%s: %s.s\n" % (obj[0], obj[3])) - file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n") - # and .s depends on .S - file.write("%s.s: %s\n" % (obj[3], source)) - # Note: next 2 lines are ONE output line! - file.write("\t$(CPP) $(CPPFLAGS) $< ") - file.write(">$@.new && mv $@.new $@\n") + + if (getdict(image.getinitobjectrules(), obj[3])): + debug.info(debug.object, "skipping %s" % (obj[3])) else: - file.write("%s: %s\n" % (obj[0], source)) - file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n") - #file.write("%s\n" % objrule[2]) + image.addmakeobject(file, obj); for driverrule, driver in image.getdriverrules().items(): source = topify(driver[1]) @@ -2207,20 +2204,7 @@ file.write("\n# smmobjectrules:\n") for irule, smm in image.getsmmobjectrules().items(): - source = topify(smm[1]) - type = smm[2] - if (type == 'S'): - # for .S, .o depends on .s - file.write("%s: %s.s\n" % (smm[0], smm[3])) - file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n") - # and .s depends on .S - file.write("%s.s: %s\n" % (smm[3], source)) - # Note: next 2 lines are ONE output line! - file.write("\t$(CPP) $(CPPFLAGS) $< ") - file.write(">$@.new && mv $@.new $@\n") - else: - file.write("%s: %s\n" % (smm[0], source)) - file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n") + image.addmakeobject(file, smm); # special rule for chip_target.c file.write("static.o: static.c\n")

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Re: [coreboot] [v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
by Myles Watson 04 May '09

04 May '09

On Mon, May 4, 2009 at 1:26 PM, <svn(a)coreboot.org> wrote: > Author: ruik > Date: 2009-05-04 21:26:43 +0200 (Mon, 04 May 2009) > New Revision: 4252 > > Modified: > trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c > Log: > The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted this change. > I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;). Did you try Ron's suggestion of reading and writing the memory instead of clearing it? I'd prefer a solution without an #if. If that's not feasible I think the comment is too weak. Note: This breaks ECC boards. Thanks, Myles > Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> > Acked-by: Rudolf Marek <r.marek(a)assembler.cz> > > > > Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c > =================================================================== > --- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-05-02 21:30:57 UTC (rev 4251) > +++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-05-04 19:26:43 UTC (rev 4252) > @@ -6,8 +6,13 @@ > // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram > // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already > // so noline clear_init_ram > + > +#if HAVE_ACPI_RESUME == 1 > + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ > + clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); > +#else > clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); > - > +#endif > } > > /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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[v2] r4252 - trunk/coreboot-v2/src/cpu/amd/car
by svn＠coreboot.org 04 May '09

04 May '09

Author: ruik Date: 2009-05-04 21:26:43 +0200 (Mon, 04 May 2009) New Revision: 4252 Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c Log: The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted this change. I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-05-02 21:30:57 UTC (rev 4251) +++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-05-04 19:26:43 UTC (rev 4252) @@ -6,8 +6,13 @@ // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram + +#if HAVE_ACPI_RESUME == 1 + /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ + clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); +#else clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); - +#endif } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/

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[PATCH] Free VGA BIOS for K8M890
by Rudolf Marek 04 May '09

04 May '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I managed to catch all I/O for init of K8M890 IGP. Attached patch is for http://www.nongnu.org/vgabios/. With a patch one can have a console and some VGA resolutions also might work. It is just a interesting result. I used libx86 library to catch all IO. It was quite painful until I realize that the emulator cannot handle properly opcodes like 0x66 0xe8 .. .. 0xff 0xff and also mov al,cs:[ebx] which I get caught in Sebios int 15 routine. I somehow managed to fix the emulator (only hacks) and patched the IO backend of emulator and obtained following tracedump: OUTB to 3c3 is 1 OUTW to 3c4 is 32 OUTB to 3c4 is 10 INB from 3c5 is 0 OUTB to 3c5 is 1 OUTL to cf8 is 80010000 INL from cfc is 32301106 OUTB to 3c4 is 2d INB from 3c5 is aa OUTB to 3c5 is bf OUTW to 3c4 is 816 ... and other ~250 lines Those were just directly transformed with bash script to IO calls in patch. The BIOS works, it even sets the memory speed grade, but not the mem size to scratch registers (it uses SeaBIOS VIA vga hooks for this) I can boot X without any problems, Windows 7 boots with VGAfailsafe driver and 16 colors ;) If someone ever want to write somethink like SeaBIOS but for VGA here is the chance (I dont have time :/) What is important, some bits in this init fixes also the problem with PowerNow which I had until VGA option rom was run. There must be smth set which enables the HT deliver stop grants or smth like this again. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAknzF6MACgkQ3J9wPJqZRNUwvQCgxCqJxqHZ4fuUgo7dVIdhj7JA zxwAn3bKtyZdyfn3LJFFuI02f5vGPjoQ =60ml -----END PGP SIGNATURE-----

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[flashrom] r457 - trunk
by svn＠coreboot.org 04 May '09

04 May '09

Author: hailfinger Date: 2009-05-04 14:29:59 +0200 (Mon, 04 May 2009) New Revision: 457 Modified: trunk/Makefile Log: Onwards with development. Re-add the svn revision to the version string. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-05-04 12:23:25 UTC (rev 456) +++ trunk/Makefile 2009-05-04 12:29:59 UTC (rev 457) @@ -38,8 +38,10 @@ all: pciutils dep $(PROGRAM) -# Set the flashrom version string -SVNDEF := -D'FLASHROM_VERSION="0.9.0"' +# Set the flashrom version string from the highest revision number +# of the checked out flashrom files. +SVNDEF := -D'FLASHROM_VERSION="0.9.0-r$(shell svnversion -cn . \ + | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/")"' $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)

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coreboot May 2009