May 2009 - coreboot - mail.coreboot.org

[PATCH] flashrom: Rewrite SB600 chipset enable function
by Carl-Daniel Hailfinger May 6, 2009

May 6, 2009

Rewrite the SB600 chipset enable function: - Check for read/write protected regions first. - Region protection is write-once according to the data sheets. Check if the write succeeded. - Verbose region protection dumping. - Improve readability of BAR mapping code. - Align BAR mapping to a page boundary (4k) instead of a 16k boundary. This patch prepares the code for a SPI detection heuristic. Tests are appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-sb600/chipset_enable.c =================================================================== --- flashrom-sb600/chipset_enable.c (Revision 459) +++ flashrom-sb600/chipset_enable.c (Arbeitskopie) @@ -658,33 +658,47 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, low_bits, num; + uint32_t tmp, prot; uint8_t reg; - low_bits = tmp = pci_read_long(dev, 0xa0); - low_bits &= ~0xffffc000; /* for mmap aligning requirements */ - low_bits &= 0xfffffff0; /* remove low 4 bits */ - tmp &= 0xffffc000; - printf_debug("SPI base address is at 0x%x\n", tmp + low_bits); - - sb600_spibar = physmap("SB600 SPI registers", tmp, 0x4000); - sb600_spibar += low_bits; - /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { - num = pci_read_long(dev, reg); - num &= 0xfffffffc; - pci_write_byte(dev, reg, num); + prot = pci_read_long(dev, reg); + if (prot & 0x3) + printf("SB600 %s %s protected from %u to %u\n", + (prot & 0x1) ? "write" : "", + (prot & 0x2) ? "read" : "", + (prot & 0xfffffc00), + (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); + prot &= 0xfffffffc; + pci_write_byte(dev, reg, prot); + prot = pci_read_long(dev, reg); + if (prot & 0x3) + printf("SB600 still %s %s protected from %u to %u\n", + (prot & 0x1) ? "write" : "", + (prot & 0x2) ? "read" : "", + (prot & 0xfffffc00), + (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + printf_debug("SPI base address is at 0x%x\n", tmp); + + /* Physical memory can only be mapped at page (4k) boundaries */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + /* The low bits of the SPI base address are used as offset into the mapped page */ + sb600_spibar += tmp & 0xfff; + flashbus = BUS_TYPE_SB600_SPI; - /* Enable SPI ROM in SB600 PM register. */ - /* If we enable SPI ROM here, we have to disable it after we leave. + /* Force enable SPI ROM in SB600 PM register. + * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have * to trade off. We only access LPC ROM if we boot via LPC ROM. And - * only SPI ROM if we boot via SPI ROM. If you want to do it crossly, - * you have to use the code below. + * only SPI ROM if we boot via SPI ROM. If you want to access SPI on + * boards with LPC straps, you have to use the code below. */ /* OUTB(0x8f, 0xcd6); -- http://www.hailfinger.org/ Index: flashrom-sb600/chipset_enable.c =================================================================== --- flashrom-sb600/chipset_enable.c (Revision 459) +++ flashrom-sb600/chipset_enable.c (Arbeitskopie) @@ -658,33 +658,47 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, low_bits, num; + uint32_t tmp, prot; uint8_t reg; - low_bits = tmp = pci_read_long(dev, 0xa0); - low_bits &= ~0xffffc000; /* for mmap aligning requirements */ - low_bits &= 0xfffffff0; /* remove low 4 bits */ - tmp &= 0xffffc000; - printf_debug("SPI base address is at 0x%x\n", tmp + low_bits); - - sb600_spibar = physmap("SB600 SPI registers", tmp, 0x4000); - sb600_spibar += low_bits; - /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { - num = pci_read_long(dev, reg); - num &= 0xfffffffc; - pci_write_byte(dev, reg, num); + prot = pci_read_long(dev, reg); + if (prot & 0x3) + printf("SB600 %s %s protected from %u to %u\n", + (prot & 0x1) ? "write" : "", + (prot & 0x2) ? "read" : "", + (prot & 0xfffffc00), + (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); + prot &= 0xfffffffc; + pci_write_byte(dev, reg, prot); + prot = pci_read_long(dev, reg); + if (prot & 0x3) + printf("SB600 still %s %s protected from %u to %u\n", + (prot & 0x1) ? "write" : "", + (prot & 0x2) ? "read" : "", + (prot & 0xfffffc00), + (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + printf_debug("SPI base address is at 0x%x\n", tmp); + + /* Physical memory can only be mapped at page (4k) boundaries */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + /* The low bits of the SPI base address are used as offset into the mapped page */ + sb600_spibar += tmp & 0xfff; + flashbus = BUS_TYPE_SB600_SPI; - /* Enable SPI ROM in SB600 PM register. */ - /* If we enable SPI ROM here, we have to disable it after we leave. + /* Force enable SPI ROM in SB600 PM register. + * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have * to trade off. We only access LPC ROM if we boot via LPC ROM. And - * only SPI ROM if we boot via SPI ROM. If you want to do it crossly, - * you have to use the code below. + * only SPI ROM if we boot via SPI ROM. If you want to access SPI on + * boards with LPC straps, you have to use the code below. */ /* OUTB(0x8f, 0xcd6);

2 2

[flashrom] r463 - trunk
by svn＠coreboot.org May 6, 2009

May 6, 2009

Author: hailfinger Date: 2009-05-06 00:50:07 +0200 (Wed, 06 May 2009) New Revision: 463 Modified: trunk/chipset_enable.c Log: Rewrite the SB600 chipset enable function: - Check for read/write protected regions first. - Region protection is write-once according to the data sheets. Check if the write succeeded. Don't write if the region is not protected. - Verbose region protection dumping. - Improve readability of BAR mapping code. - Align BAR mapping to a page boundary (4k) instead of a 16k boundary. This patch prepares the code for a SPI detection heuristic. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-05 21:08:36 UTC (rev 462) +++ trunk/chipset_enable.c 2009-05-05 22:50:07 UTC (rev 463) @@ -658,33 +658,49 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, low_bits, num; + uint32_t tmp, prot; uint8_t reg; - low_bits = tmp = pci_read_long(dev, 0xa0); - low_bits &= ~0xffffc000; /* for mmap aligning requirements */ - low_bits &= 0xfffffff0; /* remove low 4 bits */ - tmp &= 0xffffc000; - printf_debug("SPI base address is at 0x%x\n", tmp + low_bits); - - sb600_spibar = physmap("SB600 SPI registers", tmp, 0x4000); - sb600_spibar += low_bits; - /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { - num = pci_read_long(dev, reg); - num &= 0xfffffffc; - pci_write_byte(dev, reg, num); + prot = pci_read_long(dev, reg); + /* No protection flags for this region?*/ + if ((prot & 0x3) == 0) + continue; + printf_debug("SB600 %s%sprotected from %u to %u\n", + (prot & 0x1) ? "write " : "", + (prot & 0x2) ? "read " : "", + (prot & 0xfffffc00), + (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); + prot &= 0xfffffffc; + pci_write_byte(dev, reg, prot); + prot = pci_read_long(dev, reg); + if (prot & 0x3) + printf("SB600 still %s%sprotected from %u to %u\n", + (prot & 0x1) ? "write " : "", + (prot & 0x2) ? "read " : "", + (prot & 0xfffffc00), + (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ + printf_debug("SPI base address is at 0x%x\n", tmp); + + /* Physical memory can only be mapped at page (4k) boundaries */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); + /* The low bits of the SPI base address are used as offset into the mapped page */ + sb600_spibar += tmp & 0xfff; + flashbus = BUS_TYPE_SB600_SPI; - /* Enable SPI ROM in SB600 PM register. */ - /* If we enable SPI ROM here, we have to disable it after we leave. + /* Force enable SPI ROM in SB600 PM register. + * If we enable SPI ROM here, we have to disable it after we leave. * But how can we know which ROM we are going to handle? So we have * to trade off. We only access LPC ROM if we boot via LPC ROM. And - * only SPI ROM if we boot via SPI ROM. If you want to do it crossly, - * you have to use the code below. + * only SPI ROM if we boot via SPI ROM. If you want to access SPI on + * boards with LPC straps, you have to use the code below. */ /* OUTB(0x8f, 0xcd6);

1 0

[flashrom] r462 - trunk
by svn＠coreboot.org May 5, 2009

May 5, 2009

Author: myles Date: 2009-05-05 23:08:36 +0200 (Tue, 05 May 2009) New Revision: 462 Modified: trunk/chipset_enable.c Log: Here is a fix for chipset_enable.c when there is not /dev/cpu. Open fails so there is no reason to lseek in. Actually this is a trivial fix for a bad return value from open. Signed-off-by: Bertrand Jacquin <beber(a)meleeweb.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-05 16:34:53 UTC (rev 461) +++ trunk/chipset_enable.c 2009-05-05 21:08:36 UTC (rev 462) @@ -511,7 +511,7 @@ unsigned char buf[8]; fd_msr = open("/dev/cpu/0/msr", O_RDWR); - if (!fd_msr) { + if (fd_msr == -1) { perror("open msr"); return -1; }

1 0

Re: [coreboot] [flashrom] r460 - trunk
by Peter Stuge May 5, 2009

May 5, 2009

svn(a)coreboot.org wrote: > Some cosmetics in README and manpage. Thanks! //Peter

1 0

[flashrom] r461 - trunk
by svn＠coreboot.org May 5, 2009

May 5, 2009

Author: stuge Date: 2009-05-05 18:34:53 +0200 (Tue, 05 May 2009) New Revision: 461 Modified: trunk/flashchips.c Log: SST25VF080B TEST_OK_ ERASE WRITE As reported by A. Spamlover. Thanks! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-05 16:15:46 UTC (rev 460) +++ trunk/flashchips.c 2009-05-05 16:34:53 UTC (rev 461) @@ -1204,7 +1204,7 @@ .model_id = SST_25VF080B, .total_size = 1024, .page_size = 256, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .erase = spi_chip_erase_60_c7, .write = spi_chip_write,

1 0

[flashrom] r460 - trunk
by svn＠coreboot.org May 5, 2009

May 5, 2009

Author: uwe Date: 2009-05-05 18:15:46 +0200 (Tue, 05 May 2009) New Revision: 460 Modified: trunk/README trunk/flashrom.8 Log: Some cosmetics in README and manpage. Also, move more stuff to the manpage where it belongs (this also eliminates some duplicated contents). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/README =================================================================== --- trunk/README 2009-05-04 22:33:50 UTC (rev 459) +++ trunk/README 2009-05-05 16:15:46 UTC (rev 460) @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------- flashrom is a utility for reading, writing, verifying and erasing flash ROM -chips. It's often used to flash BIOS/coreboot/firmware images. +chips. It's often used to flash BIOS/coreboot/firmware images. It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash, @@ -15,33 +15,43 @@ Build Requirements ------------------ -To build the flashrom utility you need to install the following packages or -ports: +To build flashrom you need to install the following packages or ports: Linux et al: -* pciutils -* pciutils-devel / pciutils-dev / libpci-dev -* zlib-devel / zlib1g-dev + * pciutils + * pciutils-devel / pciutils-dev / libpci-dev + * zlib-devel / zlib1g-dev + On FreeBSD, you need the following ports: -* devel/gmake -* devel/libpci -To compile on FreeBSD, use the command below: -gmake + * devel/gmake + * devel/libpci -To compile on Solaris, use the commands below: -gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" CFLAGS=-O2 +To compile on Linux, use: -To compile on DragonFly BSD, use the commands below: -ln -s /usr/pkg/include/pciutils pci -gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz" + make +To compile on FreeBSD, use: + + gmake + +To compile on Solaris, use: + + gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" \ + CFLAGS=-O2 + +To compile on DragonFly BSD, use: + + ln -s /usr/pkg/include/pciutils pci + gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz" + To compile and run on Darwin/Mac OS X: -Install DirectIO from coresystems GmbH. -DirectIO is available at http://www.coresystems.de/en/directio + Install DirectIO from coresystems GmbH. + DirectIO is available at http://www.coresystems.de/en/directio. + Usage / Options --------------- @@ -51,54 +61,21 @@ Exit status ----------- -flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem -(/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. +Please see the flashrom(8) manpage. coreboot Table and Mainboard Identification -------------------------------------------- -flashrom reads the coreboot table to determine the current mainboard. If no -coreboot table could be read or if you want to override these values, you can -specify -m, e.g.: +Please see the flashrom(8) manpage. - $ flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom -See the 'Supported mainboards' section in the output of 'flashrom -L' for -a list of boards which require the specification of the board name, if no -coreboot table is found. - - ROM Layout Support ------------------ -flashrom supports ROM layouts. This allows you to flash certain parts of -the flash chip only. A ROM layout file looks like follows: +Please see the flashrom(8) manpage. - 00000000:00008fff gfxrom - 00009000:0003ffff normal - 00040000:0007ffff fallback - i.e.: - startaddr:endaddr name - - All addresses are offsets within the file, not absolute addresses! - -If you only want to update the normal image in a ROM you can say: - - flashrom -w --layout rom.layout --image normal agami_aruma.rom - -To update normal and fallback but leave the VGA BIOS alone, say: - - flashrom -w -l rom.layout -i normal -i fallback agami_aruma.rom - -Currently overlapping sections are not supported. - -ROM layouts should replace the -s and -e option since they are more -flexible and they should lead to a ROM update file format with the -ROM layout and the ROM image in one file (cpio, zip or something?). - - Supported Flash Chips / Chipsets / Mainboards --------------------------------------------- Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-05-04 22:33:50 UTC (rev 459) +++ trunk/flashrom.8 2009-05-05 16:15:46 UTC (rev 460) @@ -49,15 +49,49 @@ .TP .B "\-s, \-\-estart" <addr> Exclude start position (obsolete). +.sp +flashrom supports ROM layouts. This allows you to flash certain parts of +the flash chip only. A ROM layout file looks like follows: +.sp + 00000000:00008fff gfxrom + 00009000:0003ffff normal + 00040000:0007ffff fallback +.sp + i.e.: + startaddr:endaddr name +.sp +All addresses are offsets within the file, not absolute addresses! +If you only want to update the normal image in a ROM you can say: +.sp +.B " flashrom -w --layout rom.layout --image normal agami_aruma.rom" +.sp +To update normal and fallback but leave the VGA BIOS alone, say: +.sp +.B " flashrom -w -l rom.layout -i normal \" +.br +.B " -i fallback agami_aruma.rom" +.sp +Currently overlapping sections are not supported. +.sp +ROM layouts should replace the -s and -e option since they are more +flexible and they should lead to a ROM update file format with the +ROM layout and the ROM image in one file (cpio, zip or something?). .TP .B "\-e, \-\-eend" <addr> Exclude end postion (obsolete). .TP .B "\-m, \-\-mainboard" <[vendor:]part> -Override mainboard settings. This option is needed for some mainboards, -see the -.B "flashrom \-\-list\-supported" -output for a list. The vendor is not required when the board name is unique. +Override mainboard settings. +.sp +flashrom reads the coreboot table to determine the current mainboard. If no +coreboot table could be read or if you want to override these values, you can +specify -m, e.g.: +.sp +.B " flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom" +.sp +See the 'Supported mainboards' section in the output of 'flashrom -L' for +a list of boards which require the specification of the board name, if no +coreboot table is found. .TP .B "\-f, \-\-force" Force write without checking whether the ROM image file is really meant

1 0

[v2] r4254 - trunk/coreboot-v2/src/arch/i386/lib
by svn＠coreboot.org May 5, 2009

May 5, 2009

Author: oxygene Date: 2009-05-05 16:06:20 +0200 (Tue, 05 May 2009) New Revision: 4254 Modified: trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c Log: Fix a bug introduced in the copy_and_run refactoring. The new code always decompressed to dst (as it should) and then jumped to _iseg, when it should jump to dst. With dst != _iseg this breaks (coreboot_apc) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c 2009-05-04 20:27:09 UTC (rev 4253) +++ trunk/coreboot-v2/src/arch/i386/lib/copy_and_run.c 2009-05-05 14:06:20 UTC (rev 4254) @@ -44,11 +44,10 @@ print_debug("Jumping to image.\r\n"); __asm__ volatile ( - "movl %0, %%ebp\n\t" + "movl %%eax, %%ebp\n\t" "cli\n\t" - "leal _iseg, %%edi\n\t" "jmp *%%edi\n\t" - :: "a"(ebp) + :: "a"(ebp), "D"(dst) ); }

1 0

r4233/4234 broke h8dme (serial corruption + hang)
by Ward Vandewege May 5, 2009

May 5, 2009

Hi all, It seems r4233/4234 broke the tree for h8dme (k8). Here's how my boot hangs, note the corruption in the serial log: ---------------------------------- .... set DQS timing:RcvrEn:Pass2: 00 done Total DQS Training : tsc [00]=000000007acb45c5 Total DQS Training : tsc [01]=000000007c957514 Total DQS Training : tsc [02]=00000000f820fd23 Total DQS Training : tsc [03]=00000000fab0b966 Ram4 v_esp=000cefec testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done src=fffdf000 sdsrtc==00100f0f0f0f80 eU7ncom pdrsets=s0i0n0gc 8i0m0a0ge tUon cRoAmMp.res sing image to RAM. image length = 00028560 Jumping to image. coreboot-2.0.0-r4234M_h8dme_Fallback Fri May 1 17:07:03 EDT 2009 booting... Enumerating buses... scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled malloc Enter, size 1100, free_memi_mpatgre 0l0e1n4g8t0h0 0= 0m0a0l0l2oac6 c001 4J8u0m0p0in gC PtUo: iAmPaIgCe:. 01 ---------------------------------- Full log available at http://ward.vandewege.net/coreboot/h8dme/r4234-corruption.log Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

4 8

unexpected exception errors loading vga rom
by Joseph Smith May 5, 2009

May 5, 2009

Hello, I keep getting unexpected exception errors on my IP1000 with builds over the past 6 months or so. The unexpected exception errors are random errors and are different every time, but seem to happen right about the time the vga rom loads. I think it has something to do with x86emu and yabel loading the vga rom. If I change it to boot up with out graphics it boots up every time, no problem. If I enable the vga device (2.0) and allocate vga memory but not load the vga rom it boots up every time no problem. So this tells me it doesn’t like something the rom emulator is doing, right? This is very strange because I do not have this problem with the RM4100… just the IP1000 (brother boards). I am going to try SeaBIOS and see if that works but what do I need to do to implement HAVE_HIGH_TABLES on the IP1000? Anything special? Can someone point me to some example boards that use HAVE_HIGH_TABLES? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

9 51

slides/presentation
by Rudolf Marek May 5, 2009

May 5, 2009

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, I decided to speak a bit about coreboot in a student (university) UNIX/Linux club. Are there any slides so I can "pirate" them and maybe improve them a bit? Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkn/OKUACgkQ3J9wPJqZRNUnXwCgqAJxGLqtsIehElyb5vSYIRxG p9MAoLbe/2Kx9iGuT0iddyNsPf2OkDF2 =GD2B -----END PGP SIGNATURE-----

2 1