coreboot May 2009

coreboot@coreboot.org

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[v2] r4260 - in trunk/coreboot-v2: src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/thomson/ip1000
by svn＠coreboot.org 08 May '09

08 May '09

Author: linux_junkie Date: 2009-05-08 02:45:47 +0200 (Fri, 08 May 2009) New Revision: 4260 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb trunk/coreboot-v2/targets/thomson/ip1000/Config.lb Log: Trivial fixup IRQS on IP1000 and RM4100. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-08 00:45:47 UTC (rev 4260) @@ -80,11 +80,11 @@ register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge - register "pirqa_routing" = "0x07" - register "pirqb_routing" = "0x09" - register "pirqc_routing" = "0x0a" + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x06" + register "pirqc_routing" = "0x07" register "pirqd_routing" = "0x09" - register "pirqe_routing" = "0x05" + register "pirqe_routing" = "0x0a" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-08 00:45:47 UTC (rev 4260) @@ -80,11 +80,11 @@ register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge - register "pirqa_routing" = "0x07" - register "pirqb_routing" = "0x09" - register "pirqc_routing" = "0x0a" + register "pirqa_routing" = "0x05" + register "pirqb_routing" = "0x06" + register "pirqc_routing" = "0x07" register "pirqd_routing" = "0x09" - register "pirqe_routing" = "0x05" + register "pirqe_routing" = "0x0a" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" Modified: trunk/coreboot-v2/targets/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) +++ trunk/coreboot-v2/targets/thomson/ip1000/Config.lb 2009-05-08 00:45:47 UTC (rev 4260) @@ -51,7 +51,7 @@ ## ## Request this level of debugging output ## -option DEFAULT_CONSOLE_LOGLEVEL = 7 +option DEFAULT_CONSOLE_LOGLEVEL = 9 romimage "fallback" option USE_FALLBACK_IMAGE = 1

1 0

[PATCH] Assign PIRQs in mainboard Config.lb for IP1000 and RM4100
by Joseph Smith 08 May '09

08 May '09

This patch sets up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 3

[v2] r4259 - in trunk/coreboot-v2/src/mainboard: rca/rm4100 thomson/ip1000
by svn＠coreboot.org 08 May '09

08 May '09

Author: linux_junkie Date: 2009-05-08 02:24:24 +0200 (Fri, 08 May 2009) New Revision: 4259 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb Log: Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-08 00:19:13 UTC (rev 4258) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) @@ -80,6 +80,15 @@ register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge + register "pirqa_routing" = "0x07" + register "pirqb_routing" = "0x09" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x09" + register "pirqe_routing" = "0x05" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-08 00:19:13 UTC (rev 4258) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb 2009-05-08 00:24:24 UTC (rev 4259) @@ -80,6 +80,15 @@ register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge + register "pirqa_routing" = "0x07" + register "pirqb_routing" = "0x09" + register "pirqc_routing" = "0x0a" + register "pirqd_routing" = "0x09" + register "pirqe_routing" = "0x05" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x0b" + device pci 1d.0 on end # USB UHCI Controller #1 device pci 1d.1 on end # USB UHCI Controller #2 device pci 1d.2 on end # USB UHCI Controller #3

1 0

[PATCH] Disable AC97 modem early on IP1000
by Joseph Smith 08 May '09

08 May '09

This patch disables the AC97 modem via the ICH4 LPC disable function register early in the boot process. Leaving it enabled was causing resource allocation problems, making IO read/writes under 0x200 fail. As I found out by trail and error it has to be done right after the LAN Enable gpio pin is driven high. Tested on hardware. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 4

[v2] r4258 - trunk/coreboot-v2/src/mainboard/thomson/ip1000
by svn＠coreboot.org 08 May '09

08 May '09

Author: linux_junkie Date: 2009-05-08 02:19:13 +0200 (Fri, 08 May 2009) New Revision: 4258 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c Log: Disable the AC97 modem via the ICH4 LPC disable function register early in the boot process. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c 2009-05-07 05:47:05 UTC (rev 4257) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c 2009-05-08 00:19:13 UTC (rev 4258) @@ -43,6 +43,9 @@ set_gpio |= 1 << 23; outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c); + /* Disable AC97 Modem */ + pci_write_config8(dev, 0xf2, 0x40); + /* Super I/O GPIOs. */ dev = PME_DEV; port = dev >> 8;

1 0

cbfs XIP patch
by ron minnich 07 May '09

07 May '09

Attached. This patch lets us create XIP stages for cbfs. ron

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[PATCH] flashrom: List chipset test status
by Uwe Hermann 07 May '09

07 May '09

See patch. I'm also working on wiki-sytax output for of the status tables so we can easier sync "flashrom --whatever" output to the wiki. This patch is one of several preconditions to make that possible. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

coreboot and Intel 5100 chipset compatibility question
by Olga Gelbart 07 May '09

07 May '09

Hello, I am trying to find out whether coreboot is compatible with Intel 5100 chipset. I know that it is not listed on the compatibility page of the coreboot website, but I was wondering if anyone has done any work with it or if there are any plans to make it compatible in the future. Any information on this would be greatly appreciated! -Olga

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[flashrom] r472 - trunk
by svn＠coreboot.org 07 May '09

07 May '09

Author: uwe Date: 2009-05-07 15:24:49 +0200 (Thu, 07 May 2009) New Revision: 472 Modified: trunk/chipset_enable.c Log: Store and display chipset test status (not only chip status). The list of tested chipsets is synced from the wiki. Also, split the chipset vendor and name into two fields for easier wiki-syntax output later. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-07 00:59:53 UTC (rev 471) +++ trunk/chipset_enable.c 2009-05-07 13:24:49 UTC (rev 472) @@ -867,88 +867,94 @@ } typedef struct penable { - uint16_t vendor, device; - const char *name; + uint16_t vendor_id; + uint16_t device_id; + int status; + const char *vendor_name; + const char *device_name; int (*doit) (struct pci_dev *dev, const char *name); } FLASH_ENABLE; +#define OK 0 +#define NT 1 /* Not tested */ + static const FLASH_ENABLE enables[] = { - {0x1039, 0x0630, "SiS630", enable_flash_sis630}, - {0x8086, 0x122e, "Intel PIIX", enable_flash_piix4}, - {0x8086, 0x1234, "Intel MPIIX", enable_flash_piix4}, - {0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4}, - {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4}, - {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4}, - {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e}, - {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e}, - {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e}, - {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e}, - {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e}, - {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e}, - {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e}, - {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e}, - {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e}, - {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e}, - {0x8086, 0x2670, "Intel 631xESB/632xESB/3100", enable_flash_ich_dc}, - {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc}, - {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7}, - {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7}, - {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7}, - {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7}, - {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7}, - {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8}, - {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8}, - {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8}, - {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8}, - {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8}, - {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9}, - {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9}, - {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9}, - {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9}, - {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9}, - {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9}, - {0x8086, 0x3a14, "Intel ICH10DO", enable_flash_ich10}, - {0x8086, 0x3a16, "Intel ICH10R", enable_flash_ich10}, - {0x8086, 0x3a18, "Intel ICH10", enable_flash_ich10}, - {0x8086, 0x3a1a, "Intel ICH10D", enable_flash_ich10}, - {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, - {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, - {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, - {0x1106, 0x3337, "VIA VT8237A", enable_flash_vt823x}, - {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi}, - {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x}, - {0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111}, - {0x1106, 0x0686, "VIA VT82C686A/B", enable_flash_amd8111}, - {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530}, - {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100}, - {0x1039, 0x0008, "SiS5595", enable_flash_sis5595}, - {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536}, - {0x1022, 0x7468, "AMD8111", enable_flash_amd8111}, - {0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600}, - {0x1002, 0x439d, "ATI(AMD) SB700", enable_flash_sb600}, - {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533}, - {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */ - {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */ + {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630}, + {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, + {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, + {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, + {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, + {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, + {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, + {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, + {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, + {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, + {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, + {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, + {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, + {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, + {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, + {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, + {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, + {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, + {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, + {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, + {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, + {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, + {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, + {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, + {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, + {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, + {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, + {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, + {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, + {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, + {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, + {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, + {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, + {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, + {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, + {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595}, + {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, + {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB700", enable_flash_sb600}, + {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, + {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ + {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ /* Slave, should not be here, to fix known bug for A01. */ - {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, - {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804}, - {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804}, - {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804}, - {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804}, - {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/ - {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */ - {0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55}, - {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, - {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000}, - {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520}, - {0x1022, 0x7440, "AMD AMD-768", enable_flash_amd8111}, + {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, + {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ + {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ + {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55}, + {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, + {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, + {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, }; void print_supported_chipsets(void) @@ -958,8 +964,10 @@ printf("\nSupported chipsets:\n\n"); for (i = 0; i < ARRAY_SIZE(enables); i++) - printf("%s (%04x:%04x)\n", enables[i].name, - enables[i].vendor, enables[i].device); + printf("%s %s [%04x:%04x]%s\n", enables[i].vendor_name, + enables[i].device_name, enables[i].vendor_id, + enables[i].device_id, + (enables[i].status == OK) ? "" : " (untested)"); } int chipset_flash_enable(void) @@ -970,16 +978,16 @@ /* Now let's try to find the chipset we have... */ for (i = 0; i < ARRAY_SIZE(enables); i++) { - dev = pci_dev_find(enables[i].vendor, enables[i].device); + dev = pci_dev_find(enables[i].vendor_id, enables[i].device_id); if (dev) break; } if (dev) { - printf("Found chipset \"%s\", enabling flash write... ", - enables[i].name); + printf("Found chipset \"%s %s\", enabling flash write... ", + enables[i].vendor_name, enables[i].device_name); - ret = enables[i].doit(dev, enables[i].name); + ret = enables[i].doit(dev, enables[i].device_name); if (ret) printf("FAILED!\n"); else

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Re: [coreboot] Tyan Product Listings
by joelr＠tyan.com 07 May '09

07 May '09

Stefan, Here is a list of products we have tested thus far and have found will work just fine with FlashROM Motherboard Flash Utility Support Spreadsheet Bios Chip Vendor Bios Chip Part # Motherboard Linux Flash Utility FlashROM (v3332) FlashROM (v3332) OS Support 32-bit Distributions 64-bit Distributions S5377 Yes SST 49LF008A S5376G2NR Yes Yes SST 49LF008A S5376WAG2NR Yes Yes SST 49LF008A S5375 Yes SST 49LF008A S5375-1U Yes SST 49LF008A S5220 Yes SST 49LF008A S5211 Yes Yes SST 49LF008A S5211-1U Yes Yes SST 49LF008A S5197 Yes SST 49LF008A S5191 Yes SST 49LF008A S5180 Yes SST 49LF008A S3095 Yes SST 49LF008A S2882 Yes Yes PMC 49LF004T S2882-D Yes Yes PMC 49LF004T S2881 Yes Yes PMC 49LF004T Our process is still ongoing so we will have new updates periodically to help include new FlashROM versions as well as new Tyan motherboards to this listing. Our plans are to go through our current product listings and see if we can get FlashROM to work on them. We want to be able to add something other than AMI, Award or Phoenix as a flash utility for our customers. We have been pleased with what the FlashROM utility does and we are working on further validation with this particular utility. Thanks again for your reply and we will continue to stay in touch as new updates are made available. Joel Robertson Tech Support Manager Customer Service Manager Vendor Relations Manager joelr(a)tyan.com (510) 651-8868 ext. 5196 ________________________________ From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer Sent: Tuesday, August 26, 2008 5:39 PM To: joelr (joelr - TYANUS) Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] Tyan Product Listings Dear Joel Robertson, thank you very much for your interest in coreboot and flashrom! If a specific mainboard was tested and is working, please send a mail containing the mainboard and the flash chip you used, and what you tested on that mainboard+flash combination (verify, read, erase, write) to either coreboot(a)coreboot.rom or flashrom(a)coreboot.rom. Then we can update the web pages accordingly. In case you wish to have new, currently unsupported mainboards supported by flashrom, let us know here, too. I think we can help. Best regards, Stefan Reinauer joelr(a)tyan.com wrote: To Whomever it may concern: We would like to update the motherboard listings that support the FlashROM software. We have additional motherboards that we would like to have listed but we need clarification on the process of how to go about this. We have verified that the FlashROM does work in a 32-bit and 64-bit linux environment. We have also made sure that it will verify, read, erase and write a bios chip successfully. Please let us know what we need to update the current support listings on the coreboot.org site. Thanks, Joel Robertson Tech Support Manager Customer Service Manager Vendor Relations Manager joelr(a)tyan.com (510) 651-8868 ext. 5196 -- coreboot mailing list coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info(a)coresystems.de * http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg * HRB 7656 Geschäftsführer: Stefan Reinauer * Ust-IdNr.: DE245674866

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coreboot May 2009