coreboot April 2009

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[v2] r4048 - in trunk/coreboot-v2/src/mainboard/tyan: s2735 s2850
by svn＠coreboot.org 03 Apr '09

03 Apr '09

Author: hailfinger Date: 2009-04-03 04:18:23 +0200 (Fri, 03 Apr 2009) New Revision: 4048 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb Log: There are more than a dozen targets in the v2 tree which refer to ROMCC in their Config.lb but never use it. There's no point in keeping dead code around. Kill it. This patch removes ROMCC remainders from Config.lb for tyan/s2735 and tyan/s2850. Abuild build log with and without the patch is completely identical. More patches of the same type can be done, hopefully making ROMCC dependencies a bit more clear for v2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-02 23:08:16 UTC (rev 4047) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb 2009-04-03 02:18:23 UTC (rev 4048) @@ -35,7 +35,6 @@ arch i386 end - ## ## Build the objects we have code for in this directory. ## @@ -44,8 +43,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end object reset.o -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o @@ -63,39 +60,13 @@ end end -else ## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -end - -## ## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -103,7 +74,6 @@ if CONFIG_USE_INIT ldscript /cpu/x86/car/cache_as_ram.lds end -end ## @@ -117,24 +87,16 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/x86/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -142,36 +104,18 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE -if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds -else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc end -end ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else -# ROMCC -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - ## ## Include the secondary Configuration files ## Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2009-04-02 23:08:16 UTC (rev 4047) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb 2009-04-03 02:18:23 UTC (rev 4048) @@ -45,8 +45,6 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end -if USE_DCACHE_RAM - if CONFIG_USE_INIT makerule ./auto.o @@ -64,32 +62,7 @@ end end -else - ## -## Romcc output -## -makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" -end - -end -## ## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE @@ -99,7 +72,6 @@ mainboardinit cpu/x86/32bit/entry32.inc -if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end @@ -107,7 +79,6 @@ if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end -end ## ## Build our reset vector (This is where coreboot is entered) @@ -120,24 +91,16 @@ ldscript /cpu/x86/32bit/reset32.lds end -if USE_DCACHE_RAM -else -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc -end - ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds -if USE_DCACHE_RAM ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc -end ### ### This is the early phase of coreboot startup @@ -145,13 +108,8 @@ ### failover to another image. ### if USE_FALLBACK_IMAGE -if USE_DCACHE_RAM ldscript /arch/i386/lib/failover.lds -else - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc end -end ### ### O.k. We aren't just an intermediary anymore! @@ -160,29 +118,13 @@ ## ## Setup RAM ## -if USE_DCACHE_RAM - if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end -else - ## -## Setup RAM -## -mainboardinit cpu/x86/fpu/enable_fpu.inc -mainboardinit cpu/x86/mmx/enable_mmx.inc -mainboardinit cpu/x86/sse/enable_sse.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse/disable_sse.inc -mainboardinit cpu/x86/mmx/disable_mmx.inc - -end - -## ## Include the secondary Configuration files ## config chip.h

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[v2] r4047 - trunk/coreboot-v2/util/newconfig
by svn＠coreboot.org 03 Apr '09

03 Apr '09

Author: stepan Date: 2009-04-03 01:08:16 +0200 (Fri, 03 Apr 2009) New Revision: 4047 Modified: trunk/coreboot-v2/util/newconfig/config.g Log: Ronald Hoogenboom writes: I've attached a patch that removes the 3-mile-long compiler commandlines, which vim's quickfix doesn't like so much. Instead of putting all those -DXYZ='bla' on the compiler commandline, they are put in a file called settings.h (as #define XYZ bla) and only a --include=settings.h is put on the commandline. This file is created unconditionally at the same time as when the CPUFLAGS simply expanded make variable used to be created (not via a target rule and dependency), so it shouldn't change anything. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-04-01 22:07:53 UTC (rev 4046) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-04-02 23:08:16 UTC (rev 4047) @@ -2049,9 +2049,9 @@ file.write("# Get the value of TOP, VARIABLES, and several other variables.\n") file.write("include Makefile.settings\n\n") file.write("# Function to create an item like -Di586 or -DCONFIG_MAX_CPUS='1' or -Ui686\n") - file.write("D_item = $(if $(subst undefined,,$(origin $1)),-D$1$(if $($1),='$($1)',),-U$1)\n\n") + file.write("D_item = $(shell echo '$(if $(subst undefined,,$(origin $1)),\\#define $1$(if $($1), $($1),),\\#undef $1)' >> settings.h)\n\n") file.write("# Compute the value of CPUFLAGS here during make's first pass.\n") - file.write("CPUFLAGS := $(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))\n\n") + file.write("CPUFLAGS := $(strip $(shell echo '/* autogenerated */' > settings.h)$(foreach _var_,$(VARIABLES),$(call D_item,$(_var_)))--include=settings.h)\n\n") for i in image.getuserdefines(): file.write("%s\n" %i)

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build optimization
by Ronald Hoogenboom 02 Apr '09

02 Apr '09

Hi, I've attached a patch that removes the 3-mile-long compiler commandlines, which vim's quickfix doesn't like so much. Instead of putting all those -DXYZ='bla' on the compiler commandline, they are put in a file called settings.h (as #define XYZ bla) and only a --include=settings.h is put on the commandline. This file is created unconditionally at the same time as when the CPUFLAGS simply expanded make variable used to be created (not via a target rule and dependency), so it shouldn't change anything. Signed-off-by: Ronald Hoogenboom<hoogenboom30(a)zonnet.nl>

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coreboot v4.1
by Carl-Daniel Hailfinger 02 Apr '09

02 Apr '09

[Distribution to news outlets is encouraged.] I'm happy to announce that today coreboot v4.1 has been released. Besides being totally redesigned, it is super-fast, handles almost every existing chipset, opens our codebase to contributors without lowlevel C skills and is generally something to be celebrated. Not to mention the environmental friendliness and promotion of world peace. Features include, but are not limited to: - LARROMFS-NG, allowing code and configuration storage in the ROM without risking accidental reflashes. With its clean and simple design, you can store hundreds of different file types easily in the ROM, each of them being handled by a different plugin. - SQL-based chipset programming. Gone are the days where you had to differentiate between accessing PCI regs via struct device, u32 or device_t variants. Now you can use statements like: SELECT val_32bit FROM pci WHERE buslocation="badc:0f:fe.e" AND configbytenumber=00; or the even simpler SELECT val_32bit FROM pci NATURAL JOIN configbytes WHERE buslocation="badc:0f:fe.e" AND configbytename="Vendor ID"; Changing PCI config space follows similar rules. - A SQL interpreter in coreboot which handles all chipset code. This SQL interpreter combines the clarity of obfuscated FORTH with the speed of unoptimized SQL. - Self-modifying code! As we all know, self-modifying code has less bugs because any given bug disappears after the code has been modified often enough. Plus, this is a good way to exercise CPUs to detect hardware problems more easily. - Fancy linker scripts. LARROMFS-NG is the next generation archiving solution for all our needs because it does not rely on inherently bug-prone C code. LARROMFS-NG is implemented as a really big and all-encompassing set of linker scripts which can even link new linkers together which reinterpret these linker scripts. - New plugin architecture. Coreboot v4.1 will faithfully execute any and all code presented on any device attached to the board. Due to that, trojanizing computers becomes a piece of cake, freeing up the precious time of the intelligence community for more pressing problems like world peace. - Multi-language error messages. Although chinese error messages were a bit difficult to store in 7-bit ASCII, we created a lossy compression scheme which will hardly ever insult users by accident. - An animated splash screen with sound. This was one of the most wanted features in the past, but coreboot was too fast for anyone to notice the splash screen. Now we have a mandatory delay of 20 seconds, enough for short movies and even some tacked on ads. - Ultra-secure Suspend-to-RAM (S3) for people worried of RAM readout (the "cold boot attacks" with frozen RAM). During every suspend cycle, coreboot completely wipes the RAM and will resume to a data-free system. - WORN technology. This is shorthand for Write Once, Read Never. Others practice that coding tradition by accident, but we have perfected it as an art. - Double use technology. Most people think of weapons when they hear this, but it's more simple and a lot more environmentally friendly. Your CPU will not only calculate stuff, coreboot can also switch off the fans on demand to make sure the CPU will fry your omelette exactly right. - Less-than-zero boot times. Ever had the problem that your boot took too long? We have the simple solution: Once coreboot is finished with initializing the hardware, it will set back your clock by 30 seconds. Even with the mandatory 20 second delay for splash movies, you can finish booting 9-10 seconds before you switched the machine on. - Real life impact. With a less-than-zero boot time, time goes effectively backward. If you assemble a big enough cluster of coreboot machines, you can undo the worst decisions of your life. As you can see, coreboot v4.1 is the best thing since the invention of sliced bread. It even makes firmware veterans spin in their graves to act as human-powered electricity generators (a nice environmental plus). To limit the impact on the real world (especially due to the time machine properties), this coreboot version will only be available for download this April 1st. Sincerely, the coreboot team -- http://www.hailfinger.org/

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Re: [coreboot] [v3] r1162 - coreboot-v3/northbridge/intel/i440bxemulation
by Carl-Daniel Hailfinger 02 Apr '09

02 Apr '09

On 24.03.2009 00:55, svn(a)coreboot.org wrote: > Author: rminnich > Date: 2009-03-24 00:55:58 +0100 (Tue, 24 Mar 2009) > New Revision: 1162 > > Modified: > coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c > Log: > This is an emergency fix for building for qemu. > > With this fix, FILO works. > This was already fixed with a weak function since r1161. Changelog was: Emergency fixup for the missing is_coldboot(). Note that the weak is_coldboot() returns always 1. The i945 is_coldboot() returns 1 for a warm boot? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [coreboot] [v2] r4040 - trunk/coreboot-v2/src/boot
by Uwe Hermann 02 Apr '09

02 Apr '09

On Wed, Apr 01, 2009 at 01:03:32PM +0200, svn(a)coreboot.org wrote: > Add copyright notices to two files, src/boot/elfboot.c > and its derivative src/boot/selfboot.c. Nice, thanks for fixing that! Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

Soldering a socket on your board
by Joseph Smith 02 Apr '09

02 Apr '09

Uwe, Great job on the "Soldering a socket on your board" Wiki page. I like it :-) What I do is take a piece of aluminum foil, fold it in half (for double the protection), and cut a rectangle out just the size of the chip. I place the piece of foil over the chip when heating it with my regular heat gun (about $20 US). The foil really helps to absorb the heat so nothing else except the chip heats up. I have one that I need to do, If I get time this weekend I will do it and take some picks if you want. Just let me know. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[v2] r4046 - trunk/coreboot-v2/src/cpu/x86/mtrr
by svn＠coreboot.org 02 Apr '09

02 Apr '09

Author: mjones Date: 2009-04-02 00:07:53 +0200 (Thu, 02 Apr 2009) New Revision: 4046 Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c Log: Fix typo. trivial. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-04-01 16:22:38 UTC (rev 4045) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-04-01 22:07:53 UTC (rev 4046) @@ -134,7 +134,7 @@ return r; } -/* fms: find least sigificant bit set */ +/* fls: find least sigificant bit set */ static inline unsigned int fls(unsigned int x) { int r;

1 0

question about irc
by Jason Wang 01 Apr '09

01 Apr '09

Hi all, Is there anyone who know how to use IRC to join in coreboot chat? I really do not know how to apply an account for it. -- Jason Wang Peking University

4 3

Micro code for 1022h 01000095h
by Bao, Zheng 01 Apr '09

01 Apr '09

This patch applies for DR-B2 and B3. The patch file is for RFC requirement. Just copy the header file to src/cpu/amd/model_10xxx/ Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>

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coreboot April 2009