coreboot February 2009

coreboot@coreboot.org

67 participants
232 discussions

GSoC 2009 deadlines
by Carl-Daniel Hailfinger 19 Mar '09

19 Mar '09

Hi all, GSoC 2009 is approaching and although the number of total slots has been reduced, there is a chance we might get some slots for coreboot and/or flashrom. We might want to apply separately for coreboot and flashrom, maybe also for buildrom or libpayload because they are essentially separate projects. I don't know if SeaBIOS would benefit from GSoC because it seems rather complete to me. Deadline for organizational applications: March 13, 2009 noon. No application possible before March 9, 2009 noon. http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_org_apply… Full timeline: http://code.google.com/intl/de/opensource/gsoc/2009/faqs.html#0_1_timeline_… Regards, Carl-Daniel -- http://www.hailfinger.org/

8 14

#116: dtc-parser.tab.c Fehler 127
by coreboot 13 Mar '09

13 Mar '09

#116: dtc-parser.tab.c Fehler 127 -----------------------+---------------------------------------------------- Reporter: anonym | Type: defect Status: new | Priority: major Milestone: | Component: toolchain Version: v3 | Keywords: dtc-parser Dependencies: | Patchstatus: there is no patch -----------------------+---------------------------------------------------- /Desktop/thinclient/coreboot-v3 % make CP build/config.h GEN build/build.h CC build/lib/console.o BISON build/util/dtc/dtc-parser.tab.c make: *** [/home/xxx/Desktop/thinclient/coreboot-v3/build/util/dtc/dtc- parser.tab.c] Fehler 127 -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/116> coreboot <http://www.coreboot.org/>

1 5

#114: Use GCCINCDIR instead of open-coding it
by coreboot 13 Mar '09

13 Mar '09

#114: Use GCCINCDIR instead of open-coding it -----------------------------------------+---------------------------------- Reporter: vincent.legoll(a)gmail.com | Type: enhancement Status: new | Priority: trivial Milestone: | Component: filo Version: v2 | Keywords: makefile Dependencies: | Patchstatus: patch is ready to be committed -----------------------------------------+---------------------------------- in trunk/filo/Makefile, there is duplicated code to get gcc include directory, the attached patch fixes that. -- Ticket URL: </trac/ticket/114> coreboot <http://www.coreboot.org/>

1 1

ACPI patches for Tyan s2895, s2892, s2891
by Myles Watson 11 Mar '09

11 Mar '09

These patches let Ubuntu 8.10 boot with ACPI support and no ACPI table-related warnings. I haven't done SMM support yet, so that still complains and disables IRQ 9. Windows still doesn't like something, but I thought I'd contribute this code before I started using munged factory tables to see if I can get it to work that way. Because resource allocation is totally different, the tables will need to be munged quite a bit :( _Tyan_common_tables.diff_ This patch adds common elements for ck804-based boards. changes by file: src/arch/i386/boot/acpi.c: Be Paranoid and set srat_lapic table to zero before filling it. Enable SLIT filling if acpi_create_slit gets called. src/northbridge/amd/amdk8/northbridge.c: Add high tables code ala Stefan's code for the i945. src/northbridge/amd/amdk8/amdk8_util.asl: Put this file here instead of every board having a personal copy. src/southbridge/nvidia/ck804/ck804_lpc.c: Enable High Precision Event Timers. Add pm_base for ACPI. src/northbridge/amd/amdk8/amdk8_acpi.c Silence warnings about implicit functions and format strings. src/arch/i386/include/arch/acpi.h: Add slit prototype and minor whitespace. src/southbridge/nvidia/ck804/ck804_fadt.c: Since fadt is only dependent on the Southbridge, add it here. src/southbridge/nvidia/ck804/Config.lb: Compile in ck804_fadt.c _s289X_tables.diff_ changes by file: src/mainboard/tyan/s289X/Options.lb: Add options and defaults for ACPI tables and resources. src/mainboard/tyan/s289X/mainboard.c: Add high_tables resource ala Stefan's code for the Kontron. src/mainboard/tyan/s289X/acpi_tables.c: Fill out the ACPI tables, using existing code where possible. Only the madt is different between the boards, to be combined later. src/mainboard/tyan/s289X/Config.lb: Compile in acpi_tables.c and dsdt.dsl. Turn on the parallel port and the real-time-clock. src/mainboard/tyan/s289x/dsdt.dsl: The board layout (thanks Rudolf) and interrupts from mptable.c src/mainboard/tyan/s289x/mptable.c: Minor formatting changes to make them diff better. src/superio/smsc/lpc47b397/superio.c: (s2895 only) Correct the size of the real-time-clock so it can be where it belongs. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

5 21

Problems about booting windows xp
by Wang, Qingpei 10 Mar '09

10 Mar '09

Hi, I am trying to boot windows xp with my dbm690t which has S1G1 CPU, sb600 and rs690 chipset. Now, It still soft reset after loading several files. The serial debug message says: "fail handle_1ab1:154 Fail handle_1aXX:274 Fail get_device:608(00000001) Fail handle_15XX:308(00000086)" Do you have any advice for that or give me and ideas to debug? Thanks Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD)

6 21

[PATCH 2/2] AMD boards to use new Power Now infrastructure
by Rudolf Marek 09 Mar '09

09 Mar '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, This patch is for AMD boards which can do the P state generation. This just removes the ugly binary DSDT patching and all other related stuff. Stick to infrastructure in previous patch. This was just compile tested. I think it should work. Please test. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkmWxJ0ACgkQ3J9wPJqZRNWqygCeKf09gJbRIBWn4we3XKd/3k3T mMMAoOBs7K8q4Xuc4YqnUu3QZF7yHwwr =jbxj -----END PGP SIGNATURE-----

4 10

Coreboot patches for v2 with SeaBIOS
by Myles Watson 05 Mar '09

05 Mar '09

Does anyone have an updated HOWTO for booting XP with SeaBIOS? I'm specifically wondering if there's an option we should add to v2 which relocates BIOS tables so that SeaBIOS doesn't overwrite them, or if we should add that to buildrom. Thanks, Myles

6 35

VIA PC2500e-like board from ECS doesn't boot up
by Heiko Weinen 04 Mar '09

04 Mar '09

Hi everyone! I'm trying to make an Elitegroup (ECS) board run coreboot. Model specifics are ECS C7VCM2 rev.1.0 with: - CN700 - VT8237R - ITE IT8716F-S - VIA C7 CPU @ 1000 MHz The Homepage of the product is at: http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=885&… Yet, i've tried booting a vanilla pc2500 coreboot with various payloads. The most i got it to do was outputting this line to the serial console: "Coreboot-2.0.0-pc2500e Fr 30. Jan 20:12:16 CET 2009 booting..." Actually, there was some garbage in front of that, but that got emitted on every powerup of the board (even without flash-chip). Afterwards the system just keeps emitting two barely audible clicks every 4 seconds (which it also does without flash). Uwe tried helping with various suggestions (thanksalot!) but nothing really helped. So i'm posting here, maybe someone knows a solution. Appended is the output of lspci -tvnn, superiotool, getpir, and mptable (as Uwe kindly suggested). Thanks in advance, Heiko ----- 8< ----- Attached board info ----- >8 ----- root@grml ~ # ./coreboot_diag.sh ------- lspci -tvnn output ------- -[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:0314] +-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:1314] +-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:2314] +-00.3 VIA Technologies, Inc. PT890 Host Bridge [1106:3208] +-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:4314] +-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge [1106:7314] +-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP [1106:3344] +-0a.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller [1106:3149] +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] +-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] [1106:3227] \-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] ------- superiotool output ------- superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8716F (id=0x8716, rev=0x1) at 0x2e Register dump: idx 20 21 22 23 24 2b val 87 16 01 10 00 00 def 87 16 01 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 04 00 80 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 01 03 f8 04 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 01 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 01 03 78 00 00 07 04 08 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 02 90 00 00 00 80 00 0a 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 00 02 48 def 01 00 60 00 64 01 02 00 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 00 03 00 00 28 80 1f 00 00 08 00 00 00 00 01 00 38 00 00 00 00 00 20 00 00 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 3f 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 03 00 0a 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 02 01 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff ------- getpir output ------- Probing PIRQ table in memory. Found PCI IRQ routing table signature at 0xfcd30. Validating... checksum is wrong. Creating irq_tables.c ... Done, you can move the file to the coreboot tree now. ------- getpir generated irq_tables.c ------- /* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * * Contains the IRQ Routing Table dumped directly from your * memory, which BIOS sets up. * * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx */ #ifdef GETPIR #include "pirq_routing.h" #else #include <arch/pirq_routing.h> #endif const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*6, /* There can be total 6 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ 0x1106, /* Vendor */ 0x596, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xcc, /* u8 checksum. This has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}}, 0x1, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0}, {0x00,(0x11<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}}, 0x0, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}}, 0x0, 0x0}, {0x00,(0x01<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}}, 0x0, 0x0}, {0x00,(0x10<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr); } ------- mptable output ------- /* generated by MPTable, version 2.0.15*/ /* as modified by RGM for coreboot */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <string.h> #include <stdint.h> void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "LNXI "; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); memcpy(mc->mpc_signature, sig, sizeof(sig)); mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_spec = 0x04; mc->mpc_checksum = 0; /* not yet computed */ memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_productid, productid, sizeof(productid)); mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = LAPIC_ADDR; mc->mpe_length = 0; mc->mpe_checksum = 0; mc->reserved = 0; smp_write_processors(mc); /*Bus: Bus ID Type*/ smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "ISA "); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { device_t dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 3, 0x20, res->base); } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 4, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1e,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 5, 0x20, res->base); } } dev = dev_find_slot(4, PCI_DEVFN(0x1c,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, 8, 0x20, res->base); } } } /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x46, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x28, 0x2, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x3d, 0x2, 0x14); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x2, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x1, 0x2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x0, 0x2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x3, 0x2, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x4, 0x2, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x6, 0x2, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x7, 0x2, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x2, 0x8, 0x2, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0x9, 0x2, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xc, 0x2, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xd, 0x2, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xe, 0x2, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x2, 0xf, 0x2, 0xf); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } root@grml ~ #

3 2

[PATCH] filesystem hierarchy in v2 buildsystem
by Stefan Reinauer 03 Mar '09

03 Mar '09

See patch. This fixes a very ugly issue in v2. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 2

MPTable can not be high-memory on Linux
by Kevin O'Connor 02 Mar '09

02 Mar '09

Hi Stefan, I'm CC'ing lkml and coreboot mailing lists. On Thu, Feb 19, 2009 at 10:26:17PM +0100, Stefan Reinauer wrote: > OK, I played some more, and I finally found out it's earlyprintk and not > early_printk. Plus there is bootmem_debug: > > Initializing cgroup subsys cpuset > Initializing cgroup subsys cpu > Linux version 2.6.27.7-9-default (geeko@buildhost) (gcc version 4.3.2 > [gcc-4_3-branch re0 > PAT WC disabled due to known CPU erratum. > BIOS-provided physical RAM map: > BIOS-e820: 0000000000000000 - 0000000000001000 (reserved) > BIOS-e820: 0000000000001000 - 0000000000090000 (usable) > BIOS-e820: 0000000000090000 - 0000000000100000 (reserved) > BIOS-e820: 0000000000100000 - 000000003f7f0000 (usable) > BIOS-e820: 000000003f7f0000 - 0000000040000000 (reserved) > BIOS-e820: 00000000f0000000 - 00000000f4000000 (reserved) [...] > ACPI: no DMI BIOS year, acpi=force is required to enable ACPI > ACPI: Disabling ACPI support [...] > found SMP MP-table at [c00f9fc0] 000f9fc0 > bootmem::mark_bootmem_node nid=0 start=f9 end=fb reserve=1 flags=0 > bootmem::__reserve nid=0 start=f9 end=fb flags=0 > bootmem::__reserve silent double reserve of PFN f9 > bootmem::__reserve silent double reserve of PFN fa > BUG: Int 6: CR2 00000000 > EDI c00f9fd0 ESI 3f7f5410 EBP 0003f7f5 ESP c0535f20 > EBX c056c00c EDX 00000006 ECX 00000001 EAX c056c03c > err 00000000 EIP c054f8f0 CS 00000060 flg 00010046 > Stack: 00000000 00000000 00000001 00038000 0003f7f5 f880abf0 3f7f5410 > c00f9fd0 > 00000001 c054f91d 00000000 c054571a c0413e7e c00f9fc0 000f9fc0 > 00000001 > 3f7bf64d 00000000 3e2c5000 c054578a 00000000 c053f3b6 3f7bf64d > 00000000 > > So it dies because of the way it tries to reserve the MP-table. > > Here's the stack trace. > > [<c054f8f0>] mark_bootmem+0x9b/0xab > [<c054f91d>] reserve_bootmem+0x1d/0x1f > [<c054571a>] smp_scan_config+0xd9/0xfa > [<c054578a>] __find_smp_config+0x4f/0x6e > [<c053f3b6>] setup_arch+0x576/0x639 > [<c054ebc4>] cgroup_init_subsys+0x29/0xc9 > [<c053a6ac>] start_kernel+0x6b/0x31f > ======================= It looks like the problem is that the MPTable is located in the last 64K of memory (instead of the first few megabytes). There is a comment about this in arch/x86/kernel/mpparse.c: /* * We cannot access to MPC table to compute * table size yet, as only few megabytes from * the bottom is mapped now. * PC-9800's MPC table places on the very last * of physical memory; so that simply reserving * PAGE_SIZE from mpg->mpf_physptr yields BUG() * in reserve_bootmem. */ However, that comment is in an #ifdef specific to 32bit kernels. (Though, it's not clear to me how that code would help as it sets size to be a negative number.) The easiest way to fix this is to change SeaBIOS to copy the whole mptable to the first megabyte. Also, we need to fix your SMBIOS so that ACPI is used instead of the mptable. -Kevin

5 17

← Newer
1
2
3
4
5
6
7
...
24
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2009