coreboot February 2009

coreboot@coreboot.org

67 participants
232 discussions

r3961 - in trunk/coreboot-v2: src/config src/cpu/x86/smm util/newconfig
by svn＠coreboot.org 28 Feb '09

28 Feb '09

Author: stepan Date: 2009-02-28 13:50:32 +0100 (Sat, 28 Feb 2009) New Revision: 3961 Modified: trunk/coreboot-v2/src/config/Config.lb trunk/coreboot-v2/src/cpu/x86/smm/Config.lb trunk/coreboot-v2/util/newconfig/config.g Log: With this patch the v2 build system will create a directory hierarchy similar to what v3 does. This is required to have two source files with the same name but in different directories. (As in, two different SuperIOs on board, with a superio.c each) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-02-27 23:09:55 UTC (rev 3960) +++ trunk/coreboot-v2/src/config/Config.lb 2009-02-28 12:50:32 UTC (rev 3961) @@ -45,8 +45,8 @@ makerule coreboot_ram.o - depends "$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" - action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" + depends "$(TOP)/src/arch/$(ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" end makerule coreboot_ram Modified: trunk/coreboot-v2/src/cpu/x86/smm/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/x86/smm/Config.lb 2009-02-27 23:09:55 UTC (rev 3960) +++ trunk/coreboot-v2/src/cpu/x86/smm/Config.lb 2009-02-28 12:50:32 UTC (rev 3961) @@ -27,8 +27,8 @@ smmobject smihandler.o makerule smm.o - depends "$(SMM-OBJECTS) printk.o vtxprintf.o $(LIBGCC_FILE_NAME)" - action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $(SMM-OBJECTS) printk.o vtxprintf.o $(LIBGCC_FILE_NAME)" + depends "$(SMM-OBJECTS) $(TOP)/src/console/printk.o $(TOP)/src/console/vtxprintf.o $(LIBGCC_FILE_NAME)" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" end makerule smm Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-02-27 23:09:55 UTC (rev 3960) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-02-28 12:50:32 UTC (rev 3961) @@ -329,9 +329,14 @@ type = object_name[-1:] if (object_name[0] == '.'): source = base + suffix + object = base + '.o' else: - source = os.path.join(dirstack.tos(), base + suffix) - object = base + '.o' + rel_base = re.sub(treetop, "", os.path.join(dirstack.tos(), base)) + source = "$(TOP)/" + rel_base + suffix + if (rel_base[0] == '/'): + rel_base = re.sub("^/", "", rel_base) + object = rel_base + '.o' + debug.info(debug.object, "add object %s source %s" % (object_name, source)) l = getdict(dict, base) if (l): @@ -2378,6 +2383,30 @@ print "Creating directory %s" % img_dir os.makedirs(img_dir) + for objrule, obj in image.getobjectrules().items(): + sub_dir = img_dir + '/' + os.path.dirname(obj[0]) + if not os.path.isdir(sub_dir): + print "Creating sub directory %s" % sub_dir + os.makedirs(sub_dir) + + for driverrule, driver in image.getdriverrules().items(): + sub_dir = img_dir + '/' + os.path.dirname(driver[0]) + if not os.path.isdir(sub_dir): + print "Creating sub directory %s" % sub_dir + os.makedirs(sub_dir) + + for srule, smm in image.getsmmobjectrules().items(): + sub_dir = img_dir + '/' + os.path.dirname(smm[0]) + if not os.path.isdir(sub_dir): + print "Creating sub directory %s" % sub_dir + os.makedirs(sub_dir) + + for irule, init in image.getinitobjectrules().items(): + sub_dir = img_dir + '/' + os.path.dirname(init[0]) + if not os.path.isdir(sub_dir): + print "Creating sub directory %s" % sub_dir + os.makedirs(sub_dir) + if (debug.level(debug.dump)): for i in image.getinitincludes(): debug.info(debug.dump, "crt0include file %s" % i)

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r3960 - in trunk/coreboot-v2/src: arch/i386/boot config include/boot mainboard/kontron/986lcd-m northbridge/intel/i945
by svn＠coreboot.org 27 Feb '09

27 Feb '09

Author: stepan Date: 2009-02-28 00:09:55 +0100 (Sat, 28 Feb 2009) New Revision: 3960 Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/include/boot/tables.h trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c Log: Generic approach of putting BIOS tables at the end of memory (in addition to their low locations) This adds the kontron 986LCD-M and the i945 as a sample. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-02-27 23:09:55 UTC (rev 3960) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) .... others + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ /* 2006.1 yhlu add mptable cross 0x467 processing */ @@ -38,11 +57,32 @@ printk_debug("ok\n"); } +#if HAVE_HIGH_TABLES == 1 +uint64_t high_tables_base = 0; +uint64_t high_tables_size; +#endif + struct lb_memory *write_tables(void) { unsigned long low_table_start, low_table_end, new_low_table_end; unsigned long rom_table_start, rom_table_end; +#if HAVE_HIGH_TABLES == 1 + /* Even if high tables are configured, all tables are copied both to the + * low and the high area, so payloads and OSes don't need to know about + * the high tables. + */ + unsigned long high_table_start, high_table_end=0; + + if (high_tables_base) { + printk_debug("High Tables Base is %lx.\n", high_tables_base); + high_table_start = high_tables_base; + high_table_end = high_tables_base; + } else { + printk_debug("High Tables Base is not set.\n"); + } +#endif + rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 16 bytes instead of 0 because of a buglet @@ -53,24 +93,47 @@ post_code(0x9a); +#if HAVE_LOW_TABLES == 1 /* This table must be betweeen 0xf0000 & 0x100000 */ rom_table_end = write_pirq_routing_table(rom_table_end); rom_table_end = (rom_table_end + 1023) & ~1023; +#endif +#if HAVE_HIGH_TABLES == 1 + if (high_tables_base) { + high_table_end = write_pirq_routing_table(high_table_end); + high_table_end = (high_table_end + 1023) & ~1023; + } +#endif /* Write ACPI tables */ /* write them in the rom area because DSDT can be large (8K on epia-m) which * pushes coreboot table out of first 4K if set up in low table area */ +#if HAVE_LOW_TABLES == 1 rom_table_end = write_acpi_tables(rom_table_end); rom_table_end = (rom_table_end+1023) & ~1023; - +#endif +#if HAVE_HIGH_TABLES == 1 + if (high_tables_base) { + high_table_end = write_acpi_tables(high_table_end); + high_table_end = (high_table_end+1023) & ~1023; + } +#endif /* copy the smp block to address 0 */ post_code(0x96); /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ +#if HAVE_LOW_TABLES == 1 new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point +#endif +#if HAVE_HIGH_TABLES == 1 + if (high_tables_base) { + high_table_end = write_smp_table(high_table_end); + high_table_end = (high_table_end+1023) & ~1023; + } +#endif -#if HAVE_MP_TABLE==1 +#if HAVE_MP_TABLE == 1 /* Don't write anything in the traditional x86 BIOS data segment, * for example the linux kernel smp need to use 0x467 to pass reset vector * or use 0x40e/0x413 for EBDA finding... @@ -104,8 +167,18 @@ } // Relocate the GDT to reserved memory, so it won't get clobbered - move_gdt(low_table_end); - low_table_end += &gdt_end - &gdt; +#if HAVE_HIGH_TABLES == 1 + if (high_tables_base) { + move_gdt(high_table_end); + high_table_end += &gdt_end - &gdt; + high_table_end = (high_table_end+1023) & ~1023; + } else { +#endif + move_gdt(low_table_end); + low_table_end += &gdt_end - &gdt; +#if HAVE_HIGH_TABLES == 1 + } +#endif #if CONFIG_MULTIBOOT /* The Multiboot information structure */ @@ -119,5 +192,23 @@ write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); +#if 0 && HAVE_HIGH_TABLES == 1 + /* This is currently broken and should be severely refactored. Ideally + * we only have a pointer to the coreboot table in the low memory, so + * anyone can find the real position. + * write_coreboot_table does a lot more than just writing the coreboot + * table. It magically decides where the table should go, and therefore + * it consumes two base addresses. If we call write_coreboot_table like + * below, we get weird effects. + */ + /* And we want another copy in high area because the low area might be + * corrupted + */ + if (high_tables_base) { + write_coreboot_table(high_table_start, high_table_end, + high_table_start, high_table_end); + } +#endif + return get_lb_mem(); } Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/config/Options.lb 2009-02-27 23:09:55 UTC (rev 3960) @@ -1111,6 +1111,18 @@ comment "Enable if the mainboard/chipset requires extra entries in the memory map" end +define HAVE_LOW_TABLES + default 1 + export always + comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte" +end + +define HAVE_HIGH_TABLES + default 0 + export always + comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory" +end + define CONFIG_SPLASH_GRAPHIC default 0 export used Modified: trunk/coreboot-v2/src/include/boot/tables.h =================================================================== --- trunk/coreboot-v2/src/include/boot/tables.h 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/include/boot/tables.h 2009-02-27 23:09:55 UTC (rev 3960) @@ -3,6 +3,9 @@ #include <boot/coreboot_tables.h> +void lb_add_memory_range(struct lb_memory *mem, + uint32_t type, uint64_t start, uint64_t size); + struct lb_memory *write_tables(void); #endif /* BOOT_TABLES_H */ Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-02-27 23:09:55 UTC (rev 3960) @@ -29,6 +29,8 @@ uses LB_CKS_RANGE_END uses LB_CKS_LOC uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES # SMP uses CONFIG_SMP uses CONFIG_LOGICAL_CPUS @@ -160,6 +162,8 @@ ## Build code to provide ACPI support ## default HAVE_ACPI_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 +default HAVE_HIGH_TABLES=0 ## ## Build code to export a CMOS option table Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-02-27 23:09:55 UTC (rev 3960) @@ -289,6 +289,11 @@ printk_debug("ACPI: * DMI (Linux workaround)\n"); memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE); +#if HAVE_HIGH_TABLES == 1 + memcpy((void *)current, dmi_table, DMI_TABLE_SIZE); + current += DMI_TABLE_SIZE; + ALIGN_CURRENT; +#endif printk_info("ACPI: done.\n"); return current; Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/mainboard.c 2009-02-27 23:09:55 UTC (rev 3960) @@ -21,8 +21,30 @@ #include <device/device.h> +#include <console/console.h> +#include <boot/tables.h> #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +/* in northbridge/intel/i945/northbridge.c */ +extern uint64_t uma_memory_base, uma_memory_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + printk_debug("Adding UMA memory area\n"); + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_base, uma_memory_size); + + return 0; +} + struct chip_operations mainboard_ops = { CHIP_NAME("Kontron 986LCD-M Mainboard") }; Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-02-27 17:51:16 UTC (rev 3959) +++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-02-27 23:09:55 UTC (rev 3960) @@ -93,12 +93,18 @@ return tolm; } +#if HAVE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +uint64_t uma_memory_base=0, uma_memory_size=0; + static void pci_domain_set_resources(device_t dev) { uint32_t pci_tolm; uint8_t tolud, reg8; uint16_t reg16; - unsigned long long tomk, tolmk; + unsigned long long tomk; pci_tolm = find_pci_tolm(&dev->link[0]); @@ -120,13 +126,13 @@ switch (reg8) { case 0: tseg_size = 1024; - break; + break; /* TSEG = 1M */ case 1: tseg_size = 2048; - break; + break; /* TSEG = 2M */ case 2: tseg_size = 8192; - break; + break; /* TSEG = 8M */ } printk_debug("%dM\n", tseg_size >> 10); @@ -150,24 +156,32 @@ printk_debug("%dM UMA\n", uma_size >> 10); tomk -= uma_size; + + /* For reserving UMA memory in the memory map */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = uma_size * 1024ULL; } /* The following needs to be 2 lines, otherwise the second * number is always 0 */ - printk_info("Available memory: %dK", tomk); - printk_info(" (%dM)\n", (tomk >> 10)); + printk_info("Available memory: %dK", (uint32_t)tomk); + printk_info(" (%dM)\n", (uint32_t)(tomk >> 10)); - tolmk = tomk; - /* Report the memory regions */ ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, (tolmk - 768)); + ram_resource(dev, 4, 768, (tomk - 768)); if (tomk > 4 * 1024 * 1024) { ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); } assign_resources(&dev->link[0]); + +#if HAVE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)

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etherboot problem..
by jmcdowell＠issisolutions.com 27 Feb '09

27 Feb '09

Before I get flamed, I know this is the coreboot discussion forum. Someone told me the other day that coreboot was the form of linuxbios, and my issue touches linux bios. If this is the wrong list, please forgive me without burning me at the steak. Anyway, on with it. I have a problem, that has had me banging my head against the wall for weeks. I am finally giving up, and asking on the list, as I cannot find documentation to aid in fixing this issue. Here goes.. I have an Linux NetworX cluster here, that uses etherboot on the nodes. The new software replacement doesn't use etherboot, although it's capable of sending out the pxe payload re-packaged for etherboot. The problem is, that when it gets to loading the kernel, it just hangs there. So after trying to build all sorts of new newer newest kernels. I did a little home work. What I did find, was that execute "file" on each kernel. ( The new and old LNXI kernel ) did show two differences. Old : x86 boot sector My newly built kernels show something different. New : Linux kernel x86 boot executable RO-rootFS, root_dev 0x802, swap_dev 0x1, Normal VGA I have searched and searched for documents that explain how to get the image I need. Can anyone please shed some light on this issue? Thanks in advance. Joshua

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Re: [coreboot] etherboot problem..
by jmcdowell＠issisolutions.com 27 Feb '09

27 Feb '09

Just an update / search for more clues.. I copied over a 2.4 .config file this time, and did a make oldconfig and with your console commands added to the append statement. I did finally get some different output. See the tail end of the output below. ( I have attached the entire log file ) Floppy drive(s): fd0 is 2.88M AMI BIOS, fd1 is unknown type 12 (usb?) FDC 0 is a post-1991 82077 brd: module loaded Uniform Multi-Platform E-IDE driver piix 0000:00:1f.1: IDE controller (0x8086:0x248b rev 0x02) pci 0000:00:1f.1: found PCI INT A -> IRQ 5 piix 0000:00:1f.1: not 100% native mode: will probe irqs later ide0: BM-DMA at 0x3c40-0x3c47 ide1: BM-DMA at 0x3c48-0x3c4f ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 ide1 at 0x170-0x177,0x376 on irq 15 ide-gd driver 1.18 PNP: No PS/2 controller found. Probing ports directly. serio: i8042 KBD port at 0x60,0x64 irq 1 serio: i8042 AUX port at 0x60,0x64 irq 12 mice: PS/2 mouse device common for all mice EISA: Probing bus 0 at eisa.0 TCP cubic registered NET: Registered protocol family 17 Using IPI No-Shortcut mode turn off boot console earlyser0 If I take out the printk command, I will see no output.. So with this, does this give anyone any clues? Thanx, Joshua > I tried adding those commands to the append section of the mkelf script > and I still get the same thing.. I may not have mentioned it before. > But I am watching these nodes over conman, as they have no video. If I > use a lnxi built kernel, it will get past the firmware type message and > eventually die because its not configured correctly. Which is ok, one I > figure out how to get a working 2.6 kernel everytime, I wi address the > other issues. > I am convinced the kernel has issues. But I have even cped the .config > of one of the earlier kernels and did a make oldconfig, built it, and > still no change. > > Thanks, > Joshua > > Joshua McDowell > > -----Original Message----- > From: "Joshua McDowell" <JMcDowell(a)ISSISolutions.com> > > Date: Fri, 27 Feb 2009 20:58:01 > To: ron minnich<rminnich(a)gmail.com> > Subject: Re: [coreboot] etherboot problem.. > > > earlyprintk=ttyS0,115200. Where would I put these commands? And what is > the earlyprintk? If I may ask? > > Thanx, > Joshua > > > Joshua McDowell > > -----Original Message----- > From: ron minnich <rminnich(a)gmail.com> > > Date: Fri, 27 Feb 2009 12:44:57 > To: <JMcDowell(a)issisolutions.com> > Cc: <coreboot(a)coreboot.org> > Subject: Re: [coreboot] etherboot problem.. > > > On Fri, Feb 27, 2009 at 12:39 PM, Joshua McDowell > <JMcDowell(a)issisolutions.com> wrote: >> No it does not, I built one that doesn't have vga support and am not >> having any luck there. > > > The first thing I do with cases like this: > console=ttyS0,115200 earlyprintk=ttyS0,115200 > > to see if you even have a living kernel > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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v2 HAVE_OPTION_TABLE patch
by Myles Watson 27 Feb '09

27 Feb '09

This patch makes several CMOS variable reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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Re: [coreboot] etherboot problem..
by Joshua McDowell 27 Feb '09

27 Feb '09

I tried adding those commands to the append section of the mkelf script and I still get the same thing.. I may not have mentioned it before. But I am watching these nodes over conman, as they have no video. If I use a lnxi built kernel, it will get past the firmware type message and eventually die because its not configured correctly. Which is ok, one I figure out how to get a working 2.6 kernel everytime, I wi address the other issues. I am convinced the kernel has issues. But I have even cped the .config of one of the earlier kernels and did a make oldconfig, built it, and still no change. Thanks, Joshua Joshua McDowell -----Original Message----- From: "Joshua McDowell" <JMcDowell(a)ISSISolutions.com> Date: Fri, 27 Feb 2009 20:58:01 To: ron minnich<rminnich(a)gmail.com> Subject: Re: [coreboot] etherboot problem.. earlyprintk=ttyS0,115200. Where would I put these commands? And what is the earlyprintk? If I may ask? Thanx, Joshua Joshua McDowell -----Original Message----- From: ron minnich <rminnich(a)gmail.com> Date: Fri, 27 Feb 2009 12:44:57 To: <JMcDowell(a)issisolutions.com> Cc: <coreboot(a)coreboot.org> Subject: Re: [coreboot] etherboot problem.. On Fri, Feb 27, 2009 at 12:39 PM, Joshua McDowell <JMcDowell(a)issisolutions.com> wrote: > No it does not, I built one that doesn't have vga support and am not having any luck there. The first thing I do with cases like this: console=ttyS0,115200 earlyprintk=ttyS0,115200 to see if you even have a living kernel ron -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] etherboot problem..
by ron minnich 27 Feb '09

27 Feb '09

On Fri, Feb 27, 2009 at 12:39 PM, Joshua McDowell <JMcDowell(a)issisolutions.com> wrote: > No it does not, I built one that doesn't have vga support and am not having any luck there. The first thing I do with cases like this: console=ttyS0,115200 earlyprintk=ttyS0,115200 to see if you even have a living kernel ron

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Re: [coreboot] etherboot problem..
by Joshua McDowell 27 Feb '09

27 Feb '09

No it does not, I built one that doesn't have vga support and am not having any luck there. ------Original Message------ From: ron minnich To: jmcdowell(a)issisolutions.com Cc: coreboot(a)coreboot.org Sent: Feb 27, 2009 2:26 PM Subject: Re: [coreboot] etherboot problem.. your new kernel uses vga. Does the linuxbios on the system have vga support? ron Joshua McDowell

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[PATCH] badram filtering
by Robert Millan 27 Feb '09

27 Feb '09

Hi, This patch implements badram filtering in GRUB. It's the same idea as in http://rick.vanrein.org/linux/badram/ but applied to GRUB. The badram module sits between loaders (or other users like lsmmap) and filters the mmap entries, but only when user previously set the "badram" variable (whose syntax is the same as the one in badram patch for Linux). NOTE this won't affect loadees that get the memory map from BIOS instead of from GRUB. This means it currently works for Multiboot and for the new/experimental Linux loader. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

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r3959 - in trunk/coreboot-v2/src: cpu/amd/dualcore cpu/amd/model_fxx northbridge/amd/amdk8
by svn＠coreboot.org 27 Feb '09

27 Feb '09

Author: myles Date: 2009-02-27 18:51:16 +0100 (Fri, 27 Feb 2009) New Revision: 3959 Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c Log: This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/cpu/amd/dualcore/dualcore.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -56,9 +56,10 @@ unsigned nodes; unsigned nodeid; - if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core - return; - } + if (HAVE_OPTION_TABLE && + read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { + return; // disable dual_core + } nodes = get_nodes(); Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/init_cpus.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -72,7 +72,7 @@ nodes = get_nodes(); disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1 if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core disable_siblings = 1; } Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/coherent_ht.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -1597,7 +1597,8 @@ #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ + if ((!HAVE_OPTION_TABLE) || + read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ total_cpus = verify_dualcore(nodes); } else { Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-02-25 08:07:33 UTC (rev 3958) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit.c 2009-02-27 17:51:16 UTC (rev 3959) @@ -598,11 +598,11 @@ if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (HAVE_OPTION_TABLE && + read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); - } static int is_dual_channel(const struct mem_controller *ctrl) @@ -1146,7 +1146,8 @@ { unsigned long tom_k, base_k; - if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + if ((!HAVE_OPTION_TABLE) || + read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { print_debug("Interleaving disabled\r\n"); @@ -1450,7 +1451,7 @@ min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (bios_cycle_time > min_cycle_time) { + if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2;

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coreboot February 2009