#104: flashrom: Change flash drivers to never erase data before writing
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Reporter: stuge | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone: flashrom v1.0
Component: flashrom | Version:
Keywords: erase write | Dependencies: #103
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
The user should be responsible for ensuring that the flash chip has been
erased where new data should be written.
At the moment, flashrom will erase at least one full page and then rewrite
it, when the user asks to only write a few bytes using -l/-i/-s/-e.
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Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104>
coreboot <http://www.coreboot.org/>
#101: flashrom: Remove pciutils check from Makefile
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Reporter: stuge | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone: flashrom v1.0
Component: flashrom | Version:
Keywords: pciutils libpci build ldflags | Dependencies:
Patchstatus: patch needs review |
---------------------------------------------+------------------------------
The check belongs in a configure script or similar, the check also claims
that packages can not be found for any build error, which is not good
enough. Has confused more than one user already.
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Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/101>
coreboot <http://www.coreboot.org/>
#113: problem
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Reporter: anonymous | Owner: somebody
Type: defect | Status: new
Priority: major | Milestone:
Component: adlo | Version: v2
Keywords: | Dependencies:
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
there is a bug
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Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/113>
coreboot <http://www.coreboot.org/>
#106: flashrom: Add -T to automatically test all flash chip operations
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Reporter: stuge | Owner: somebody
Type: enhancement | Status: new
Priority: major | Milestone: flashrom v1.0
Component: flashrom | Version:
Keywords: testing | Dependencies:
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
Maybe require -f to actually perform the test, since it will potentially
fail to restore the flash chip to it's original state.
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Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/106>
coreboot <http://www.coreboot.org/>
Hi guys,
We are trying to make flashrom work on
http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=858&…
Chipset MCP73 / SIP chipset Macronix MX25L8005.
We made modifications using a enable_flash_mcp55 function, but does't work.
./flashrom -V -c MX25L8005 -r -f rom
Calibrating delay loop... 627M loops per second, 100 myus = 199 us. OK.
No coreboot table found.
Found chipset "NVIDIA MCP73", enabling flash write... OK.
Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI
chipset/strapping detected
No EEPROM/flash device found.
Force read (-f -r -c) requested, forcing chip probe success:
Probing for Macronix MX25L8005, 1024 KB: Found chip "Macronix MX25L8005"
(1024 KB) at physical address 0xfff00000.
Force reading flash... spi_chip_read called, but no SPI chipset/strapping
detected 0
done.
How can I do works?
Are there any hints?
Thanks!
--
Fabrício Ceolin
Hello,
as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and
wonder if I could flash it with coreboot. The box has
Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset.
hovewer the results of the following commands are not encouriging, please
tell me if there is any chance to get coreboot working. Please find attached
the outpoot of the commands.
sudo superiotool -dV > siot.out
lspci -tvnn > lspci.out
sudo flashrom -V
Hi guys
I don't know how usefull is it but there is a bug in cache_as_ram.inc
and cache_as_ram_post.c for the 6fx intel processors. The code disable /
enable the prefetcher in IA32_MISC_ENABLES MSR register.
cache_as_ram.inc :
/* Disable prefetchers */
movl $0x01a0, %eax
rdmsr
orl $((1 << 9) | (1 << 19)), %eax
orl $((1 << 5) | (1 << 7)), %edx
wrmsr
should be
movl $0x01a0, %ecx
Same thing in cache_as_ram_post.c
/* Enable prefetchers */
"movl $0x01a0, %eax\n"
"rdmsr\n"
"andl $~((1 << 9) | (1 << 19)), %eax\n"
"andl $~((1 << 5) | (1 << 7)), %edx\n"
"wrmsr\n"
should be
"movl $0x01a0, %ecx\n"
Regards,
Thomas
