February 2009 - coreboot - mail.coreboot.org

#104: flashrom: Change flash drivers to never erase data before writing

by coreboot

#104: flashrom: Change flash drivers to never erase data before writing ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase write | Dependencies: #103 Patchstatus: there is no patch | ---------------------------------+------------------------------------------ The user should be responsible for ensuring that the flash chip has been erased where new data should be written. At the moment, flashrom will erase at least one full page and then rewrite it, when the user asks to only write a few bytes using -l/-i/-s/-e. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/104> coreboot <http://www.coreboot.org/>

9 years, 10 months

2
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#101: flashrom: Remove pciutils check from Makefile

by coreboot

#101: flashrom: Remove pciutils check from Makefile ---------------------------------------------+------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: pciutils libpci build ldflags | Dependencies: Patchstatus: patch needs review | ---------------------------------------------+------------------------------ The check belongs in a configure script or similar, the check also claims that packages can not be found for any build error, which is not good enough. Has confused more than one user already. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/101> coreboot <http://www.coreboot.org/>

9 years, 10 months

3
6
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#120: flashrom failure to read

by coreboot

#120: flashrom failure to read ---------------------------------+------------------------------------------ Reporter: toc@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Running flashrom -r rom.file results in an output file of all null bytes. Standard output: {{{ Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... tried to set 0xdc to 0x3 on Intel ICH9R failed (WARNING ONLY) FAILED! Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Reading flash... done. }}} Verbose output indicates failure of opcode 0x03. {{{ Reading flash... ich_spi_read_page: offset=0, number=256, buf=0xb7cf0008 Opcode 3 not found. run OPCODE 0x03 failed Error readingdone. }}} Full verbose output attached -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/120> coreboot <http://www.coreboot.org/>

9 years, 10 months

1
25
0 0

#113: problem

by coreboot

#113: problem ---------------------------------+------------------------------------------ Reporter: anonymous | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: adlo | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ there is a bug -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/113> coreboot <http://www.coreboot.org/>

9 years, 10 months

1
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#106: flashrom: Add -T to automatically test all flash chip operations

by coreboot

#106: flashrom: Add -T to automatically test all flash chip operations ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: testing | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Maybe require -f to actually perform the test, since it will potentially fail to restore the flash chip to it's original state. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/106> coreboot <http://www.coreboot.org/>

9 years, 10 months

1
6
0 0

flashrom on MCP73

by Fabrício Ceolin

Hi guys, We are trying to make flashrom work on http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=85... Chipset MCP73 / SIP chipset Macronix MX25L8005. We made modifications using a enable_flash_mcp55 function, but does't work. ./flashrom -V -c MX25L8005 -r -f rom Calibrating delay loop... 627M loops per second, 100 myus = 199 us. OK. No coreboot table found. Found chipset "NVIDIA MCP73", enabling flash write... OK. Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for Macronix MX25L8005, 1024 KB: Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Force reading flash... spi_chip_read called, but no SPI chipset/strapping detected 0 done. How can I do works? Are there any hints? Thanks! -- Fabrício Ceolin

10 years, 1 month

3
4
0 0

#121: flashrom runtime error

by coreboot

#121: flashrom runtime error ---------------------------------+------------------------------------------ Reporter: lymanrb@… | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ I got such errors when running flashrom. {{{ Calibrating delay loop... OK. Can't mmap memory using /dev/mem: Invalid argument }}} My env {{{ Linux xxx 2.6.28-ARCH #1 SMP PREEMPT Sun Jan 18 19:41:52 UTC 2009 x86_64 Intel(R) Core(TM)2 Duo CPU T7250 @ 2.00GHz GenuineIntel GNU/Linux core/pciutils 3.0.3-1 [installed] (base) PCI bus configuration space access library and tools core/zlib 1.2.3.3-3 [installed] (base) A compression/decompression Library $ ./flashrom -R flashrom r3869 }}} -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/121> coreboot <http://www.coreboot.org/>

10 years, 2 months

5
10
0 0

sony vaio pcg sr1k

by misi e

Hello, as I posted on the blog of Uwe, I have a sony vaio pcg sr1k laptop, and wonder if I could flash it with coreboot. The box has Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge chipset. hovewer the results of the following commands are not encouriging, please tell me if there is any chance to get coreboot working. Please find attached the outpoot of the commands. sudo superiotool -dV > siot.out lspci -tvnn > lspci.out sudo flashrom -V

10 years, 3 months

5
10
0 0

msrtool CS5536 interrupt and DIVIL LBAR MSRs

by Peter Stuge

Can someone please review these register definitions? Thank you! //Peter

10 years, 4 months

4
8
0 0

Bug in cache_as_ram.inc and cache_as_ram_post.c

by Thomas Jourdan

Hi guys I don't know how usefull is it but there is a bug in cache_as_ram.inc and cache_as_ram_post.c for the 6fx intel processors. The code disable / enable the prefetcher in IA32_MISC_ENABLES MSR register. cache_as_ram.inc : /* Disable prefetchers */ movl $0x01a0, %eax rdmsr orl $((1 << 9) | (1 << 19)), %eax orl $((1 << 5) | (1 << 7)), %edx wrmsr should be movl $0x01a0, %ecx Same thing in cache_as_ram_post.c /* Enable prefetchers */ "movl $0x01a0, %eax\n" "rdmsr\n" "andl $~((1 << 9) | (1 << 19)), %eax\n" "andl $~((1 << 5) | (1 << 7)), %edx\n" "wrmsr\n" should be "movl $0x01a0, %ecx\n" Regards, Thomas

10 years, 4 months

2
1
0 0

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coreboot February 2009