coreboot February 2009

coreboot@coreboot.org

67 participants
232 discussions

RFC: a "forge" for our various subprojects
by Patrick Georgi 27 Feb '09

27 Feb '09

Hi all, I installed an instance of Indefero (www.indefero.net), a *forge or googlecode alike, with most of our projects at http://www.coresystems.de/~patrick/indefero/. It's a purely experimental setup, but I'd like some feedback on what's good and what isn't, for our use. The reasons for this experiment are: - lack of acceptance of our trac install - imho better usability than trac - a more formalized notion of "projects", with issue tracker, code browser, download area, documentation, developers. - out of the box support for svn and git, with hg around the corner and support for multiple SCMs in the design. If you miss a project in the list, tell me, we can (probably) add it. Libpayload unfortunately doesn't have its own repository, which seems to be a requirement for svn-based projects - hence "probably". The developer of the software seems to be quite responsive to requests and bug reports, so it might be possible to overcome such problems. I'm open to any result (use it, don't use it, wait until scenario $x is better supported, ...), but if it is decided that we want to use this tool, we could put it at a subdomain (code.coreboot.org or whatever), either with the data migrated or a fresh start (depends on how much test "junk" ends up in the database). Regards, Patrick Georgi

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issues with seabios on the m2a-vm
by Ward Vandewege 27 Feb '09

27 Feb '09

Hi all, I'm seeing some weird behavior with seabios on the asus m2a-vm. The machine boots fine with filo: http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-filo.cap If I use seabios as a payload and leave CONFIG_BOOTMENU enabled, seabios hangs on boot - but it's not entirely dead as pushing num lock, caps lock or scroll lock results in this on the serial console: i8042 ctr old=00000061 new=00000060 i8042 ctr old=00000061 new=00000060 I tracked the hang down to the line while (get_keystroke(0) >= 0) ; in src/boot.c. Here's the boot log: http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-seabios-hang.cap If I disable CONFIG_BOOTMENU, seabios does not hang but things go pretty badly: http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-seabios-no-menu.cap The IRQs seem to be messed up, and there seem to be some serious SATA issues with the AHCI driver segfaulting and no sata drives being properly detected by the kernel. This is my config.h: http://ward.vandewege.net/coreboot/m2a-vm/m2a-vm-seabios-no-menu-config.h Any suggestions for what might be going wrong? Ultimately I'd like to try seabios with a sata controller whose option rom hangs the coreboot emulator. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

4 10

grub2.tar Error...
by Lim, Vincent 26 Feb '09

26 Feb '09

Hi All: Just wanted to make sure the grub2.tar from http://www.coreboot.org/GRUB2 is a working version. I download grub2.tar per instructed: ' wget http://coreboot.org/viewmtn/revision/tar/edae9d3e3d999c07b2d8a99f04f2585 86eb79297 -O grub2.tar ' However, when I tried to untar it, I received errors as below: beamer:.../vlim/coreboot[ 191 ] --> tar -xvf grub2.tar tar: This does not look like a tar archive tar: Skipping to next header tar: Archive contains obsolescent base-64 headers tar: Read 264 bytes from grub2.tar tar: Error exit delayed from previous errors Anyone has the same experience as me ? Best Regards, Vincent Best Regards, Vincent Lim SimNow Team Performance CoE Central Engineering T 512.602.1618 F 512.602.7745

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Re: [coreboot] ?
by Corey Osgood 26 Feb '09

26 Feb '09

I don't provide any services like that myself, but I've CC'd the list and someone there should be able to help you out ;) Thanks, Corey On Wed, Feb 25, 2009 at 7:39 PM, n. prince <aprincefromqueens(a)yahoo.com>wrote: > How do one become a coreboot vendor, do you provide classes? thanks > > --- On *Wed, 2/25/09, Corey Osgood <corey.osgood(a)gmail.com>* wrote: > > From: Corey Osgood <corey.osgood(a)gmail.com> > Subject: Re: [coreboot] ? > To: aprincefromqueens(a)yahoo.com > Cc: coreboot(a)coreboot.org > Date: Wednesday, February 25, 2009, 6:02 PM > > > On Wed, Feb 25, 2009 at 12:55 PM, n. prince <aprincefromqueens(a)yahoo.com>wrote: > >> Gentlemen, >> I like to know if you offer a Bios with Coreboot >> pre-installed? >> > > There are vendors who offer systems with coreboot preinstalled: > http://www.coreboot.org/Products > I believe Peter Stuge is still offering Gigabyte M57SLI boards with > coreboot preinstalled as well, but you'd have to contact him directly for > more info. > > >> Can Coreboot be configured to boot in 2 sec. vs. 3? >> > > Boot times are dependent on hardware speed and the complexity of their > initialization mechanism. > > >> Might you support Amd Gigabyte multi-Bios circuitboards, Tyan >> Thunder n3600W motherboards, and Everun notebooks, or circuitboards with >> the Tilera 64 cpu. >> > > You can find a list of currently supported motherboards here: > http://www.coreboot.org/Supported_Motherboards. Boards with Gigabyte's > multi-BIOS system have been ported to in the past, and there's probably info > on the web site on how it works. The Tyan board you've mentioned is not > currently supported, but it's based on a supported chipset, so theoretically > it shouldn't be hard to port. No Everun products are currently supported, > and without public datasheets for the embedded controller, it's very > difficult to support notebooks. The Tilera 64 cpu is not explicitly > supported. > > Do you have raid solution capablity with multi-; ssd and pci express >> cards combo capability. >> > > I don't know honestly what's required for RAID from a BIOS point of view, > aside from the raid controller firmware, but I assume there's a payload that > can handle it, probably SeaBIOS. See here for more info on the various > payloads supported by coreboot: http://www.coreboot.org/Payloads > > > >> Also might you have an AMI Aptio alternative? >> > > > I know there was some work a while back to get Tiano working with coreboot, > but I don't know what ever happened with it. Coreboot does work with Open > Firmware or OpenBIOS as a payload. > > -Corey > > >

1 0

I can not find "xpboot.diff"
by 김용우 26 Feb '09

26 Feb '09

2 1

About "xpboot.diff"
by 김용우 26 Feb '09

26 Feb '09

1 0

?
by n. prince 26 Feb '09

26 Feb '09

Gentlemen, I like to know if you offer a Bios with Coreboot pre-installed?Can Coreboot be configured to boot in 2 sec. vs. 3?Might you support Amd Gigabyte multi-Bios circuitboards, Tyan Thunder n3600W motherboards, and Everun notebooks, or circuitboards with the Tilera 64 cpu. Do you have raid solution capablity with multi-; ssd and pci express cards combo capability. Also might you have an AMI Aptio alternative? Thanks

2 1

Plugin support
by Myles Watson 25 Feb '09

25 Feb '09

I implemented the *_PLUGIN_SUPPORT config options for v3. I thought it was simple since I was just enabling the defines already in the code. In retrospect I may have implemented them backward. The space in the ROM consumed by PLUGIN_SUPPORT is very small if you already have support for that bus. If you don't have support for the bus it could be significant. I wanted to make it so that e.g. HYPERTRANSPORT_PLUGIN_SUPPORT was the default if you had HYPERTRANSPORT_SUPPORT. I'd also like people to be able to select CARDBUS_PLUGIN_SUPPORT or NO_CARDBUS_PLUGIN_SUPPORT. Maybe we could get rid of the *PLUGIN_SUPPORT options all together and just allow the developer to select CARDBUS_SUPPORT or REMOVE_CARDBUS_SUPPORT directly? We don't want people to deselect HYPERTRANSPORT_SUPPORT when they have an Opteron, though. Could I get some feedback on what people want? It's very low on my priority list, but I'm willing to take ownership since I put it there. Thanks, Myles

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r1140 - in coreboot-v3: . device
by svn＠coreboot.org 25 Feb '09

25 Feb '09

Author: myles Date: 2009-02-25 18:50:38 +0100 (Wed, 25 Feb 2009) New Revision: 1140 Modified: coreboot-v3/Kconfig coreboot-v3/device/Kconfig coreboot-v3/device/Makefile coreboot-v3/device/hypertransport.c coreboot-v3/device/pci_device.c Log: This patch removes all *_PLUGIN_SUPPORT options and replaces most *_SUPPORT options with NO_*_SUPPORT options. This means that you have to specify that you want a smaller BIOS, otherwise you get full functionality. HyperTransport is the only exception for a couple of reasons. HT requires a mainboard.h file which not all mainboards have, and it's less likely to be "plugged in" to a board that doesn't have some onboard HT. It also fixes a trivial typo in Kconfig (paylaod -> payload) Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2009-02-24 03:38:37 UTC (rev 1139) +++ coreboot-v3/Kconfig 2009-02-25 17:50:38 UTC (rev 1140) @@ -94,15 +94,15 @@ # These are used for internal purposes only: # Buses: -config PCIX_SUPPORT +config NO_PCIX_SUPPORT boolean -config PCIE_SUPPORT +config NO_PCIE_SUPPORT boolean config HYPERTRANSPORT_SUPPORT boolean -config AGP_SUPPORT +config NO_AGP_SUPPORT boolean -config CARDBUS_SUPPORT +config NO_CARDBUS_SUPPORT boolean # Northbridges: @@ -124,19 +124,14 @@ config SOUTHBRIDGE_INTEL_I82371EB boolean config SOUTHBRIDGE_NVIDIA_CK804 - select PCIE_SUPPORT boolean config SOUTHBRIDGE_NVIDIA_MCP55 - select PCIE_SUPPORT boolean config SOUTHBRIDGE_AMD_AMD8151 - select AGP_SUPPORT boolean config SOUTHBRIDGE_AMD_AMD8132 - select PCIX_SUPPORT boolean config SOUTHBRIDGE_AMD_AMD8131 - select PCIX_SUPPORT boolean config SOUTHBRIDGE_AMD_AMD8111 boolean @@ -174,7 +169,7 @@ bool "Include ELF payload loader" default n help - This option allows an unparsed ELF paylaod to be added and loaded. + This option allows an unparsed ELF payload to be added and loaded. choice prompt "Payload type" Modified: coreboot-v3/device/Kconfig =================================================================== --- coreboot-v3/device/Kconfig 2009-02-24 03:38:37 UTC (rev 1139) +++ coreboot-v3/device/Kconfig 2009-02-25 17:50:38 UTC (rev 1140) @@ -123,44 +123,33 @@ Initialize onboard VGA chips before any plugin VGA cards are initialized. -menu "Plugin Support" +menu "Remove Bus Support (for size reasons)" depends EXPERT -config PCIX_PLUGIN_SUPPORT - bool "Support for devices that provide PCI-X and aren't in the dts." - select PCIX_SUPPORT +config NO_PCIX_SUPPORT + bool "Remove support for PCI-X." default false help - Compile in the drivers for cards that provide PCI-X. + Don't compile in the drivers for cards that provide PCI-X. -config PCIE_PLUGIN_SUPPORT - bool "Support for devices that provide PCI-e and aren't in the dts." - select PCIE_SUPPORT +config NO_PCIE_SUPPORT + bool "Remove support for PCI-Express." default false help - Compile in the drivers for cards that provide PCI-e. + Don't compile in the drivers for cards that provide PCI-e. -config HYPERTRANSPORT_PLUGIN_SUPPORT - bool "Support for devices that provide HT and aren't in the dts." - select HYPERTRANSPORT_SUPPORT +config NO_AGP_SUPPORT + bool "Remove support for AGP." default false help - Compile in the drivers for cards that provide HT. + Don't compile in the drivers for cards that provide AGP. -config AGP_PLUGIN_SUPPORT - bool "Support for devices that provide AGP and aren't in the dts." - select AGP_SUPPORT +config NO_CARDBUS_SUPPORT + bool "Remove support for CardBus." default false help - Compile in the drivers for cards that provide AGP. + Don't compile in the drivers for cards that provide CardBus. -config CARDBUS_PLUGIN_SUPPORT - bool "Support for devices that provide Cardbus and aren't in the dts." - select CARDBUS_SUPPORT - default false - help - Compile in the drivers for cards that provide Cardbus. - endmenu endmenu #Devices Modified: coreboot-v3/device/Makefile =================================================================== --- coreboot-v3/device/Makefile 2009-02-24 03:38:37 UTC (rev 1139) +++ coreboot-v3/device/Makefile 2009-02-25 17:50:38 UTC (rev 1140) @@ -32,19 +32,19 @@ STAGE2_DEVICE_SRC += hypertransport.c endif -ifeq ($(CONFIG_PCIX_SUPPORT),y) +ifneq ($(CONFIG_NO_PCIX_SUPPORT),y) STAGE2_DEVICE_SRC += pcix_device.c endif -ifeq ($(CONFIG_PCIE_SUPPORT),y) +ifneq ($(CONFIG_NO_PCIE_SUPPORT),y) STAGE2_DEVICE_SRC += pcie_device.c endif -ifeq ($(CONFIG_CARDBUS_SUPPORT),y) +ifneq ($(CONFIG_NO_CARDBUS_SUPPORT),y) STAGE2_DEVICE_SRC += cardbus_device.c endif -ifeq ($(CONFIG_AGP_SUPPORT),y) +ifneq ($(CONFIG_NO_AGP_SUPPORT),y) STAGE2_DEVICE_SRC += agp_device.c endif Modified: coreboot-v3/device/hypertransport.c =================================================================== --- coreboot-v3/device/hypertransport.c 2009-02-24 03:38:37 UTC (rev 1139) +++ coreboot-v3/device/hypertransport.c 2009-02-25 17:50:38 UTC (rev 1140) @@ -41,6 +41,15 @@ #include <lib.h> #include <lapic.h> +/* These defines are for PLUGIN_SUPPORT. */ +#ifndef HT_CHAIN_UNITID_BASE +#define HT_CHAIN_UNITID_BASE 0 +#endif + +#ifndef HT_CHAIN_END_UNITID_BASE +#define HT_CHAIN_END_UNITID_BASE 0 +#endif + #define OPT_HT_LINK 0 static struct device *ht_scan_get_devs(struct device **old_devices) Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2009-02-24 03:38:37 UTC (rev 1139) +++ coreboot-v3/device/pci_device.c 2009-02-25 17:50:38 UTC (rev 1140) @@ -32,19 +32,19 @@ #include <device/pci.h> #include <device/pci_ids.h> -#ifdef CONFIG_PCIX_PLUGIN_SUPPORT +#ifndef CONFIG_NO_PCIX_SUPPORT #include <device/pcix.h> #endif -#ifdef CONFIG_AGP_PLUGIN_SUPPORT +#ifndef CONFIG_NO_AGP_SUPPORT #include <device/agp.h> #endif -#ifdef CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT +#ifdef CONFIG_HYPERTRANSPORT_SUPPORT #include <device/hypertransport.h> #endif -#ifdef CONFIG_PCIE_PLUGIN_SUPPORT +#ifndef CONFIG_NO_PCIE_SUPPORT #include <device/pcie.h> #endif -#ifdef CONFIG_CARDBUS_PLUGIN_SUPPORT +#ifndef CONFIG_NO_CARDBUS_SUPPORT #include <device/cardbus.h> #endif @@ -792,7 +792,7 @@ */ static const struct device_operations *get_pci_bridge_ops(struct device *dev) { -#ifdef CONFIG_PCIX_PLUGIN_SUPPORT +#ifndef CONFIG_NO_PCIX_SUPPORT unsigned int pcix_pos; pcix_pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (pcix_pos) { @@ -801,12 +801,12 @@ return &default_pcix_ops_bus; } #endif -#ifdef CONFIG_AGP_PLUGIN_SUPPORT +#ifndef CONFIG_NO_AGP_SUPPORT /* How do I detect an PCI to AGP bridge? */ #warning AGP detection not implemented, so AGP bridge plugin not supported. #endif -#ifdef CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT +#ifdef CONFIG_HYPERTRANSPORT_SUPPORT unsigned int ht_pos; ht_pos = 0; while ((ht_pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, ht_pos))) { @@ -821,7 +821,7 @@ } } #endif -#ifdef CONFIG_PCIE_PLUGIN_SUPPORT +#ifndef CONFIG_NO_PCIE_SUPPORT unsigned int pcie_pos; pcie_pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); if (pcie_pos) { @@ -897,7 +897,7 @@ else dev->ops = get_pci_bridge_ops(dev); break; -#ifdef CONFIG_CARDBUS_PLUGIN_SUPPORT +#ifndef CONFIG_NO_CARDBUS_SUPPORT case PCI_HEADER_TYPE_CARDBUS: dev->ops = &default_cardbus_ops_bus; break;

1 0

AGP Support in V3
by Myles Watson 25 Feb '09

25 Feb '09

AGP support looks like it is just a placeholder. Is there any reason we shouldn't just have it use default pci ops? The only thing it does now is find the AGP capability. There's a comment that says that the OS is responsible for AGP tuning. Thanks, Myles

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coreboot February 2009