coreboot November 2009

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[PATCH] Fix MP table initialization
by Magnus Christensson 26 Nov '09

26 Nov '09

Fixes a problem introduced in one of my earlier patches. M.

2 2

#147: Linux kernel halts when scanning the PCI bus below 0:14.4 on RS690
by coreboot 25 Nov '09

25 Nov '09

#147: Linux kernel halts when scanning the PCI bus below 0:14.4 on RS690 -----------------------------------+---------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: rs690 pci scan halt | Dependencies: Patchstatus: patch needs work | -----------------------------------+---------------------------------------- 유택연 wrote: Old the onboard pci driver is still seems to be needed as a dummy driver. On RS690 based system like dbm690t and pistachio, linux kernel is halted on scan PCI bus below 00:14:04 node. A patch to again make graphics an onboard device on the amd/pistachio mainboard is available at http://patchwork.coreboot.org/patch/592/ Myles Watson wrote: I think this is a symptom of a broken RS690 driver, although it may be related to another problem. The right way to fix it is to figure out why it's needed, since it shouldn't be. I think the most likely thing is that the RS690 driver is trying to initialize the graphics device, and shouldn't. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/147> coreboot <http://www.coreboot.org/>

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Re: [coreboot] [v2] r4925 makes my linux hang
by Bao, Zheng 25 Nov '09

25 Nov '09

R4925 makes my linux hang. Output is attached. My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700). But dbm690t works well. I don't know why. Zheng -----Original Message----- From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of svn(a)coreboot.org Sent: Saturday, November 07, 2009 7:42 AM To: coreboot(a)coreboot.org Subject: [coreboot] [v2] r4925 - in trunk/src: devices driversinclude/device mainboard/amd/dbm690t mainboard/amd/pistachiomainboard/arima/hdama mainboard/artecgroup/dbe61/realmodemainboard/asi/mb_5blmp mainboard/asus/mew-vmmainboard/broadcom/blast mainboard/digita Author: myles Date: 2009-11-06 23:42:26 +0000 (Fri, 06 Nov 2009) New Revision: 4925 Removed: trunk/src/drivers/pci/ Modified: trunk/src/devices/pci_device.c trunk/src/devices/pci_rom.c trunk/src/drivers/Makefile.inc trunk/src/include/device/device.h trunk/src/mainboard/amd/dbm690t/Config.lb trunk/src/mainboard/amd/dbm690t/devicetree.cb trunk/src/mainboard/amd/pistachio/Config.lb trunk/src/mainboard/amd/pistachio/devicetree.cb trunk/src/mainboard/arima/hdama/Config.lb trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c trunk/src/mainboard/asi/mb_5blmp/Config.lb trunk/src/mainboard/asi/mb_5blmp/devicetree.cb trunk/src/mainboard/asus/mew-vm/Config.lb trunk/src/mainboard/asus/mew-vm/devicetree.cb trunk/src/mainboard/broadcom/blast/Config.lb trunk/src/mainboard/broadcom/blast/devicetree.cb trunk/src/mainboard/digitallogic/msm586seg/Config.lb trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb trunk/src/mainboard/emulation/qemu-x86/mainboard.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb trunk/src/mainboard/hp/dl145_g3/Config.lb trunk/src/mainboard/hp/dl145_g3/devicetree.cb trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb trunk/src/mainboard/ibm/e326/Config.lb trunk/src/mainboard/ibm/e326/devicetree.cb trunk/src/mainboard/intel/d945gclf/Config.lb trunk/src/mainboard/intel/d945gclf/devicetree.cb trunk/src/mainboard/intel/xe7501devkit/Config.lb trunk/src/mainboard/intel/xe7501devkit/devicetree.cb trunk/src/mainboard/iwill/dk8_htx/Config.lb trunk/src/mainboard/iwill/dk8_htx/devicetree.cb trunk/src/mainboard/kontron/986lcd-m/Config.lb trunk/src/mainboard/kontron/986lcd-m/devicetree.cb trunk/src/mainboard/kontron/kt690/Config.lb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/mitac/6513wu/Config.lb trunk/src/mainboard/mitac/6513wu/devicetree.cb trunk/src/mainboard/msi/ms6178/Config.lb trunk/src/mainboard/msi/ms6178/devicetree.cb trunk/src/mainboard/msi/ms9185/Config.lb trunk/src/mainboard/msi/ms9185/devicetree.cb trunk/src/mainboard/msi/ms9282/Config.lb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/nec/powermate2000/Config.lb trunk/src/mainboard/nec/powermate2000/devicetree.cb trunk/src/mainboard/newisys/khepri/Config.lb trunk/src/mainboard/rca/rm4100/Config.lb trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/sunw/ultra40/Config.lb trunk/src/mainboard/sunw/ultra40/devicetree.cb trunk/src/mainboard/supermicro/h8dme/Config.lb trunk/src/mainboard/supermicro/h8dme/devicetree.cb trunk/src/mainboard/supermicro/h8dmr/Config.lb trunk/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/technexion/tim5690/Config.lb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/Config.lb trunk/src/mainboard/technexion/tim8690/devicetree.cb trunk/src/mainboard/technologic/ts5300/Config.lb trunk/src/mainboard/technologic/ts5300/devicetree.cb trunk/src/mainboard/thomson/ip1000/Config.lb trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/tyan/s2735/Config.lb trunk/src/mainboard/tyan/s2735/devicetree.cb trunk/src/mainboard/tyan/s2850/Config.lb trunk/src/mainboard/tyan/s2850/devicetree.cb trunk/src/mainboard/tyan/s2875/Config.lb trunk/src/mainboard/tyan/s2875/devicetree.cb trunk/src/mainboard/tyan/s2880/Config.lb trunk/src/mainboard/tyan/s2880/devicetree.cb trunk/src/mainboard/tyan/s2881/Config.lb trunk/src/mainboard/tyan/s2881/devicetree.cb trunk/src/mainboard/tyan/s2882/Config.lb trunk/src/mainboard/tyan/s2882/devicetree.cb trunk/src/mainboard/tyan/s2885/Config.lb trunk/src/mainboard/tyan/s2885/devicetree.cb trunk/src/mainboard/tyan/s2891/devicetree.cb trunk/src/mainboard/tyan/s2892/devicetree.cb trunk/src/mainboard/tyan/s2895/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/Config.lb trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb trunk/src/mainboard/tyan/s4880/Config.lb trunk/src/mainboard/tyan/s4880/devicetree.cb trunk/src/mainboard/tyan/s4882/Config.lb trunk/src/mainboard/tyan/s4882/devicetree.cb trunk/src/mainboard/via/epia/Config.lb trunk/src/mainboard/via/epia/devicetree.cb trunk/src/mainboard/via/vt8454c/Config.lb trunk/src/mainboard/via/vt8454c/devicetree.cb trunk/src/northbridge/via/cn400/vga.c trunk/src/northbridge/via/cn700/vga.c trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vx800/vga.c trunk/src/southbridge/nvidia/ck804/chip.h trunk/src/southbridge/nvidia/ck804/ck804.c Log: Remove drivers/pci/onboard. The only purpose was for option ROMs, which are now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/pci_device.c =================================================================== --- trunk/src/devices/pci_device.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/devices/pci_device.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -285,11 +285,6 @@ unsigned long value; resource_t moving; - if ((dev->on_mainboard) && (dev->rom_address == 0)) { - /* Skip it if rom_address is not set in the MB Config.lb. */ - return; - } - /* Initialize the resources to nothing. */ resource = new_resource(dev, index); @@ -326,18 +321,6 @@ } resource->flags = 0; } - - /* For on board device with embedded ROM image, the ROM image is at - * fixed address specified in the Config.lb, the dev->rom_address is - * inited by driver_pci_onboard_ops::enable_dev() */ - if ((dev->on_mainboard) && (dev->rom_address != 0)) { - resource->base = dev->rom_address; - /* The resource allocator needs the size to be non-zero. */ - resource->size = 0x100; - resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - compact_resources(dev); } Modified: trunk/src/devices/pci_rom.c =================================================================== --- trunk/src/devices/pci_rom.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/devices/pci_rom.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -31,42 +31,37 @@ struct rom_header * pci_rom_probe(struct device *dev) { - unsigned long rom_address = 0; struct rom_header *rom_header; struct pci_data *rom_data; - void *v; - /* if it's in FLASH, then it's as if dev->on_mainboard was true */ - v = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - printk_debug("In cbfs, rom address for %s = %p\n", - dev_path(dev), v); - if (v) { - dev->rom_address = (u32)v; - dev->on_mainboard = 1; - } + /* If it's in FLASH, then don't check device for ROM. */ + rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - if (dev->on_mainboard) { - // in case some device PCI_ROM_ADDRESS can not be set or readonly - rom_address = dev->rom_address; - printk_debug("On mainboard, rom address for %s = %lx\n", - dev_path(dev), rom_address); + if (rom_header) { + printk_debug("In cbfs, rom address for %s = %p\n", + dev_path(dev), rom_header); } else { + unsigned long rom_address; + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); - printk_debug("On card, rom address for %s = %lx\n", - dev_path(dev), rom_address); - } - if (rom_address == 0x00000000 || rom_address == 0xffffffff) { - return NULL; - } + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { + #if CONFIG_BOARD_EMULATION_QEMU_X86 + rom_address = 0xc0000; + #else + return NULL; + #endif + } else { + /* enable expansion ROM address decoding */ + pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address|PCI_ROM_ADDRESS_ENABLE); + } - if(!dev->on_mainboard) { - /* enable expansion ROM address decoding */ - pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); + printk_debug("On card, rom address for %s = %lx\n", + dev_path(dev), rom_address); + rom_header = (struct rom_header *)rom_address; } - rom_header = (struct rom_header *)rom_address; printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n", le32_to_cpu(rom_header->signature), rom_header->size * 512, le32_to_cpu(rom_header->data)); @@ -76,11 +71,12 @@ return NULL; } - rom_data = (struct pci_data *) ((void *)rom_header + le32_to_cpu(rom_header->data)); + rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data)); + printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) { - printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", + printk_err("ID mismatch: Vendor ID %04x, Device ID %04x\n", rom_data->vendor, rom_data->device); return NULL; } @@ -90,7 +86,8 @@ rom_data->type); if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { printk_debug("Class Code mismatch ROM %08x, dev %08x\n", - (rom_data->class_hi << 8) | rom_data->class_lo, dev->class); + (rom_data->class_hi << 8) | rom_data->class_lo, + dev->class); //return NULL; } Modified: trunk/src/drivers/Makefile.inc =================================================================== --- trunk/src/drivers/Makefile.inc 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/drivers/Makefile.inc 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,3 +1,2 @@ -subdirs-y += pci subdirs-y += generic/debug subdirs-y += ati/ragexl Modified: trunk/src/include/device/device.h =================================================================== --- trunk/src/include/device/device.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/include/device/device.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -70,7 +70,6 @@ unsigned int enabled : 1; /* set if we should enable the device */ unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int on_mainboard : 1; - unsigned long rom_address; u8 command; Modified: trunk/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -156,9 +156,7 @@ device pci 0.0 on end # HT 0x7910 # device pci 0.1 off end # CLK device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.0 on end # HT 0x7910 # device pci 0.1 off end # CLK device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -177,9 +177,7 @@ device pci 0.1 on end # USB1 device pci 0.2 off end # USB 2.0 device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - end + device pci 6.0 on end # ATI Rage XL ## PCI Slot 5 (correct?) #chip drivers/generic/generic # device pci 5.0 on Modified: trunk/src/mainboard/arima/hdama/devicetree.cb =================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -73,9 +73,7 @@ device pci 0.1 on end # USB1 device pci 0.2 off end # USB 2.0 device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - end + device pci 6.0 on end # ATI Rage XL ## PCI Slot 5 (correct?) #chip drivers/generic/generic # device pci 5.0 on Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h =================================================================== --- trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,10 +1,6 @@ #ifndef PCI_REALMODE_H #define PCI_REALMODE_H -struct drivers_pci_realmode_config -{ - unsigned long rom_address; -}; //struct chip_operations; extern struct chip_operations drivers_pci_realmode_ops; Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c =================================================================== --- trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -74,36 +74,6 @@ emulator to successfully run this bios. */ - - - -/* - Modified to be an universal driver for loading VGA ROMs. - Aug 2006, anti.sullin(a)artecdesign.ee, Artec Design - - USAGE: - define in your motherboard Config.lb file in device hierarchy - around the VGA pci device realmode chip and define its rom address. - Rom address is read from Config.lb, this rom is then copied to 0xC000 and then excecuted - - chip drivers/pci/realmode - device pci 1.1 on end # VGA - register "rom_address" = "0xfffc0000" # at the beginning of 256k - end - - then, chip enable is called at this list first traversal, and this sets - up device's init callback. Device init is called during last list traversal and - so, other hw should be already initialized to run vga bios successfully. -*/ - - - - - - - - - /* Declare a temporary global descriptor table - necessary because the Core part of the bios no longer sets up any 16 bit segments */ __asm__ ( @@ -918,8 +888,6 @@ // code to make vga init go through the emulator - as of yet this does not workfor the epia-m dev->on_mainboard=1; - dev->rom_address = (void *)cfg->rom_address; - pci_dev_init(dev); // code to make vga init run in real mode - does work but against the current coreboot philosophy Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -135,11 +135,6 @@ device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -37,11 +37,6 @@ device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -97,18 +97,14 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video - #chip drivers/pci/onboard # device pci 1.0 on end - #end end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" device pci 1e.0 on # PCI Bridge - #chip drivers/pci/onboard # device pci 1.0 on end - #end end device pci 1f.0 on # ISA/LPC? Bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb =================================================================== --- trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,18 +2,14 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video - #chip drivers/pci/onboard # device pci 1.0 on end - #end end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" device pci 1e.0 on # PCI Bridge - #chip drivers/pci/onboard # device pci 1.0 on end - #end end device pci 1f.0 on # ISA/LPC? Bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -207,21 +207,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - end + device pci 4.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - - end # device pci 18.0 device pci 18.0 on end Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb =================================================================== --- trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -105,21 +105,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - end + device pci 4.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - - end # device pci 18.0 device pci 18.0 on end Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -102,13 +102,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - - chip drivers/pci/onboard - device pci 12.0 on end # enet - end - chip drivers/pci/onboard - device pci 14.0 on end # 69000 - end + device pci 12.0 on end # enet + device pci 14.0 on end # 69000 # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,13 +1,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - - chip drivers/pci/onboard - device pci 12.0 on end # enet - end - chip drivers/pci/onboard - device pci 14.0 on end # 69000 - end + device pci 12.0 on end # enet + device pci 14.0 on end # 69000 # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c =================================================================== --- trunk/src/mainboard/emulation/qemu-x86/mainboard.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -16,7 +16,6 @@ * force coreboot to use it. */ dev->on_mainboard = 1; - dev->rom_address = 0xc0000; /* Now do the usual initialization */ pci_dev_init(dev); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -178,9 +178,7 @@ chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - end end device pci 2.0 on # LPC chip superio/ite/it8716f Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -11,9 +11,7 @@ chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - end end device pci 2.0 on # LPC chip superio/ite/it8716f Modified: trunk/src/mainboard/hp/dl145_g3/Config.lb =================================================================== --- trunk/src/mainboard/hp/dl145_g3/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/dl145_g3/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -195,15 +195,6 @@ device pci 2.1 on end # USB device pci 2.2 on end # USB device pci 3.0 on end # VGA - - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end end end device pci 18.0 on end Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/dl145_g3/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -72,15 +72,6 @@ device pci 2.1 on end # USB device pci 2.2 on end # USB device pci 3.0 on end # VGA - - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end end end device pci 18.0 on end Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -76,9 +76,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -7,9 +7,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -125,9 +125,7 @@ device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # ATI Rage XL - end + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366 Modified: trunk/src/mainboard/ibm/e326/devicetree.cb =================================================================== --- trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # ATI Rage XL - end + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366 Modified: trunk/src/mainboard/intel/d945gclf/Config.lb =================================================================== --- trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -150,9 +150,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -28,9 +28,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/xe7501devkit/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -127,9 +127,7 @@ device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) device pci 1e.0 on # Hub to PCI bridge - chip drivers/pci/onboard # VGA ROM - device pci 0.0 on end - end + device pci 0.0 on end end device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -25,9 +25,7 @@ device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) device pci 1e.0 on # Hub to PCI bridge - chip drivers/pci/onboard # VGA ROM - device pci 0.0 on end - end + device pci 0.0 on end end device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47b272 Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -232,9 +232,6 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/pci/onboard - # device pci 6.0 on end - #end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -24,9 +24,6 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/pci/onboard - # device pci 6.0 on end - #end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -153,9 +153,7 @@ device pci 00.0 on end # host bridge # autodetect 0:1.0 because it might or might not be there. # device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -9,9 +9,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller chip southbridge/intel/i82801gx Modified: trunk/src/mainboard/kontron/kt690/Config.lb =================================================================== --- trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/mitac/6513wu/Config.lb =================================================================== --- trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -80,9 +80,7 @@ end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb =================================================================== --- trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -26,9 +26,7 @@ end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" Modified: trunk/src/mainboard/msi/ms6178/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -26,9 +26,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -207,29 +207,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - end - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end - + device pci 3.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -73,29 +73,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - end - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end - + device pci 3.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end Modified: trunk/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -278,27 +278,21 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on #P2P - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # P2P device pci 7.0 on end # reserve device pci 8.0 on end # MAC0 device pci 9.0 on end # MAC1 device pci a.0 on device pci 0.0 on - chip drivers/pci/onboard - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 end end # 0x376 device pci b.0 on end # PCI E 0x374 device pci c.0 on end device pci d.0 on #SAS - chip drivers/pci/onboard - device pci 0.0 on end - end + device pci 0.0 on end end # PCI E 1 0x378 device pci e.0 on end # PCI E 0 0x375 device pci f.0 on end #PCI E 0x377 pci_E slot Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -137,27 +137,21 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on #P2P - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # P2P device pci 7.0 on end # reserve device pci 8.0 on end # MAC0 device pci 9.0 on end # MAC1 device pci a.0 on device pci 0.0 on - chip drivers/pci/onboard - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 end end # 0x376 device pci b.0 on end # PCI E 0x374 device pci c.0 on end device pci d.0 on #SAS - chip drivers/pci/onboard - device pci 0.0 on end - end + device pci 0.0 on end end # PCI E 1 0x378 device pci e.0 on end # PCI E 0 0x375 device pci f.0 on end #PCI E 0x377 pci_E slot Modified: trunk/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,11 +75,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # end - end + device pci 1.0 off end # Onboard video chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb =================================================================== --- trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -6,11 +6,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # end - end + device pci 1.0 off end # Onboard video chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1" Modified: trunk/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/src/mainboard/newisys/khepri/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/newisys/khepri/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -98,8 +98,6 @@ config chip.h -# FIXME: ROM for onboard VGA - chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_940 Modified: trunk/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb =================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,9 +1,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/src/mainboard/sunw/ultra40/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/sunw/ultra40/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -210,8 +210,6 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" -# register "nic_rom_address" = "0xfff80000" # 64k -# register "raid_rom_address" = "0xfff90000" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end @@ -243,7 +241,6 @@ device pci c.0 off end # PCI E 2 device pci d.0 off end # PCI E 1 device pci e.0 on end # PCI E 0 -# register "nic_rom_address" = "0xfff80000" # 64k register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb =================================================================== --- trunk/src/mainboard/sunw/ultra40/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/sunw/ultra40/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -106,8 +106,6 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" -# register "nic_rom_address" = "0xfff80000" # 64k -# register "raid_rom_address" = "0xfff90000" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end @@ -139,7 +137,6 @@ device pci c.0 off end # PCI E 2 device pci d.0 off end # PCI E 1 device pci e.0 on end # PCI E 0 -# register "nic_rom_address" = "0xfff80000" # 64k register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -254,9 +254,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -92,9 +92,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -276,9 +276,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -112,9 +112,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -280,9 +280,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,9 +114,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/technexion/tim5690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b Modified: trunk/src/mainboard/technologic/ts5300/Config.lb =================================================================== --- trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -104,12 +104,6 @@ device pci_domain 0 on device pci 0.0 on end -# chip drivers/pci/onboard -# device pci 12.0 on end # enet -# end -# chip drivers/pci/onboard -# device pci 14.0 on end # 69000 -# end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb =================================================================== --- trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,12 +2,6 @@ device pci_domain 0 on device pci 0.0 on end -# chip drivers/pci/onboard -# device pci 12.0 on end # enet -# end -# chip drivers/pci/onboard -# device pci 14.0 on end # 69000 -# end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end Modified: trunk/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb =================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,9 +1,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" Modified: trunk/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2735/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2735/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -100,10 +100,8 @@ chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan - device pci 1.1 on end - end + device pci 1.0 on end # intel lan + device pci 1.1 on end end device pci 1e.0 on end device pci 1f.0 on end @@ -117,12 +115,8 @@ device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan 10/100 - end - chip drivers/pci/onboard - device pci 2.0 on end # ati - end + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end device pci 1f.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2735/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2735/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -6,10 +6,8 @@ chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan - device pci 1.1 on end - end + device pci 1.0 on end # intel lan + device pci 1.1 on end end device pci 1e.0 on end device pci 1f.0 on end @@ -23,12 +21,8 @@ device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan 10/100 - end - chip drivers/pci/onboard - device pci 2.0 on end # ati - end + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end device pci 1f.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -119,9 +119,7 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci b.0 on end - end + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -17,9 +17,7 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci b.0 on end - end + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -123,9 +123,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -113,10 +113,8 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end #broadcom - device pci 9.1 on end - end + device pci 9.0 on end #broadcom + device pci 9.1 on end # chip drivers/lsi/53c1030 # device pci a.0 on end # device pci a.1 on end @@ -135,12 +133,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end #some sata - end - chip drivers/pci/onboard - device pci 6.0 on end #adti - end + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -11,10 +11,8 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end #broadcom - device pci 9.1 on end - end + device pci 9.0 on end #broadcom + device pci 9.1 on end # chip drivers/lsi/53c1030 # device pci a.0 on end # device pci a.1 on end @@ -33,12 +31,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end #some sata - end - chip drivers/pci/onboard - device pci 6.0 on end #adti - end + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -115,14 +115,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - chip drivers/pci/onboard - device pci a.0 on end # Adaptic - device pci a.1 on end - end + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -136,12 +132,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # SiI - end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 5.0 on end # SiI + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -13,14 +13,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - chip drivers/pci/onboard - device pci a.0 on end # Adaptic - device pci a.1 on end - end + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -34,12 +30,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # SiI - end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 5.0 on end # SiI + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,14 +114,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 6.0 on end # adaptec - device pci 6.1 on end - end - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -135,16 +131,11 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end #intel 10/100 - end + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -12,14 +12,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 6.0 on end # adaptec - device pci 6.1 on end - end - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -33,16 +29,11 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end #intel 10/100 - end + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2885/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2885/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2885/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,9 +121,7 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5703 - end + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -137,9 +135,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci b.0 on end # SiI 3114 - end + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2885/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2885/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -19,9 +19,7 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5703 - end + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -35,9 +33,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci b.0 on end # SiI 3114 - end + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2891/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2891/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -104,9 +104,7 @@ device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 7.0 on end - end + device pci 7.0 on end end device pci a.0 off end # NIC device pci b.0 off end # PCI E 3 @@ -127,10 +125,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 1.1 on end end Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2892/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2892/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -105,12 +105,9 @@ device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end - end + device pci 6.0 on end + # end + device pci 8.0 on end end device pci a.0 off end # NIC device pci b.0 off end # PCI E 3 @@ -131,10 +128,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 1.1 on end end Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2895/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2895/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -111,10 +111,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 6.0 on end # lsi scsi - device pci 6.1 on end - end + device pci 6.0 on end # lsi scsi + device pci 6.1 on end end device pci 1.1 on end end Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -279,9 +279,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -112,9 +112,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC Modified: trunk/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -116,10 +116,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -133,9 +131,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -19,10 +19,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -36,9 +34,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,10 +114,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -132,12 +130,9 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 5.0 on end #SiI - end + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -17,10 +17,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -35,12 +33,9 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 5.0 on end #SiI - end + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf Modified: trunk/src/mainboard/via/epia/Config.lb =================================================================== --- trunk/src/mainboard/via/epia/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/epia/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -96,10 +96,7 @@ device pci_domain 0 on device pci 0.0 on end # Northbridge # device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end + # device pci 0.0 on end # Integrated VGA # end chip southbridge/via/vt8231 register "enable_native_ide" = "0" Modified: trunk/src/mainboard/via/epia/devicetree.cb =================================================================== --- trunk/src/mainboard/via/epia/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/epia/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,10 +2,7 @@ device pci_domain 0 on device pci 0.0 on end # Northbridge # device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end + # device pci 0.0 on end # Integrated VGA # end chip southbridge/via/vt8231 register "enable_native_ide" = "0" Modified: trunk/src/mainboard/via/vt8454c/Config.lb =================================================================== --- trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,9 +121,7 @@ device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller device pci 1.0 on # PCI Bridge - chip drivers/pci/onboard - device pci 0.0 on end - end # Onboard Video + device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA #device pci f.1 on end # IDE Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb =================================================================== --- trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -12,9 +12,7 @@ device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller device pci 1.0 on # PCI Bridge - chip drivers/pci/onboard - device pci 0.0 on end - end # Onboard Video + device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA #device pci f.1 on end # IDE Modified: trunk/src/northbridge/via/cn400/vga.c =================================================================== --- trunk/src/northbridge/via/cn400/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cn400/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,15 +121,8 @@ #endif } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static const struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/cn700/vga.c =================================================================== --- trunk/src/northbridge/via/cn700/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cn700/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -101,15 +101,8 @@ memset(0xf0000, 0, 0x10000); } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static const struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/cx700/cx700_vga.c =================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cx700/cx700_vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -97,15 +97,8 @@ outb(reg8, SR_DATA); } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/vt8623/northbridge.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -124,9 +124,6 @@ #if 0 /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */ - dev->on_mainboard=1; - dev->rom_address = (void *)0xfffc0000; - pci_dev_init(dev); call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); @@ -167,17 +164,8 @@ #endif } -static void vga_read_resources(device_t dev) -{ - - dev->rom_address = (void *)0xfffc0000; - dev->on_mainboard=1; - pci_dev_read_resources(dev); - -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/northbridge/via/vx800/vga.c =================================================================== --- trunk/src/northbridge/via/vx800/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/vx800/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -126,15 +126,8 @@ } -static void vga_read_resources(device_t dev) -{ - dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1); - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init, Modified: trunk/src/southbridge/nvidia/ck804/chip.h =================================================================== --- trunk/src/southbridge/nvidia/ck804/chip.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/southbridge/nvidia/ck804/chip.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -7,8 +7,6 @@ unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned long nic_rom_address; - unsigned long raid_rom_address; unsigned int mac_eeprom_smbus; unsigned int mac_eeprom_addr; }; Modified: trunk/src/southbridge/nvidia/ck804/ck804.c =================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/southbridge/nvidia/ck804/ck804.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -77,12 +77,10 @@ case PCI_DEVICE_ID_NVIDIA_CK804_NIC: devfn -= (9 << 3); index = 10; - dev->rom_address = conf->nic_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: devfn -= (9 << 3); index = 10; - dev->rom_address = conf->nic_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_ACI: devfn -= (3 << 3); @@ -95,7 +93,6 @@ case PCI_DEVICE_ID_NVIDIA_CK804_IDE: devfn -= (5 << 3); index = 14; - dev->rom_address = conf->raid_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: devfn -= (6 << 3); -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

4 30

[PATCH 13/13] Fix PkgLength calculation for the SSDT.
by Magnus Christensson 25 Nov '09

25 Nov '09

Signed-off-by: Magnus Christensson <mch(a)virtutech.com> --- src/acpi.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/acpi.c b/src/acpi.c index 843af69..88007ae 100644 --- a/src/acpi.c +++ b/src/acpi.c @@ -464,10 +464,12 @@ build_ssdt(void) // build processor scope header *(ssdt_ptr++) = 0x10; // ScopeOp if (cpu_length <= 0x3e) { + /* Handle 1-4 CPUs with one byte encoding */ *(ssdt_ptr++) = cpu_length + 1; } else { - *(ssdt_ptr++) = 0x7F; - *(ssdt_ptr++) = (cpu_length + 2) >> 6; + /* Handle 5-314 CPUs with two byte encoding */ + *(ssdt_ptr++) = 0x40 | ((cpu_length + 1) & 0xf); + *(ssdt_ptr++) = (cpu_length + 1) >> 4; } *(ssdt_ptr++) = '_'; // Name *(ssdt_ptr++) = 'P'; -- 1.6.2.5 --------------010906020603050202070006--

1 0

[PATCH] Linux cannot bootable without old onboard pci driver on RS690 system.
by 유택연 25 Nov '09

25 Nov '09

Hi, Old the onboard pci driver is still seems to be needed as a dummy driver. On RS690 based system like dbm690t and pistachio, linux kernel is halted on scan PCI bus below 00:14:04 node. This patch is tested under linux kernel version 2.6.37.36. See attached patches. jaagar

2 1

device tree supermicro H8QME-2+
by Knut Kujat 25 Nov '09

25 Nov '09

Hello, I'm trying to port coreboot to the supermicro H8QME-2+ Board and right now I'm building the device tree. To be able to do so I use the device tree from the supermicro H8QMR board because they are quite similar. Now my question, even if I'm already modifying the device tree I'm not sure if I'm doing alright and would be really grateful if someone could take a peek and see if I'm at least on the right way?! Please find attached the H8QME-2+ block diagram and a "lspci -vxx" output. dir /southbridge/nvidia/mcp55 chip northbridge/amd/amdfam10/root_complex device apic_cluster 0 on chip cpu/amd/socket_F_1207 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # SB on link 2.0 chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end #The H8QME has only one serial. #device pnp 2e.3 on # Com2 # io 0x60 = 0x2f8 # irq 0x70 = 3 #end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end #SuperIO end #LPC device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end end chip drivers/generic/generic #dimm 2-0-0 device i2c 58 on end end chip drivers/generic/generic #dimm 2-0-1 device i2c 59 on end end chip drivers/generic/generic #dimm 2-1-0 device i2c 5a on end end chip drivers/generic/generic #dimm 2-1-1 device i2c 5b on end end chip drivers/generic/generic #dimm 3-0-0 device i2c 5c on end end chip drivers/generic/generic #dimm 3-0-1 device i2c 5d on end end chip drivers/generic/generic #dimm 3-1-0 device i2c 5e on end end chip drivers/generic/generic #dimm 3-1-1 device i2c 5f on end end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1 # device i2c 50 on end # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end # end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end # end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end # end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end # end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end # end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI device pci 6.0 on end end #Don't know exactly what an AZA device is but #the h8qme doesn't seems to has one #device pci 6.1 on end # AZA #device pci 8.0 on end # NIC #device pci 9.0 on end # NIC device pci a.0 on end # PCI E 5 # #device pci 0.0 on #nec pci-x #end #device pci 0.1 on #nec pci-x # device pci 4.0 on end #scsi # device pci 4.1 on end #scsi #end #end device pci b.0 on end # PCI E 4 device pci c.0 on end # PCI E 3 device pci d.0 on end # PCI E 2 device pci e.0 on end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 19.0 on chip southbridge/amd/amd8132 device pci 3.0 on end # NIC device pci 3.1 on end # NIC #device pci 4.0 on end #scsi #device pci 4.1 on end #scsi end #amd8132 end #device pci 19.0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end device pci 1a.0 on end device pci 1a.1 on end device pci 1a.2 on end device pci 1a.3 on end device pci 1a.4 on end device pci 1b.0 on end device pci 1b.1 on end device pci 1b.2 on end device pci 1b.3 on end device pci 1b.4 on end end # end # PCI domain # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io # end end #root_complex THX!! Knut Kujat [root@jp14 sbin]# lspci -vxx 00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a2) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Capabilities: [dc] HyperTransport: MSI Mapping 00: de 10 69 03 06 01 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00 00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0 00: de 10 64 03 0f 00 a0 00 a3 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 13 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: 66MHz, fast devsel, IRQ 5 I/O ports at cc00 [size=64] I/O ports at 2d00 [size=64] I/O ports at 2e00 [size=64] Capabilities: [44] Power Management version 2 00: de 10 68 03 01 00 b0 00 a3 00 05 0c 00 00 80 00 10: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 2d 00 00 01 2e 00 00 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 00 00 00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) (prog-if 10 [OHCI]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 22 Memory at dfebf000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 00: de 10 6c 03 07 00 b0 00 a1 10 03 0c 00 00 80 00 10: 00 f0 eb df 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 03 01 00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) (prog-if 20 [EHCI]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 23 Memory at dfebec00 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port Capabilities: [80] Power Management version 2 00: de 10 6d 03 06 00 b0 00 a2 20 03 0c 00 00 80 00 10: 00 ec eb df 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0 [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] I/O ports at ffa0 [size=16] Capabilities: [44] Power Management version 2 00: de 10 6e 03 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: a1 ff 00 00 00 00 00 00 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 21 I/O ports at c480 [size=8] I/O ports at c400 [size=4] I/O ports at c080 [size=8] I/O ports at c000 [size=4] I/O ports at bc00 [size=16] Memory at dfebd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 81 c4 00 00 01 c4 00 00 81 c0 00 00 01 c0 00 00 20: 01 bc 00 00 00 d0 eb df 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01 00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 20 I/O ports at b880 [size=8] I/O ports at b800 [size=4] I/O ports at b480 [size=8] I/O ports at b400 [size=4] I/O ports at b080 [size=16] Memory at dfebc000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 81 b8 00 00 01 b8 00 00 81 b4 00 00 01 b4 00 00 20: 81 b0 00 00 00 c0 eb df 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 00:05.2 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 23 I/O ports at b000 [size=8] I/O ports at ac00 [size=4] I/O ports at a880 [size=8] I/O ports at a800 [size=4] I/O ports at a480 [size=16] Memory at dfebb000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00: de 10 7f 03 07 00 b0 00 a3 85 01 01 00 00 80 00 10: 01 b0 00 00 01 ac 00 00 81 a8 00 00 01 a8 00 00 20: 81 a4 00 00 00 b0 eb df 00 00 00 00 d9 15 11 13 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 03 03 01 00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) (prog-if 01 [Subtractive decode]) Flags: bus master, 66MHz, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: dff00000-dfffffff Prefetchable memory behind bridge: d0000000-d7ffffff Capabilities: [b8] #0d [0000] Capabilities: [8c] HyperTransport: MSI Mapping 00: de 10 70 03 07 00 b0 00 a2 01 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 d0 d0 80 02 20: f0 df f0 df 00 d0 f0 d7 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 0a 02 00:0a.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00: de 10 76 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0b.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00: de 10 74 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0c.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00: de 10 74 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0d.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00: de 10 78 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0e.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00: de 10 75 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a3) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 Capabilities: [40] #0d [0000] Capabilities: [48] Power Management version 2 Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/1 Enable+ Capabilities: [60] HyperTransport: MSI Mapping Capabilities: [80] Express Root Port (Slot+) IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [160] Advanced Error Reporting 00: de 10 77 03 04 04 10 00 a3 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 07 07 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration Flags: fast devsel Capabilities: [80] HyperTransport: Host or Secondary Interface Capabilities: [a0] HyperTransport: Host or Secondary Interface Capabilities: [c0] HyperTransport: Host or Secondary Interface 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map Flags: fast devsel 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller Flags: fast devsel 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control Flags: fast devsel Capabilities: [f0] #0f [0010] 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control Flags: fast devsel 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration Flags: fast devsel Capabilities: [80] HyperTransport: Host or Secondary Interface Capabilities: [a0] HyperTransport: Host or Secondary Interface Capabilities: [c0] HyperTransport: Host or Secondary Interface 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:19.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map Flags: fast devsel 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller Flags: fast devsel 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control Flags: fast devsel Capabilities: [f0] #0f [0010] 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:19.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control Flags: fast devsel 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1a.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration Flags: fast devsel Capabilities: [80] HyperTransport: Host or Secondary Interface Capabilities: [a0] HyperTransport: Host or Secondary Interface Capabilities: [c0] HyperTransport: Host or Secondary Interface 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:1a.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map Flags: fast devsel 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1a.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller Flags: fast devsel 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1a.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control Flags: fast devsel Capabilities: [f0] #0f [0010] 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:1a.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control Flags: fast devsel 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1b.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration Flags: fast devsel Capabilities: [80] HyperTransport: Host or Secondary Interface Capabilities: [a0] HyperTransport: Host or Secondary Interface Capabilities: [c0] HyperTransport: Host or Secondary Interface 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00:1b.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map Flags: fast devsel 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1b.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller Flags: fast devsel 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:1b.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control Flags: fast devsel Capabilities: [f0] #0f [0010] 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:1b.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control Flags: fast devsel 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:01.0 VGA compatible controller: ATI Technologies Inc ES1000 (rev 02) (prog-if 00 [VGA controller]) Subsystem: Super Micro Computer Inc Unknown device 1311 Flags: bus master, stepping, medium devsel, latency 64, IRQ 10 Memory at d0000000 (32-bit, prefetchable) [size=128M] I/O ports at d000 [size=256] Memory at dfff0000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at dff00000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 00: 02 10 5e 51 87 00 90 02 02 00 00 03 10 40 00 00 10: 08 00 00 d0 01 d0 00 00 00 00 ff df 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 d9 15 11 13 30: 00 00 fc df 50 00 00 00 00 00 00 00 0a 01 08 00 08:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8132 PCI-X Bridge (rev 12) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 64 Bus: primary=08, secondary=09, subordinate=09, sec-latency=64 Capabilities: [60] PCI-X bridge device Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration Capabilities: [c0] HyperTransport: Slave or Primary Interface Capabilities: [f4] HyperTransport: MSI Mapping 00: 22 10 58 74 14 01 10 08 12 00 04 06 10 40 81 00 10: 00 00 00 00 00 00 00 00 08 09 09 40 f1 01 20 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 60 00 00 00 00 00 00 00 ff 00 07 00 08:01.1 PIC: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC (rev 12) (prog-if 10 [IO-APIC]) Subsystem: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC Flags: bus master, medium devsel, latency 0 Memory at cfeff000 (64-bit, non-prefetchable) [size=4K] 00: 22 10 59 74 06 00 00 02 12 10 00 08 00 00 00 00 10: 04 f0 ef cf 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 59 74 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 08:02.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8132 PCI-X Bridge (rev 12) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 64 Bus: primary=08, secondary=0a, subordinate=0a, sec-latency=64 I/O behind bridge: 0000e000-0000efff Memory behind bridge: cff00000-cfffffff Capabilities: [60] PCI-X bridge device Capabilities: [b8] HyperTransport: Interrupt Discovery and Configuration Capabilities: [c0] HyperTransport: Revision ID: 2.00 Capabilities: [f4] HyperTransport: MSI Mapping 00: 22 10 58 74 17 01 10 08 12 00 04 06 10 40 81 00 10: 00 00 00 00 00 00 00 00 08 0a 0a 40 e1 e1 20 02 20: f0 cf f0 cf f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 60 00 00 00 00 00 00 00 ff 00 07 00 08:02.1 PIC: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC (rev 12) (prog-if 10 [IO-APIC]) Subsystem: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC Flags: bus master, medium devsel, latency 0 Memory at cfefe000 (64-bit, non-prefetchable) [size=4K] 00: 22 10 59 74 06 00 00 02 12 10 00 08 00 00 00 00 10: 04 e0 ef cf 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 59 74 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 0a:03.0 Ethernet controller: Intel Corporation 82546GB Gigabit Ethernet Controller (rev 03) Subsystem: Super Micro Computer Inc Unknown device 117a Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 47 Memory at cffe0000 (64-bit, non-prefetchable) [size=128K] I/O ports at ec00 [size=64] Capabilities: [dc] Power Management version 2 Capabilities: [e4] PCI-X non-bridge device Capabilities: [f0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- 00: 86 80 79 10 17 01 30 02 03 00 00 02 10 40 80 00 10: 04 00 fe cf 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 ec 00 00 00 00 00 00 00 00 00 00 d9 15 7a 11 30: 00 00 00 00 dc 00 00 00 00 00 00 00 05 01 ff 00 0a:03.1 Ethernet controller: Intel Corporation 82546GB Gigabit Ethernet Controller (rev 03) Subsystem: Super Micro Computer Inc Unknown device 117a Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 48 Memory at cffa0000 (64-bit, non-prefetchable) [size=128K] I/O ports at e880 [size=64] Capabilities: [dc] Power Management version 2 Capabilities: [e4] PCI-X non-bridge device Capabilities: [f0] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- 00: 86 80 79 10 17 01 30 02 03 00 00 02 10 40 80 00 10: 04 00 fa cf 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 e8 00 00 00 00 00 00 00 00 00 00 d9 15 7a 11 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0b 02 ff 00 dir /southbridge/nvidia/mcp55 chip northbridge/amd/amdfam10/root_complex device apic_cluster 0 on chip cpu/amd/socket_F_1207 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # SB on link 2.0 chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end #The H8QME has only one serial. #device pnp 2e.3 on # Com2 # io 0x60 = 0x2f8 # irq 0x70 = 3 #end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end #SuperIO end #LPC device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end end chip drivers/generic/generic #dimm 2-0-0 device i2c 58 on end end chip drivers/generic/generic #dimm 2-0-1 device i2c 59 on end end chip drivers/generic/generic #dimm 2-1-0 device i2c 5a on end end chip drivers/generic/generic #dimm 2-1-1 device i2c 5b on end end chip drivers/generic/generic #dimm 3-0-0 device i2c 5c on end end chip drivers/generic/generic #dimm 3-0-1 device i2c 5d on end end chip drivers/generic/generic #dimm 3-1-0 device i2c 5e on end end chip drivers/generic/generic #dimm 3-1-1 device i2c 5f on end end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? # chip drivers/generic/generic #PCIXA Slot1 # device i2c 50 on end # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end # end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end # end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end # end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end # end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end # end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI device pci 6.0 on end end #Don't know exactly what an AZA device is but #the h8qme doesn't seems to has one #device pci 6.1 on end # AZA #device pci 8.0 on end # NIC #device pci 9.0 on end # NIC device pci a.0 on end # PCI E 5 # #device pci 0.0 on #nec pci-x #end #device pci 0.1 on #nec pci-x # device pci 4.0 on end #scsi # device pci 4.1 on end #scsi #end #end device pci b.0 on end # PCI E 4 device pci c.0 on end # PCI E 3 device pci d.0 on end # PCI E 2 device pci e.0 on end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 19.0 on chip southbridge/amd/amd8132 device pci 3.0 on end # NIC device pci 3.1 on end # NIC #device pci 4.0 on end #scsi #device pci 4.1 on end #scsi end #amd8132 end #device pci 19.0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end device pci 1a.0 on end device pci 1a.1 on end device pci 1a.2 on end device pci 1a.3 on end device pci 1a.4 on end device pci 1b.0 on end device pci 1b.1 on end device pci 1b.2 on end device pci 1b.3 on end device pci 1b.4 on end end # end # PCI domain # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io # end end #root_complex

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build service results for r4955
by coreboot information 25 Nov '09

25 Nov '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "zbao" checked in revision 4955 to the coreboot repository. This caused the following changes: Change Log: This patch is buzzer of TechNexion TIM-5690. I forgot to svn add the speaker.c and speaker.h. Signed-off-by: Libra Li <libra.li(a)technexion.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Build Log: Compilation of technexion:tim5690 has been fixed If something broke during this checkin please be a pain in zbao's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r4956 - trunk/src/mainboard/technexion/tim5690
by svn＠coreboot.org 25 Nov '09

25 Nov '09

Author: stuge Date: 2009-11-25 09:35:59 +0100 (Wed, 25 Nov 2009) New Revision: 4956 Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c trunk/src/mainboard/technexion/tim5690/speaker.c Log: Trivial style changes, replace a few C++ type comments, and some code reuse Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-11-25 08:14:04 UTC (rev 4955) +++ trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-11-25 08:35:59 UTC (rev 4956) @@ -28,7 +28,6 @@ #include <../southbridge/amd/sb600/sb600.h> #include "chip.h" #include "tn_post_code.h" -//#include "speaker.h" // test buzzer #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ @@ -185,12 +184,6 @@ uma_memory_base, uma_memory_size); #endif technexion_post_code(LED_MESSAGE_FINISH); - // test buzzer - //speaker_on_delay(); - //speaker_off_delay(); - //speaker_on_delay(); - //speaker_off_nodelay(); - } struct chip_operations mainboard_ops = { Modified: trunk/src/mainboard/technexion/tim5690/speaker.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/speaker.c 2009-11-25 08:14:04 UTC (rev 4955) +++ trunk/src/mainboard/technexion/tim5690/speaker.c 2009-11-25 08:35:59 UTC (rev 4956) @@ -32,7 +32,7 @@ #include <../southbridge/amd/sb600/sb600.h> #include <delay.h> -#endif // __PRE_RAM__ +#endif /* __PRE_RAM__ */ #include "speaker.h" @@ -41,11 +41,11 @@ * Options_0 - RW - 8 bits - [PM_Reg: 60h]. * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. */ -#ifndef __PRE_RAM__ - pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); -#else +#ifdef __PRE_RAM__ pmio_write(0x60, (pmio_read(0x60) | (1<<5))); -#endif // __PRE_RAM__ +#else + pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); +#endif /* __PRE_RAM__ */ /* SB600 RRG. * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h]. @@ -72,12 +72,7 @@ } void speaker_on_delay(void) { - /* SB600 RRG. - * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. - * SpkrEnable, bit[0]=1b, Enable counter 2 - * SpkrTmrEnable, bit[1]=1b, Speaker timer on - */ - outb(inb(0x61) | 0x03, 0x61); + speaker_on_nodelay(); mdelay(100); } @@ -91,12 +86,6 @@ } void speaker_off_delay(void) { - /* SB600 RRG. - * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. - * SpkrEnable, bit[0]=0b, Disable counter 2 - * SpkrTmrEnable, bit[1]=0b, Speaker timer off - */ - outb(inb(0x61) & ~0x03, 0x61); + speaker_off_nodelay(); mdelay(100); } -

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Re: [coreboot] [commit] r4954 - trunk/src/mainboard/technexion/tim5690
by Libra Li 25 Nov '09

25 Nov '09

Hi, Zheng, This version is loss speaker.c and speaker.h. Thanks. Signed-off-by: Libra Li <libra.li(a)technexion.com> 2009/11/25 <svn(a)coreboot.org> > Author: zbao > Date: 2009-11-25 08:48:24 +0100 (Wed, 25 Nov 2009) > New Revision: 4954 > > Modified: > trunk/src/mainboard/technexion/tim5690/Config.lb > trunk/src/mainboard/technexion/tim5690/Makefile.inc > trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c > trunk/src/mainboard/technexion/tim5690/mainboard.c > trunk/src/mainboard/technexion/tim5690/tn_post_code.c > trunk/src/mainboard/technexion/tim5690/tn_post_code.h > Log: > This patch is buzzer of TechNexion TIM-5690. > > Change EARLY_STAGE into __PRE_RAM__. > > Signed-off-by: Libra Li <libra.li(a)technexion.com> > Acked-by: Zheng Bao <zheng.bao(a)amd.com> > > > Modified: trunk/src/mainboard/technexion/tim5690/Config.lb > =================================================================== > --- trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-25 02:25:37 > UTC (rev 4953) > +++ trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-25 07:48:24 > UTC (rev 4954) > @@ -31,6 +31,7 @@ > > driver mainboard.o > object tn_post_code.o > +object speaker.o > > #dir /drivers/si/3114 > > > Modified: trunk/src/mainboard/technexion/tim5690/Makefile.inc > =================================================================== > --- trunk/src/mainboard/technexion/tim5690/Makefile.inc 2009-11-25 02:25:37 > UTC (rev 4953) > +++ trunk/src/mainboard/technexion/tim5690/Makefile.inc 2009-11-25 07:48:24 > UTC (rev 4954) > @@ -32,6 +32,8 @@ > # This is debug message for products of Technexion. > obj-y += tn_post_code.o > > +obj-y += speaker.o > + > # This is part of the conversion to init-obj and away from included code. > > initobj-y += crt0.o > > Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c > =================================================================== > --- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-25 > 02:25:37 UTC (rev 4953) > +++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-25 > 07:48:24 UTC (rev 4954) > @@ -100,8 +100,8 @@ > > #include "cpu/amd/model_fxx/fidvid.c" > > -#define TECHNEXION_EARLY_SETUP > #include "tn_post_code.c" > +#include "speaker.c" > > > #if CONFIG_USE_FALLBACK_IMAGE == 1 > @@ -249,6 +249,9 @@ > soft_reset(); > } > > + speaker_init(255); > + speaker_on_nodelay(); > + > allow_all_aps_stop(bsp_apicid); > > /* It's the time to set ctrl now; */ > @@ -261,6 +264,8 @@ > > sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); > > + speaker_off_nodelay(); > + > rs690_before_pci_init(); > sb600_before_pci_init(); > > > Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c > =================================================================== > --- trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-11-25 02:25:37 > UTC (rev 4953) > +++ trunk/src/mainboard/technexion/tim5690/mainboard.c 2009-11-25 07:48:24 > UTC (rev 4954) > @@ -28,6 +28,7 @@ > #include <../southbridge/amd/sb600/sb600.h> > #include "chip.h" > #include "tn_post_code.h" > +//#include "speaker.h" // test buzzer > > #define ADT7461_ADDRESS 0x4C > #define ARA_ADDRESS 0x0C /* Alert Response Address */ > @@ -184,6 +185,12 @@ > uma_memory_base, uma_memory_size); > #endif > technexion_post_code(LED_MESSAGE_FINISH); > + // test buzzer > + //speaker_on_delay(); > + //speaker_off_delay(); > + //speaker_on_delay(); > + //speaker_off_nodelay(); > + > } > > struct chip_operations mainboard_ops = { > > Modified: trunk/src/mainboard/technexion/tim5690/tn_post_code.c > =================================================================== > --- trunk/src/mainboard/technexion/tim5690/tn_post_code.c 2009-11-25 > 02:25:37 UTC (rev 4953) > +++ trunk/src/mainboard/technexion/tim5690/tn_post_code.c 2009-11-25 > 07:48:24 UTC (rev 4954) > @@ -1,6 +1,26 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > > -#ifdef TECHNEXION_EARLY_SETUP > > +#ifdef __PRE_RAM__ > + > #include <arch/cpu.h> > #include "southbridge/amd/sb600/sb600.h" > > @@ -14,7 +34,7 @@ > #include "tn_post_code.h" > > > -#ifdef TECHNEXION_EARLY_SETUP > +#ifdef __PRE_RAM__ > > // TechNexion's Post Code Initially. > void technexion_post_code_init(void) > @@ -116,7 +136,7 @@ > device_t dev=0; > > // SMBus Module and ACPI Block (Device 20, Function 0) > -#ifdef TECHNEXION_EARLY_SETUP > +#ifdef __PRE_RAM__ > dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, > PCI_DEVICE_ID_ATI_SB600_SM), 0); > #else > dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0); > > Modified: trunk/src/mainboard/technexion/tim5690/tn_post_code.h > =================================================================== > --- trunk/src/mainboard/technexion/tim5690/tn_post_code.h 2009-11-25 > 02:25:37 UTC (rev 4953) > +++ trunk/src/mainboard/technexion/tim5690/tn_post_code.h 2009-11-25 > 07:48:24 UTC (rev 4954) > @@ -1,11 +1,29 @@ > +/* > + * This file is part of the coreboot project. > + * > + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 > USA > + */ > > - > #define LED_MESSAGE_START 0xFF > #define LED_MESSAGE_FINISH 0x99 > #define LED_MESSAGE_RAM 0x01 > > > -#ifdef TECHNEXION_EARLY_SETUP > +#ifdef __PRE_RAM__ > > // TechNexion's Post Code Initially. > void technexion_post_code_init(void); > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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[commit] r4955 - trunk/src/mainboard/technexion/tim5690
by svn＠coreboot.org 25 Nov '09

25 Nov '09

Author: zbao Date: 2009-11-25 09:14:04 +0100 (Wed, 25 Nov 2009) New Revision: 4955 Added: trunk/src/mainboard/technexion/tim5690/speaker.c trunk/src/mainboard/technexion/tim5690/speaker.h Log: This patch is buzzer of TechNexion TIM-5690. I forgot to svn add the speaker.c and speaker.h. Signed-off-by: Libra Li <libra.li(a)technexion.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Added: trunk/src/mainboard/technexion/tim5690/speaker.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/speaker.c (rev 0) +++ trunk/src/mainboard/technexion/tim5690/speaker.c 2009-11-25 08:14:04 UTC (rev 4955) @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifdef __PRE_RAM__ + +#include <arch/cpu.h> +#include "southbridge/amd/sb600/sb600.h" + +#else + +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <../southbridge/amd/sb600/sb600.h> +#include <delay.h> + +#endif // __PRE_RAM__ + +#include "speaker.h" + +void speaker_init(uint8_t time) { + /* SB600 RRG. + * Options_0 - RW - 8 bits - [PM_Reg: 60h]. + * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. + */ +#ifndef __PRE_RAM__ + pm_iowrite(0x60, (pm_ioread(0x60) | (1<<5))); +#else + pmio_write(0x60, (pmio_read(0x60) | (1<<5))); +#endif // __PRE_RAM__ + + /* SB600 RRG. + * Tmr1CntrlWord - RW - 8 bits - [IO_Reg: 43h]. + * ModeSelect, bit[3:1]=011b, Square wave output. + * CmmandSelect, bit[5:4]=11b, Read/write least, and then most significant byte. + * CounterSelect, bit[7:6]=10b, Select counter 2. + */ + outb(0xb6, 0x43); + + + /* SB600 RRG. + * TimerCh2- RW - 8 bits - [IO_Reg: 42h]. + */ + outb(time, 0x42); +} + +void speaker_on_nodelay(void) { + /* SB600 RRG. + * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. + * SpkrEnable, bit[0]=1b, Enable counter 2 + * SpkrTmrEnable, bit[1]=1b, Speaker timer on + */ + outb(inb(0x61) | 0x03, 0x61); +} + +void speaker_on_delay(void) { + /* SB600 RRG. + * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. + * SpkrEnable, bit[0]=1b, Enable counter 2 + * SpkrTmrEnable, bit[1]=1b, Speaker timer on + */ + outb(inb(0x61) | 0x03, 0x61); + mdelay(100); +} + +void speaker_off_nodelay(void) { + /* SB600 RRG. + * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. + * SpkrEnable, bit[0]=0b, Disable counter 2 + * SpkrTmrEnable, bit[1]=0b, Speaker timer off + */ + outb(inb(0x61) & ~0x03, 0x61); +} + +void speaker_off_delay(void) { + /* SB600 RRG. + * Nmi_Status - RW - 8 bits - [IO_Reg: 61h]. + * SpkrEnable, bit[0]=0b, Disable counter 2 + * SpkrTmrEnable, bit[1]=0b, Speaker timer off + */ + outb(inb(0x61) & ~0x03, 0x61); + mdelay(100); +} + Added: trunk/src/mainboard/technexion/tim5690/speaker.h =================================================================== --- trunk/src/mainboard/technexion/tim5690/speaker.h (rev 0) +++ trunk/src/mainboard/technexion/tim5690/speaker.h 2009-11-25 08:14:04 UTC (rev 4955) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void speaker_init(uint8_t time); +void speaker_on_nodelay(void); +void speaker_off_nodelay(void); +void speaker_on_delay(void); +void speaker_off_delay(void);

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coreboot November 2009