R4925 makes my linux hang. Output is attached. My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700). But dbm690t works well. I don't know why.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of svn@coreboot.org Sent: Saturday, November 07, 2009 7:42 AM To: coreboot@coreboot.org Subject: [coreboot] [v2] r4925 - in trunk/src: devices driversinclude/device mainboard/amd/dbm690t mainboard/amd/pistachiomainboard/arima/hdama mainboard/artecgroup/dbe61/realmodemainboard/asi/mb_5blmp mainboard/asus/mew-vmmainboard/broadcom/blast mainboard/digita
Author: myles Date: 2009-11-06 23:42:26 +0000 (Fri, 06 Nov 2009) New Revision: 4925
Removed: trunk/src/drivers/pci/ Modified: trunk/src/devices/pci_device.c trunk/src/devices/pci_rom.c trunk/src/drivers/Makefile.inc trunk/src/include/device/device.h trunk/src/mainboard/amd/dbm690t/Config.lb trunk/src/mainboard/amd/dbm690t/devicetree.cb trunk/src/mainboard/amd/pistachio/Config.lb trunk/src/mainboard/amd/pistachio/devicetree.cb trunk/src/mainboard/arima/hdama/Config.lb trunk/src/mainboard/arima/hdama/devicetree.cb trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c trunk/src/mainboard/asi/mb_5blmp/Config.lb trunk/src/mainboard/asi/mb_5blmp/devicetree.cb trunk/src/mainboard/asus/mew-vm/Config.lb trunk/src/mainboard/asus/mew-vm/devicetree.cb trunk/src/mainboard/broadcom/blast/Config.lb trunk/src/mainboard/broadcom/blast/devicetree.cb trunk/src/mainboard/digitallogic/msm586seg/Config.lb trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb trunk/src/mainboard/emulation/qemu-x86/mainboard.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb trunk/src/mainboard/hp/dl145_g3/Config.lb trunk/src/mainboard/hp/dl145_g3/devicetree.cb trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb trunk/src/mainboard/ibm/e326/Config.lb trunk/src/mainboard/ibm/e326/devicetree.cb trunk/src/mainboard/intel/d945gclf/Config.lb trunk/src/mainboard/intel/d945gclf/devicetree.cb trunk/src/mainboard/intel/xe7501devkit/Config.lb trunk/src/mainboard/intel/xe7501devkit/devicetree.cb trunk/src/mainboard/iwill/dk8_htx/Config.lb trunk/src/mainboard/iwill/dk8_htx/devicetree.cb trunk/src/mainboard/kontron/986lcd-m/Config.lb trunk/src/mainboard/kontron/986lcd-m/devicetree.cb trunk/src/mainboard/kontron/kt690/Config.lb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/mitac/6513wu/Config.lb trunk/src/mainboard/mitac/6513wu/devicetree.cb trunk/src/mainboard/msi/ms6178/Config.lb trunk/src/mainboard/msi/ms6178/devicetree.cb trunk/src/mainboard/msi/ms9185/Config.lb trunk/src/mainboard/msi/ms9185/devicetree.cb trunk/src/mainboard/msi/ms9282/Config.lb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/nec/powermate2000/Config.lb trunk/src/mainboard/nec/powermate2000/devicetree.cb trunk/src/mainboard/newisys/khepri/Config.lb trunk/src/mainboard/rca/rm4100/Config.lb trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/sunw/ultra40/Config.lb trunk/src/mainboard/sunw/ultra40/devicetree.cb trunk/src/mainboard/supermicro/h8dme/Config.lb trunk/src/mainboard/supermicro/h8dme/devicetree.cb trunk/src/mainboard/supermicro/h8dmr/Config.lb trunk/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/technexion/tim5690/Config.lb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/Config.lb trunk/src/mainboard/technexion/tim8690/devicetree.cb trunk/src/mainboard/technologic/ts5300/Config.lb trunk/src/mainboard/technologic/ts5300/devicetree.cb trunk/src/mainboard/thomson/ip1000/Config.lb trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/tyan/s2735/Config.lb trunk/src/mainboard/tyan/s2735/devicetree.cb trunk/src/mainboard/tyan/s2850/Config.lb trunk/src/mainboard/tyan/s2850/devicetree.cb trunk/src/mainboard/tyan/s2875/Config.lb trunk/src/mainboard/tyan/s2875/devicetree.cb trunk/src/mainboard/tyan/s2880/Config.lb trunk/src/mainboard/tyan/s2880/devicetree.cb trunk/src/mainboard/tyan/s2881/Config.lb trunk/src/mainboard/tyan/s2881/devicetree.cb trunk/src/mainboard/tyan/s2882/Config.lb trunk/src/mainboard/tyan/s2882/devicetree.cb trunk/src/mainboard/tyan/s2885/Config.lb trunk/src/mainboard/tyan/s2885/devicetree.cb trunk/src/mainboard/tyan/s2891/devicetree.cb trunk/src/mainboard/tyan/s2892/devicetree.cb trunk/src/mainboard/tyan/s2895/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/Config.lb trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb trunk/src/mainboard/tyan/s4880/Config.lb trunk/src/mainboard/tyan/s4880/devicetree.cb trunk/src/mainboard/tyan/s4882/Config.lb trunk/src/mainboard/tyan/s4882/devicetree.cb trunk/src/mainboard/via/epia/Config.lb trunk/src/mainboard/via/epia/devicetree.cb trunk/src/mainboard/via/vt8454c/Config.lb trunk/src/mainboard/via/vt8454c/devicetree.cb trunk/src/northbridge/via/cn400/vga.c trunk/src/northbridge/via/cn700/vga.c trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vx800/vga.c trunk/src/southbridge/nvidia/ck804/chip.h trunk/src/southbridge/nvidia/ck804/ck804.c Log: Remove drivers/pci/onboard. The only purpose was for option ROMs, which are now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Stefan Reinauer stepan@coresystems.de
Modified: trunk/src/devices/pci_device.c =================================================================== --- trunk/src/devices/pci_device.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/devices/pci_device.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -285,11 +285,6 @@ unsigned long value; resource_t moving;
- if ((dev->on_mainboard) && (dev->rom_address == 0)) { - /* Skip it if rom_address is not set in the MB Config.lb. */ - return; - } - /* Initialize the resources to nothing. */ resource = new_resource(dev, index);
@@ -326,18 +321,6 @@ } resource->flags = 0; } - - /* For on board device with embedded ROM image, the ROM image is at - * fixed address specified in the Config.lb, the dev->rom_address is - * inited by driver_pci_onboard_ops::enable_dev() */ - if ((dev->on_mainboard) && (dev->rom_address != 0)) { - resource->base = dev->rom_address; - /* The resource allocator needs the size to be non-zero. */ - resource->size = 0x100; - resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - } - compact_resources(dev); }
Modified: trunk/src/devices/pci_rom.c =================================================================== --- trunk/src/devices/pci_rom.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/devices/pci_rom.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -31,42 +31,37 @@
struct rom_header * pci_rom_probe(struct device *dev) { - unsigned long rom_address = 0; struct rom_header *rom_header; struct pci_data *rom_data;
- void *v; - /* if it's in FLASH, then it's as if dev->on_mainboard was true */ - v = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - printk_debug("In cbfs, rom address for %s = %p\n", - dev_path(dev), v); - if (v) { - dev->rom_address = (u32)v; - dev->on_mainboard = 1; - } + /* If it's in FLASH, then don't check device for ROM. */ + rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
- if (dev->on_mainboard) { - // in case some device PCI_ROM_ADDRESS can not be set or readonly - rom_address = dev->rom_address; - printk_debug("On mainboard, rom address for %s = %lx\n",
- dev_path(dev), rom_address); + if (rom_header) { + printk_debug("In cbfs, rom address for %s = %p\n", + dev_path(dev), rom_header); } else { + unsigned long rom_address; + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); - printk_debug("On card, rom address for %s = %lx\n", - dev_path(dev), rom_address); - }
- if (rom_address == 0x00000000 || rom_address == 0xffffffff) { - return NULL; - } + if (rom_address == 0x00000000 || rom_address == 0xffffffff) { + #if CONFIG_BOARD_EMULATION_QEMU_X86 + rom_address = 0xc0000; + #else + return NULL; + #endif + } else { + /* enable expansion ROM address decoding */ + pci_write_config32(dev, PCI_ROM_ADDRESS, + rom_address|PCI_ROM_ADDRESS_ENABLE); + }
- if(!dev->on_mainboard) { - /* enable expansion ROM address decoding */ - pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); + printk_debug("On card, rom address for %s = %lx\n", + dev_path(dev), rom_address); + rom_header = (struct rom_header *)rom_address; }
- rom_header = (struct rom_header *)rom_address; printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n", le32_to_cpu(rom_header->signature), rom_header->size * 512, le32_to_cpu(rom_header->data)); @@ -76,11 +71,12 @@ return NULL; }
- rom_data = (struct pci_data *) ((void *)rom_header + le32_to_cpu(rom_header->data)); + rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data)); + printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) { - printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", + printk_err("ID mismatch: Vendor ID %04x, Device ID %04x\n", rom_data->vendor, rom_data->device); return NULL; } @@ -90,7 +86,8 @@ rom_data->type); if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { printk_debug("Class Code mismatch ROM %08x, dev %08x\n",
- (rom_data->class_hi << 8) | rom_data->class_lo, dev->class); + (rom_data->class_hi << 8) | rom_data->class_lo, + dev->class); //return NULL; }
Modified: trunk/src/drivers/Makefile.inc =================================================================== --- trunk/src/drivers/Makefile.inc 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/drivers/Makefile.inc 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,3 +1,2 @@ -subdirs-y += pci subdirs-y += generic/debug subdirs-y += ati/ragexl
Modified: trunk/src/include/device/device.h =================================================================== --- trunk/src/include/device/device.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/include/device/device.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -70,7 +70,6 @@ unsigned int enabled : 1; /* set if we should enable the device */ unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int on_mainboard : 1; - unsigned long rom_address;
u8 command;
Modified: trunk/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/dbm690t/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/dbm690t/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/pistachio/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -156,9 +156,7 @@ device pci 0.0 on end # HT 0x7910 # device pci 0.1 off end # CLK device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/amd/pistachio/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.0 on end # HT 0x7910 # device pci 0.1 off end # CLK device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/arima/hdama/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -177,9 +177,7 @@ device pci 0.1 on end # USB1 device pci 0.2 off end # USB 2.0 device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - end + device pci 6.0 on end # ATI Rage XL ## PCI Slot 5 (correct?) #chip drivers/generic/generic # device pci 5.0 on
Modified: trunk/src/mainboard/arima/hdama/devicetree.cb =================================================================== --- trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/arima/hdama/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -73,9 +73,7 @@ device pci 0.1 on end # USB1 device pci 0.2 off end # USB 2.0 device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - end + device pci 6.0 on end # ATI Rage XL ## PCI Slot 5 (correct?) #chip drivers/generic/generic # device pci 5.0 on
Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h =================================================================== --- trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/artecgroup/dbe61/realmode/chip.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,10 +1,6 @@ #ifndef PCI_REALMODE_H #define PCI_REALMODE_H
-struct drivers_pci_realmode_config -{ - unsigned long rom_address; -}; //struct chip_operations; extern struct chip_operations drivers_pci_realmode_ops;
Modified: trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c =================================================================== --- trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/artecgroup/dbe61/realmode/vgabios.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -74,36 +74,6 @@ emulator to successfully run this bios. */
- - - -/* - Modified to be an universal driver for loading VGA ROMs. - Aug 2006, anti.sullin@artecdesign.ee, Artec Design - - USAGE: - define in your motherboard Config.lb file in device hierarchy - around the VGA pci device realmode chip and define its rom address. - Rom address is read from Config.lb, this rom is then copied to 0xC000 and then excecuted - - chip drivers/pci/realmode - device pci 1.1 on end # VGA - register "rom_address" = "0xfffc0000" # at the beginning of 256k - end - - then, chip enable is called at this list first traversal, and this sets - up device's init callback. Device init is called during last list traversal and - so, other hw should be already initialized to run vga bios successfully. -*/ - - - - - - - - - /* Declare a temporary global descriptor table - necessary because the Core part of the bios no longer sets up any 16 bit segments */ __asm__ ( @@ -918,8 +888,6 @@
// code to make vga init go through the emulator - as of yet this does not workfor the epia-m dev->on_mainboard=1; - dev->rom_address = (void *)cfg->rom_address; - pci_dev_init(dev);
// code to make vga init run in real mode - does work but against the current coreboot philosophy
Modified: trunk/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asi/mb_5blmp/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -135,11 +135,6 @@ device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/asi/mb_5blmp/devicetree.cb =================================================================== --- trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asi/mb_5blmp/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -37,11 +37,6 @@ device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asus/mew-vm/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -97,18 +97,14 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video - #chip drivers/pci/onboard # device pci 1.0 on end - #end end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
device pci 1e.0 on # PCI Bridge - #chip drivers/pci/onboard # device pci 1.0 on end - #end end device pci 1f.0 on # ISA/LPC? Bridge chip superio/smsc/lpc47b272
Modified: trunk/src/mainboard/asus/mew-vm/devicetree.cb =================================================================== --- trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/asus/mew-vm/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,18 +2,14 @@ device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 on # Onboard Video - #chip drivers/pci/onboard # device pci 1.0 on end - #end end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
device pci 1e.0 on # PCI Bridge - #chip drivers/pci/onboard # device pci 1.0 on end - #end end device pci 1f.0 on # ISA/LPC? Bridge chip superio/smsc/lpc47b272
Modified: trunk/src/mainboard/broadcom/blast/Config.lb =================================================================== --- trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/broadcom/blast/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -207,21 +207,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - end + device pci 4.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - - end # device pci 18.0
device pci 18.0 on end
Modified: trunk/src/mainboard/broadcom/blast/devicetree.cb =================================================================== --- trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/broadcom/blast/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -105,21 +105,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4 - end + device pci 4.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - - end # device pci 18.0
device pci 18.0 on end
Modified: trunk/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/digitallogic/msm586seg/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -102,13 +102,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - - chip drivers/pci/onboard - device pci 12.0 on end # enet - end - chip drivers/pci/onboard - device pci 14.0 on end # 69000 - end + device pci 12.0 on end # enet + device pci 14.0 on end # 69000 # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end
Modified: trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb =================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/digitallogic/msm586seg/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,13 +1,8 @@ chip cpu/amd/sc520 device pci_domain 0 on device pci 0.0 on end - - chip drivers/pci/onboard - device pci 12.0 on end # enet - end - chip drivers/pci/onboard - device pci 14.0 on end # 69000 - end + device pci 12.0 on end # enet + device pci 14.0 on end # 69000 # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end
Modified: trunk/src/mainboard/emulation/qemu-x86/mainboard.c =================================================================== --- trunk/src/mainboard/emulation/qemu-x86/mainboard.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/emulation/qemu-x86/mainboard.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -16,7 +16,6 @@ * force coreboot to use it. */ dev->on_mainboard = 1; - dev->rom_address = 0xc0000;
/* Now do the usual initialization */ pci_dev_init(dev);
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -178,9 +178,7 @@ chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - end end device pci 2.0 on # LPC chip superio/ite/it8716f
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -11,9 +11,7 @@ chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge - chip drivers/pci/onboard # Integrated VGA device pci 0.0 on end - end end device pci 2.0 on # LPC chip superio/ite/it8716f
Modified: trunk/src/mainboard/hp/dl145_g3/Config.lb =================================================================== --- trunk/src/mainboard/hp/dl145_g3/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/dl145_g3/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -195,15 +195,6 @@ device pci 2.1 on end # USB device pci 2.2 on end # USB device pci 3.0 on end # VGA - - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end end end device pci 18.0 on end
Modified: trunk/src/mainboard/hp/dl145_g3/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/dl145_g3/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/dl145_g3/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -72,15 +72,6 @@ device pci 2.1 on end # USB device pci 2.2 on end # USB device pci 3.0 on end # VGA - - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end end end device pci 18.0 on end
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/e_vectra_p2706t/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -76,9 +76,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb =================================================================== --- trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/hp/e_vectra_p2706t/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -7,9 +7,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/ibm/e326/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -125,9 +125,7 @@ device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # ATI Rage XL - end + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366
Modified: trunk/src/mainboard/ibm/e326/devicetree.cb =================================================================== --- trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/ibm/e326/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # ATI Rage XL - end + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366
Modified: trunk/src/mainboard/intel/d945gclf/Config.lb =================================================================== --- trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/d945gclf/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -150,9 +150,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
Modified: trunk/src/mainboard/intel/d945gclf/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/d945gclf/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -28,9 +28,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
Modified: trunk/src/mainboard/intel/xe7501devkit/Config.lb =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/xe7501devkit/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -127,9 +127,7 @@ device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) device pci 1e.0 on # Hub to PCI bridge - chip drivers/pci/onboard # VGA ROM - device pci 0.0 on end - end + device pci 0.0 on end end device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47b272
Modified: trunk/src/mainboard/intel/xe7501devkit/devicetree.cb =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/intel/xe7501devkit/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -25,9 +25,7 @@ device pci 1d.1 off end # USB (not populated) device pci 1d.2 off end # USB (not populated) device pci 1e.0 on # Hub to PCI bridge - chip drivers/pci/onboard # VGA ROM - device pci 0.0 on end - end + device pci 0.0 on end end device pci 1f.0 on # LPC bridge chip superio/smsc/lpc47b272
Modified: trunk/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/iwill/dk8_htx/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -232,9 +232,6 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/pci/onboard - # device pci 6.0 on end - #end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/iwill/dk8_htx/devicetree.cb =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/iwill/dk8_htx/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -24,9 +24,6 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/pci/onboard - # device pci 6.0 on end - #end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/kontron/986lcd-m/Config.lb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/986lcd-m/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -153,9 +153,7 @@ device pci 00.0 on end # host bridge # autodetect 0:1.0 because it might or might not be there. # device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
Modified: trunk/src/mainboard/kontron/986lcd-m/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/986lcd-m/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -9,9 +9,7 @@ device pci_domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port - chip drivers/pci/onboard - device pci 02.0 on end # vga controller - end + device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
Modified: trunk/src/mainboard/kontron/kt690/Config.lb =================================================================== --- trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/kt690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb =================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/mitac/6513wu/Config.lb =================================================================== --- trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/mitac/6513wu/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -80,9 +80,7 @@ end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05"
Modified: trunk/src/mainboard/mitac/6513wu/devicetree.cb =================================================================== --- trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/mitac/6513wu/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -26,9 +26,7 @@ end device pci_domain 0 on # PCI domain device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - chip drivers/pci/onboard - device pci 1.0 on end - end + device pci 1.0 on end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05"
Modified: trunk/src/mainboard/msi/ms6178/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms6178/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/msi/ms6178/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms6178/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -26,9 +26,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 1.0 on end - end + device pci 1.0 on end # Onboard VGA chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/msi/ms9185/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9185/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -207,29 +207,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - end - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end - + device pci 3.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end
Modified: trunk/src/mainboard/msi/ms9185/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9185/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -73,29 +73,8 @@ device pci 2.0 on end # USB 0x0223 device pci 2.1 on end # USB device pci 2.2 on end # USB - #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), - chip drivers/pci/onboard - device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address - # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3 - end - #bx_a013+ start - #chip drivers/pci/onboard #SATA2 - # device pci 5.0 on end - # device pci 5.1 on end - # device pci 5.2 on end - # device pci 5.3 on end - #end - #bx_a013+ end - + device pci 3.0 on end # it is in bcm5785_0 bus end - #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,) -# chip drivers/pci/onboard -# device pci 0.0 on end # fake, will be disabled -# end -# chip drivers/pci/onboard -# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed -# end - end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end
Modified: trunk/src/mainboard/msi/ms9282/Config.lb =================================================================== --- trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9282/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -278,27 +278,21 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on #P2P - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # P2P device pci 7.0 on end # reserve device pci 8.0 on end # MAC0 device pci 9.0 on end # MAC1 device pci a.0 on device pci 0.0 on - chip drivers/pci/onboard - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 end end # 0x376 device pci b.0 on end # PCI E 0x374 device pci c.0 on end device pci d.0 on #SAS - chip drivers/pci/onboard - device pci 0.0 on end - end + device pci 0.0 on end end # PCI E 1 0x378 device pci e.0 on end # PCI E 0 0x375 device pci f.0 on end #PCI E 0x377 pci_E slot
Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb =================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -137,27 +137,21 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on #P2P - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # P2P device pci 7.0 on end # reserve device pci 8.0 on end # MAC0 device pci 9.0 on end # MAC1 device pci a.0 on device pci 0.0 on - chip drivers/pci/onboard - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end + device pci 4.0 on end #pci_E lan1 + device pci 4.1 on end #pci_E lan2 end end # 0x376 device pci b.0 on end # PCI E 0x374 device pci c.0 on end device pci d.0 on #SAS - chip drivers/pci/onboard - device pci 0.0 on end - end + device pci 0.0 on end end # PCI E 1 0x378 device pci e.0 on end # PCI E 0 0x375 device pci f.0 on end #PCI E 0x377 pci_E slot
Modified: trunk/src/mainboard/nec/powermate2000/Config.lb =================================================================== --- trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/nec/powermate2000/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,11 +75,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # end - end + device pci 1.0 off end # Onboard video chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/nec/powermate2000/devicetree.cb =================================================================== --- trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/nec/powermate2000/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -6,11 +6,7 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # end - end + device pci 1.0 off end # Onboard video chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
Modified: trunk/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/src/mainboard/newisys/khepri/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/newisys/khepri/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -98,8 +98,6 @@
config chip.h
-# FIXME: ROM for onboard VGA - chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_940
Modified: trunk/src/mainboard/rca/rm4100/Config.lb =================================================================== --- trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/rca/rm4100/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06"
Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb =================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,9 +1,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06"
Modified: trunk/src/mainboard/sunw/ultra40/Config.lb =================================================================== --- trunk/src/mainboard/sunw/ultra40/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/sunw/ultra40/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -210,8 +210,6 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" -# register "nic_rom_address" = "0xfff80000" # 64k -# register "raid_rom_address" = "0xfff90000" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end @@ -243,7 +241,6 @@ device pci c.0 off end # PCI E 2 device pci d.0 off end # PCI E 1 device pci e.0 on end # PCI E 0 -# register "nic_rom_address" = "0xfff80000" # 64k register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end
Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb =================================================================== --- trunk/src/mainboard/sunw/ultra40/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/sunw/ultra40/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -106,8 +106,6 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" -# register "nic_rom_address" = "0xfff80000" # 64k -# register "raid_rom_address" = "0xfff90000" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end @@ -139,7 +137,6 @@ device pci c.0 off end # PCI E 2 device pci d.0 off end # PCI E 1 device pci e.0 on end # PCI E 0 -# register "nic_rom_address" = "0xfff80000" # 64k register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end
Modified: trunk/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dme/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -254,9 +254,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -92,9 +92,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -276,9 +276,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -112,9 +112,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -280,9 +280,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,9 +114,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/technexion/tim5690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim5690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/technexion/tim8690/Config.lb =================================================================== --- trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim8690/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -155,9 +155,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -20,9 +20,7 @@ chip southbridge/amd/rs690 device pci 0.0 on end # HT 0x7910 device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - end + device pci 5.0 on end # Internal Graphics 0x791F end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 3.0 off end # PCIE P2P bridge 0x791b
Modified: trunk/src/mainboard/technologic/ts5300/Config.lb =================================================================== --- trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technologic/ts5300/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -104,12 +104,6 @@ device pci_domain 0 on device pci 0.0 on end -# chip drivers/pci/onboard -# device pci 12.0 on end # enet -# end -# chip drivers/pci/onboard -# device pci 14.0 on end # 69000 -# end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end
Modified: trunk/src/mainboard/technologic/ts5300/devicetree.cb =================================================================== --- trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/technologic/ts5300/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,12 +2,6 @@ device pci_domain 0 on device pci 0.0 on end -# chip drivers/pci/onboard -# device pci 12.0 on end # enet -# end -# chip drivers/pci/onboard -# device pci 14.0 on end # 69000 -# end # register "com1" = "{1}" # register "com1" = "{1, 0, 0x3f8, 4}" end
Modified: trunk/src/mainboard/thomson/ip1000/Config.lb =================================================================== --- trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/thomson/ip1000/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -75,9 +75,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06"
Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb =================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -1,9 +1,7 @@ chip northbridge/intel/i82830 # Northbridge device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - chip drivers/pci/onboard # Onboard VGA - device pci 2.0 on end # VGA (Intel 82830 CGC) - end + device pci 2.0 on end # VGA (Intel 82830 CGC) chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06"
Modified: trunk/src/mainboard/tyan/s2735/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2735/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2735/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -100,10 +100,8 @@ chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan - device pci 1.1 on end - end + device pci 1.0 on end # intel lan + device pci 1.1 on end end device pci 1e.0 on end device pci 1f.0 on end @@ -117,12 +115,8 @@ device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan 10/100 - end - chip drivers/pci/onboard - device pci 2.0 on end # ati - end + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end device pci 1f.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2735/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2735/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2735/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -6,10 +6,8 @@ chip southbridge/intel/i82870 device pci 1c.0 on end device pci 1d.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan - device pci 1.1 on end - end + device pci 1.0 on end # intel lan + device pci 1.1 on end end device pci 1e.0 on end device pci 1f.0 on end @@ -23,12 +21,8 @@ device pci 1d.3 on end device pci 1d.7 on end device pci 1e.0 on - chip drivers/pci/onboard - device pci 1.0 on end # intel lan 10/100 - end - chip drivers/pci/onboard - device pci 2.0 on end # ati - end + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end device pci 1f.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2850/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2850/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -119,9 +119,7 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci b.0 on end - end + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2850/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2850/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -17,9 +17,7 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci b.0 on end - end + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2875/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2875/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -123,9 +123,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2875/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2875/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -21,9 +21,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2880/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -113,10 +113,8 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end #broadcom - device pci 9.1 on end - end + device pci 9.0 on end #broadcom + device pci 9.1 on end # chip drivers/lsi/53c1030 # device pci a.0 on end # device pci a.1 on end @@ -135,12 +133,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end #some sata - end - chip drivers/pci/onboard - device pci 6.0 on end #adti - end + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2880/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -11,10 +11,8 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end #broadcom - device pci 9.1 on end - end + device pci 9.0 on end #broadcom + device pci 9.1 on end # chip drivers/lsi/53c1030 # device pci a.0 on end # device pci a.1 on end @@ -33,12 +31,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end #some sata - end - chip drivers/pci/onboard - device pci 6.0 on end #adti - end + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2881/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2881/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -115,14 +115,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - chip drivers/pci/onboard - device pci a.0 on end # Adaptic - device pci a.1 on end - end + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -136,12 +132,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # SiI - end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 5.0 on end # SiI + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2881/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2881/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -13,14 +13,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - chip drivers/pci/onboard - device pci a.0 on end # Adaptic - device pci a.1 on end - end + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -34,12 +30,8 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end # SiI - end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 5.0 on end # SiI + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2882/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,14 +114,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 6.0 on end # adaptec - device pci 6.1 on end - end - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -135,16 +131,11 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end #intel 10/100 - end + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2882/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -12,14 +12,10 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 6.0 on end # adaptec - device pci 6.1 on end - end - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -33,16 +29,11 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 5.0 on end - end + device pci 5.0 on end # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end #intel 10/100 - end + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2885/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2885/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2885/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,9 +121,7 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5703 - end + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -137,9 +135,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci b.0 on end # SiI 3114 - end + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2885/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2885/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2885/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -19,9 +19,7 @@ chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5703 - end + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -35,9 +33,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci b.0 on end # SiI 3114 - end + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2891/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2891/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -104,9 +104,7 @@ device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 7.0 on end - end + device pci 7.0 on end end device pci a.0 off end # NIC device pci b.0 off end # PCI E 3 @@ -127,10 +125,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 1.1 on end end
Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2892/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2892/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -105,12 +105,9 @@ device pci 8.0 on end # SATA 0 device pci 9.0 on # PCI # chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 8.0 on end - end + device pci 6.0 on end + # end + device pci 8.0 on end end device pci a.0 off end # NIC device pci b.0 off end # PCI E 3 @@ -131,10 +128,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 1.1 on end end
Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2895/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2895/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -111,10 +111,8 @@ device pci 0.0 on end device pci 0.1 on end device pci 1.0 on - chip drivers/pci/onboard - device pci 6.0 on end # lsi scsi - device pci 6.1 on end - end + device pci 6.0 on end # lsi scsi + device pci 6.1 on end end device pci 1.1 on end end
Modified: trunk/src/mainboard/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2912_fam10/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -279,9 +279,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -112,9 +112,7 @@ device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on - chip drivers/pci/onboard - device pci 4.0 on end - end + device pci 4.0 on end end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC
Modified: trunk/src/mainboard/tyan/s4880/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4880/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -116,10 +116,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -133,9 +131,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s4880/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4880/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -19,10 +19,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end - device pci 9.1 on end - end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -36,9 +34,7 @@ device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - chip drivers/pci/onboard - device pci 6.0 on end - end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s4882/Config.lb =================================================================== --- trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4882/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -114,10 +114,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -132,12 +130,9 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 5.0 on end #SiI - end + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/tyan/s4882/devicetree.cb =================================================================== --- trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/tyan/s4882/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -17,10 +17,8 @@ # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - chip drivers/pci/onboard - device pci 9.0 on end #Broadcom - device pci 9.1 on end - end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -35,12 +33,9 @@ device pci 0.2 off end device pci 1.0 off end #chip drivers/ati/ragexl - chip drivers/pci/onboard - device pci 6.0 on end - end - chip drivers/pci/onboard - device pci 5.0 on end #SiI - end + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf
Modified: trunk/src/mainboard/via/epia/Config.lb =================================================================== --- trunk/src/mainboard/via/epia/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/epia/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -96,10 +96,7 @@ device pci_domain 0 on device pci 0.0 on end # Northbridge # device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end + # device pci 0.0 on end # Integrated VGA # end chip southbridge/via/vt8231 register "enable_native_ide" = "0"
Modified: trunk/src/mainboard/via/epia/devicetree.cb =================================================================== --- trunk/src/mainboard/via/epia/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/epia/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -2,10 +2,7 @@ device pci_domain 0 on device pci 0.0 on end # Northbridge # device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end + # device pci 0.0 on end # Integrated VGA # end chip southbridge/via/vt8231 register "enable_native_ide" = "0"
Modified: trunk/src/mainboard/via/vt8454c/Config.lb =================================================================== --- trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/vt8454c/Config.lb 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,9 +121,7 @@ device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller device pci 1.0 on # PCI Bridge - chip drivers/pci/onboard - device pci 0.0 on end - end # Onboard Video + device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA #device pci f.1 on end # IDE
Modified: trunk/src/mainboard/via/vt8454c/devicetree.cb =================================================================== --- trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/mainboard/via/vt8454c/devicetree.cb 2009-11-06 23:42:26 UTC (rev 4925) @@ -12,9 +12,7 @@ device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller device pci 1.0 on # PCI Bridge - chip drivers/pci/onboard - device pci 0.0 on end - end # Onboard Video + device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA #device pci f.1 on end # IDE
Modified: trunk/src/northbridge/via/cn400/vga.c =================================================================== --- trunk/src/northbridge/via/cn400/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cn400/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -121,15 +121,8 @@ #endif }
-static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static const struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init,
Modified: trunk/src/northbridge/via/cn700/vga.c =================================================================== --- trunk/src/northbridge/via/cn700/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cn700/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -101,15 +101,8 @@ memset(0xf0000, 0, 0x10000); }
-static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static const struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init,
Modified: trunk/src/northbridge/via/cx700/cx700_vga.c =================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/cx700/cx700_vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -97,15 +97,8 @@ outb(reg8, SR_DATA); }
-static void vga_read_resources(device_t dev) -{ - dev->rom_address = 0xfff80000; - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init,
Modified: trunk/src/northbridge/via/vt8623/northbridge.c =================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/vt8623/northbridge.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -124,9 +124,6 @@ #if 0 /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */ - dev->on_mainboard=1; - dev->rom_address = (void *)0xfffc0000; - pci_dev_init(dev); call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); @@ -167,17 +164,8 @@ #endif }
-static void vga_read_resources(device_t dev) -{ - - dev->rom_address = (void *)0xfffc0000; - dev->on_mainboard=1; - pci_dev_read_resources(dev); - -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init,
Modified: trunk/src/northbridge/via/vx800/vga.c =================================================================== --- trunk/src/northbridge/via/vx800/vga.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/northbridge/via/vx800/vga.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -126,15 +126,8 @@
}
-static void vga_read_resources(device_t dev) -{ - dev->rom_address = (void *)(0xffffffff - CONFIG_ROM_SIZE + 1); - dev->on_mainboard = 1; - pci_dev_read_resources(dev); -} - static struct device_operations vga_operations = { - .read_resources = vga_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vga_init,
Modified: trunk/src/southbridge/nvidia/ck804/chip.h =================================================================== --- trunk/src/southbridge/nvidia/ck804/chip.h 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/southbridge/nvidia/ck804/chip.h 2009-11-06 23:42:26 UTC (rev 4925) @@ -7,8 +7,6 @@ unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned long nic_rom_address; - unsigned long raid_rom_address; unsigned int mac_eeprom_smbus; unsigned int mac_eeprom_addr; };
Modified: trunk/src/southbridge/nvidia/ck804/ck804.c =================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804.c 2009-11-06 17:32:32 UTC (rev 4924) +++ trunk/src/southbridge/nvidia/ck804/ck804.c 2009-11-06 23:42:26 UTC (rev 4925) @@ -77,12 +77,10 @@ case PCI_DEVICE_ID_NVIDIA_CK804_NIC: devfn -= (9 << 3); index = 10; - dev->rom_address = conf->nic_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: devfn -= (9 << 3); index = 10; - dev->rom_address = conf->nic_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_ACI: devfn -= (3 << 3); @@ -95,7 +93,6 @@ case PCI_DEVICE_ID_NVIDIA_CK804_IDE: devfn -= (5 << 3); index = 14; - dev->rom_address = conf->raid_rom_address; break; case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: devfn -= (6 << 3);
R4925 makes my linux hang. Output is attached. My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700). But dbm690t works well. I don't know why.
Can you send the log from r4924?
Thanks, Myles
Log from r4924.
-----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Tuesday, November 10, 2009 12:03 AM To: Bao, Zheng; coreboot@coreboot.org Cc: 'Carl-Daniel Hailfinger'; 'Stefan Reinauer'; 'Marc Jones' Subject: RE: [coreboot] [v2] r4925 makes my linux hang
R4925 makes my linux hang. Output is attached. My board is K8+rs780+sb700, which is close to dbm690t(k8+rs690+sb700). But dbm690t works well. I don't know why.
Can you send the log from r4924?
Thanks, Myles
Log from r4924.
The problem is that the video card gets treated as if it were part of the RS780. In many chipsets, there's a check to see if the device is really part of the chipset before it is initialized using the chipset functions.
rs780_enable: dev=000231dc, VID_DID=0x96151002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x000202f0, dev=0x000231dc, port=0x00000005 PcieLinkTraining port=5:lc current state=0 PcieTrainPort port=0x5 result=0 PCI: 01:05.0 [1002/9615] ops
Maybe we need some way to say "use the default" still? chip default_ops or something?
Thanks, Myles
By "we", please tell me if it has anything to do with the chipset and mainboard code.
Zheng
-----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Tuesday, November 10, 2009 11:31 AM To: Bao, Zheng; coreboot@coreboot.org Cc: 'Carl-Daniel Hailfinger'; 'Stefan Reinauer'; 'Marc Jones' Subject: RE: [coreboot] [v2] r4925 makes my linux hang
Log from r4924.
The problem is that the video card gets treated as if it were part of the RS780. In many chipsets, there's a check to see if the device is really part of the chipset before it is initialized using the chipset functions.
rs780_enable: dev=000231dc, VID_DID=0x96151002 Bus-0, Dev-4,5,6,7, Fun-0. enable=1 gpp_sb_init nb_dev=0x000202f0, dev=0x000231dc, port=0x00000005 PcieLinkTraining port=5:lc current state=0 PcieTrainPort port=0x5 result=0 PCI: 01:05.0 [1002/9615] ops
Maybe we need some way to say "use the default" still? chip default_ops or something?
Thanks, Myles
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng Zheng.Bao@amd.com wrote:
By "we", please tell me if it has anything to do with the chipset and mainboard code.
Sorry I wasn't clear. I meant maybe coreboot needs a generic chip driver.
I think the 780 code needs to check the device to make sure it's part of the chipset before initializing the devices.
Thanks, Myles
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson mylesgw@gmail.com wrote:
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng Zheng.Bao@amd.com wrote:
By "we", please tell me if it has anything to do with the chipset and mainboard code.
Sorry I wasn't clear. I meant maybe coreboot needs a generic chip driver.
I think the 780 code needs to check the device to make sure it's part of the chipset before initializing the devices.
Could you send me your devicetree.cb or Config.lb? Thanks, Myles
On Tue, Nov 10, 2009 at 9:45 AM, Myles Watson mylesgw@gmail.com wrote:
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson mylesgw@gmail.com wrote:
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng Zheng.Bao@amd.com wrote:
By "we", please tell me if it has anything to do with the chipset and mainboard code.
Sorry I wasn't clear. I meant maybe coreboot needs a generic chip driver.
I think the 780 code needs to check the device to make sure it's part of the chipset before initializing the devices.
Could you send me your devicetree.cb or Config.lb?
My thought is that you can put chip drivers/generic/generic around the
video card so that it doesn't get the 780 ops.
Thanks, Myles
Myles Watson wrote:
On Tue, Nov 10, 2009 at 9:45 AM, Myles Watson <mylesgw@gmail.com mailto:mylesgw@gmail.com> wrote:
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson <mylesgw@gmail.com <mailto:mylesgw@gmail.com>> wrote: On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng <Zheng.Bao@amd.com <mailto:Zheng.Bao@amd.com>> wrote: > By "we", please tell me if it has anything to do with the chipset and > mainboard code. Sorry I wasn't clear. I meant maybe coreboot needs a generic chip driver. I think the 780 code needs to check the device to make sure it's part of the chipset before initializing the devices. Could you send me your devicetree.cb or Config.lb?My thought is that you can put chip drivers/generic/generic around the video card so that it doesn't get the 780 ops.
Does it get any 780 ops at all? I'd think it only does when a struct pci_driver is catching it?
Stefan
Could you send me your devicetree.cb or Config.lb?My thought is that you can put chip drivers/generic/generic around the video card so that it doesn't get the 780 ops.
Does it get any 780 ops at all? I'd think it only does when a struct pci_driver is catching it?
I haven't seen the device tree, but the 780 code is initializing it. That seems to be the only difference between the failing and functioning logs.
Thanks, Myles
Config.lb and lspci of mahogany and mahogany_fam10 are attached.
Zheng
________________________________
From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Myles Watson Sent: Tuesday, November 10, 2009 11:46 PM To: Bao, Zheng Cc: Stefan Reinauer; Marc Jones; Carl-Daniel Hailfinger; coreboot@coreboot.org Subject: Re: [coreboot] [v2] r4925 makes my linux hang
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson mylesgw@gmail.com wrote:
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng Zheng.Bao@amd.com wrote:
By "we", please tell me if it has anything to do with the chipset and mainboard code.
Sorry I wasn't clear. I meant maybe coreboot needs a generic chip driver.
I think the 780 code needs to check the device to make sure it's part of the chipset before initializing the devices.
Could you send me your devicetree.cb or Config.lb? Thanks, Myles
Config.lb_mahogany_k8
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on # Internal Graphics P2P bridge 0x9602 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x9615 register "rom_address" = "0xfff00000" end end
I think onboard was removed, and also rom_address because CBFS can be used to find the ROM.
I'm not sure how to best "decouple" the graphics device from the 780.
//Peter
The onboard was not removed because all my work have based on 4924, which has remove the onboard. If I need try the new code, I will remove it.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Peter Stuge Sent: Wednesday, November 11, 2009 11:33 AM To: coreboot@coreboot.org Subject: Re: [coreboot] [v2] r4925 makes my linux hang
Config.lb_mahogany_k8
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on # Internal Graphics P2P bridge 0x9602 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics
0x9615
register "rom_address" = "0xfff00000" endend
I think onboard was removed, and also rom_address because CBFS can be used to find the ROM.
I'm not sure how to best "decouple" the graphics device from the 780.
//Peter
Peter Stuge wrote:
Config.lb_mahogany_k8
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on # Internal Graphics P2P bridge 0x9602 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x9615 register "rom_address" = "0xfff00000" end end
I would think the above does not compile anymore with HEAD.
I think onboard was removed, and also rom_address because CBFS can be used to find the ROM.
I'm not sure how to best "decouple" the graphics device from the 780.
What do you mean by decouple?
There is likely a
static struct pci_driver pcie_driver_780 __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX, };
and that is why a non-standard .ops is associated with that device.
If the problem is chip_ops:
This is how it should look if the graphics device is supposed to have the chip_ops of the 780 attached (ie the internal graphicsw can use values from struct southbridge_amd_rs780_config
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on # Internal Graphics P2P bridge 0x9602 device pci 5.0 on end # Internal Graphics 0x9615 end
This is different from the old behavior, however... It gives a different set of chip_ops to the internal graphics chip:
struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("AMD RS780 Northbridge") .enable_dev = enable_dev, };
Now, I don't know the RS780 code but if it is based on/similar to the RS690 code I think I know what's wrong.
This is from RS690: /*********************************************** * 0:00.0 NBCFG : * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default * 0:01.0 P2P Internal: * 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 * case 0 will be called twice, one is by cpu in hypertransport.c line458, * the other is by rs690. ***********************************************/ void rs690_enable(device_t dev) { ... dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ ... case 1: /* bus0, dev1 */ printk_info("Bus-0, Dev-1, Fun-0.\n"); break; ... case 4: /* bus0, dev4-7, four GPP */ case 5: case 6: case 7: printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs690_gpp_sb_init(nb_dev, dev, dev_ind); break; ... }
Now let's think about that for a minute:
* case 0 will not only match for bus 0, device 0, function 0. Instead it will ignore bus and function. So it will listen to all device 0 that have an ams_rs690_ops called * The same appears for case 5. Instead of calling it for 0:5.0 it also gets called for 1:5.0 (or whatever bus gfx is on) and will treat it as a device that it is not.
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics driver which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
Stefan
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics driver which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
The only downside is that the subsystem IDs won't be set, because the device will not be "on mainboard" anymore.
Thanks, Myles
Myles Watson wrote:
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics driver which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
The only downside is that the subsystem IDs won't be set, because the device will not be "on mainboard" anymore.
It should be set, since there is a driver for that device....
On Wed, Nov 11, 2009 at 2:26 PM, Stefan Reinauer stepan@coresystems.de wrote:
Myles Watson wrote:
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics driver which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
The only downside is that the subsystem IDs won't be set, because the device will not be "on mainboard" anymore.
It should be set, since there is a driver for that device....
Great. I thought it only got set if it was found in the device tree.
Thanks, Myles
Myles Watson wrote:
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics driver which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
The only downside is that the subsystem IDs won't be set, because the device will not be "on mainboard" anymore.
... a viable alternative is fixing the chip's enable_dev to take the bus and function number into regard.
Stefan
Great!!
It fixes the hanging on my board. And the display also works. Everything seems to be fine.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer Sent: Thursday, November 12, 2009 5:30 AM To: Myles Watson Cc: coreboot@coreboot.org Subject: Re: [coreboot] [v2] r4925 makes my linux hang
Myles Watson wrote:
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics
driver
which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
The only downside is that the subsystem IDs won't be set, because the
device
will not be "on mainboard" anymore.
... a viable alternative is fixing the chip's enable_dev to take the bus and function number into regard.
Stefan
Other boards like 690/600 need to modify, don't they?
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Bao, Zheng Sent: Friday, November 13, 2009 12:07 PM To: Stefan Reinauer; Myles Watson Cc: Marc Jones; coreboot@coreboot.org Subject: Re: [coreboot] [v2] r4925 makes my linux hang
Great!!
It fixes the hanging on my board. And the display also works. Everything seems to be fine.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Stefan Reinauer Sent: Thursday, November 12, 2009 5:30 AM To: Myles Watson Cc: coreboot@coreboot.org Subject: Re: [coreboot] [v2] r4925 makes my linux hang
Myles Watson wrote:
The good news is: chip southbridge/amd/rs780 unconditionally pulls in the graphics
driver
which is still executed per PCI ID, and not per notation of static.c
So it's completely enough to drop the graphics device from Config.lb/devicetree.cb and say
chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
The only downside is that the subsystem IDs won't be set, because the
device
will not be "on mainboard" anymore.
... a viable alternative is fixing the chip's enable_dev to take the bus and function number into regard.
Stefan
Other boards like 690/600 need to modify, don't they?
I don't have any boards with those chipsets. I thought you said the dbm690t was fine, but I don't know for sure.
Thanks, Myles
Now my VGA BIOS seems to run incorrectly.
Without_entry.txt: The output of image running with Config.lb like, chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
With_entry.txt: The output of image running with Config.lib like chip southbridge/amd/rs780 device pci 0.0 on # HT 0x9600 device pci 5.0 on end end device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
That only happens when the CPU is K8. When the cpu is fam10, VGA runs ok. Any advice?
Zheng
-----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Saturday, November 14, 2009 12:34 AM To: Bao, Zheng; 'Stefan Reinauer' Cc: 'Marc Jones'; coreboot@coreboot.org Subject: RE: [coreboot] [v2] r4925 makes my linux hang
Other boards like 690/600 need to modify, don't they?
I don't have any boards with those chipsets. I thought you said the dbm690t was fine, but I don't know for sure.
Thanks, Myles
Bao, Zheng wrote:
Now my VGA BIOS seems to run incorrectly.
Without_entry.txt: The output of image running with Config.lb like, chip southbridge/amd/rs780 device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
With_entry.txt: The output of image running with Config.lib like chip southbridge/amd/rs780 device pci 0.0 on # HT 0x9600 device pci 5.0 on end end device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
That only happens when the CPU is K8. When the cpu is fam10, VGA runs ok. Any advice?
In the second case it seems to die in ACPI table creation, during VGA init...
You can try to enable and use the GDB backend to find out where exactly it dies...
http://www.coreboot.org/Debugging
Stefan
That only happens when the CPU is K8. When the cpu is fam10, VGA runs ok. Any advice?
I'd be interested in the complete logs, and a log from a successful fam10 boot.
Thanks, Myles
Here comes the complete logs.
Zheng
-----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Monday, November 16, 2009 10:21 PM To: Bao, Zheng Cc: Stefan Reinauer; Marc Jones; coreboot@coreboot.org Subject: Re: [coreboot] [v2] r4925 makes my linux hang
That only happens when the CPU is K8. When the cpu is fam10, VGA runs ok. Any advice?
I'd be interested in the complete logs, and a log from a successful fam10 boot.
Thanks, Myles
Here comes the complete logs.
I only got the fam10 log, I didn't see the complete k8 logs.
Thanks, Myles
Here comes the complete log. The family 10 is also attached for your convenience.
Zheng
-----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Monday, November 23, 2009 11:24 PM To: Bao, Zheng Cc: coreboot@coreboot.org Subject: RE: [coreboot] [v2] r4925 makes my linux hang
Here comes the complete logs.
I only got the fam10 log, I didn't see the complete k8 logs.
Thanks, Myles
Zheng,
From the K8 log:
PCI: 00:02.0: enabled 0, 0 resources PCI: 00:03.0: enabled 0, 0 resources
These devices are enabled for fam10, but disabled for the K8 board. I thought the only difference was supposed to be the processor/northbridge.
Because of that, rs780_gfx_init doesn't get run. UMA is also different.
I'm not sure what's actually breaking it, but it would be easier to tell if you minimize some of those differences.
Thanks, Myles
These devices used to be enabled. I just disabled when the internal gfx hanged. I tried again with those enabled, the log is not much different except the message printed in rs780_gfx_init.
Zheng
-----Original Message----- From: Myles Watson [mailto:mylesgw@gmail.com] Sent: Wednesday, November 25, 2009 12:10 AM To: Bao, Zheng Cc: 'coreboot' Subject: RE: [coreboot] [v2] r4925 makes my linux hang
Zheng,
From the K8 log:
PCI: 00:02.0: enabled 0, 0 resources PCI: 00:03.0: enabled 0, 0 resources
These devices are enabled for fam10, but disabled for the K8 board. I thought the only difference was supposed to be the processor/northbridge.
Because of that, rs780_gfx_init doesn't get run. UMA is also different.
I'm not sure what's actually breaking it, but it would be easier to tell if you minimize some of those differences.
Thanks, Myles
Since I don't have the hardware, I only have the log files to look at. Could you send a working log file with the onboard patch and the broken one without it? That way the only differences should be related to that change.
Thanks, Myles
I could not narrow down the difference to a minimum scale. When I started merge my code to the official code, it kept not working for a long time. So the latest working code has to be got from my own repository, which doesn't have CBFS support. Please see if it is help.
Zheng
-----Original Message----- From: coreboot-bounces+zheng.bao=amd.com@coreboot.org [mailto:coreboot-bounces+zheng.bao=amd.com@coreboot.org] On Behalf Of Myles Watson Sent: Wednesday, November 25, 2009 10:09 PM To: Bao, Zheng Cc: 'coreboot' Subject: Re: [coreboot] [v2] r4925 makes my linux hang
Since I don't have the hardware, I only have the log files to look at. Could you send a working log file with the onboard patch and the broken one without it? That way the only differences should be related to that change.
Thanks, Myles
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Bao, Zheng -
Myles Watson -
Peter Stuge -
Stefan Reinauer