coreboot November 2009

coreboot@coreboot.org

55 participants
232 discussions

[commit] r4950 - in trunk/targets/tyan: s2912 s2912_fam10
by svn＠coreboot.org 19 Nov '09

19 Nov '09

Author: myles Date: 2009-11-19 15:25:31 +0100 (Thu, 19 Nov 2009) New Revision: 4950 Modified: trunk/targets/tyan/s2912/Config.lb trunk/targets/tyan/s2912_fam10/Config.lb Log: Trivial fix for tyan/s2912 to build. Remove overspecified options in Config.lb. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/targets/tyan/s2912/Config.lb =================================================================== --- trunk/targets/tyan/s2912/Config.lb 2009-11-18 17:10:36 UTC (rev 4949) +++ trunk/targets/tyan/s2912/Config.lb 2009-11-19 14:25:31 UTC (rev 4950) @@ -24,74 +24,19 @@ target s2912 mainboard tyan/s2912 -# serengeti_leopard romimage "normal" -# 48K for SCSI FW -# option CONFIG_ROM_SIZE = 475136 -# 48K for SCSI FW and 48K for ATI ROM -# option CONFIG_ROM_SIZE = 425984 -# 64K for Etherboot -# option CONFIG_ROM_SIZE = 458752 -# 44k for atixx.rom -# option CONFIG_ROM_SIZE = 479232 - option CONFIG_USE_FAILOVER_IMAGE=0 + option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x18800 - option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x15800 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" -# payload ../../../payloads/tg3--ide_disk.zelf -# payload ../../../payloads/filo.elf -# payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo.zelf -# payload ../../../payloads/tg3--filo_hda2.zelf -# payload ../../../payloads/tg3.zelf -# payload ../../../../payloads/tg3_vga.zelf -# payload ../../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf - payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf -# payload ../../../payloads/tg3_com2.zelf -# payload ../../../payloads/e1000--filo.zelf -# payload ../../../payloads/tg3--e1000--filo.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf + payload ../payload.elf end romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 -# option CONFIG_ROM_IMAGE_SIZE=0x13800 -# option CONFIG_ROM_IMAGE_SIZE=0x19800 - option CONFIG_ROM_IMAGE_SIZE=0x20000 -# option CONFIG_ROM_IMAGE_SIZE=0x15800 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" -# payload ../../../payloads/tg3--ide_disk.zelf -# payload ../../../payloads/filo.elf -# payload ../../../payloads/filo_mem.elf -# payload ../../../payloads/filo.zelf -# payload ../../../payloads/tg3--filo_hda2.zelf -# payload ../../../payloads/tg3.zelf -# payload ../../../../payloads/tg3_vga.zelf -# payload ../../../../payloads/memtest -# payload ../../../../payloads/e1000_vga.zelf -# payload ../../../../payloads/tg3--filo_hda2_vga.zelf -# payload ../../../../payloads/filo_hda.zelf -# payload ../../../../payloads/adlo.elf -# payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf -# payload ../../../../payloads/forcedeth_mcp55_filo_hda2.zelf - payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf -# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf -# payload ../../../payloads/tg3_com2.zelf -# payload ../../../payloads/e1000--filo.zelf -# payload ../../../payloads/tg3--e1000--filo.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf -# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf +# payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf + payload ../payload.elf end romimage "failover" @@ -102,5 +47,4 @@ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" end -#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" Modified: trunk/targets/tyan/s2912_fam10/Config.lb =================================================================== --- trunk/targets/tyan/s2912_fam10/Config.lb 2009-11-18 17:10:36 UTC (rev 4949) +++ trunk/targets/tyan/s2912_fam10/Config.lb 2009-11-19 14:25:31 UTC (rev 4950) @@ -30,18 +30,13 @@ romimage "normal" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=0x20000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" -# payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf payload ../payload.elf end romimage "fallback" option CONFIG_USE_FAILOVER_IMAGE=0 option CONFIG_USE_FALLBACK_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=0x20000 - option CONFIG_XIP_ROM_SIZE=0x40000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" # payload ../../../../payloads/forcedeth--filo_hda2_vga_5_4_2_mcp55.zelf payload ../payload.elf

1 0

SerialICE mailing list
by Stefan Reinauer 18 Nov '09

18 Nov '09

Hi, SerialICE, our Qemu based (x86) firmware debugger got its own mailing list now. You can subscribe to the (quite low traffic) mailing list at http://serialice.com/mailman/listinfo/serialice More information about SerialICE: http://www.serialice.com/ Latest announcement on the Qemu mailing list: http://lists.gnu.org/archive/html/qemu-devel/2009-10/msg02464.html Regards, Stefan -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: info(a)coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866

1 0

[OT] machine check related to promotion to a large page
by Andriy Gapon 18 Nov '09

18 Nov '09

Sorry for the offtopic, but I see from time to time technical people from amd.com writing to this list, so I decided to try my luck. I would be very grateful for any help with the following issues. Perhaps, I could be referred to the proper technical contacts. FreeBSD starting with upcoming 8.0 version has transparent support for large pages (superpages in FreeBSD terms). This means that an eligible range of 4KB pages can be promoted to a 4MB page at an opportune moment. The large page can also be broken down into normal pages when needed, of course. Large pages can also be explicitly allocated, but that is beside the point. We seem to have a problem, that is perhaps caused by lack of strictness in our code, that looks to be caused by the mentioned above superpages feature. But the problem manifests itself only on AMD family 10h processors. To be precise, we have reports that family Fh is not affected, all problem reports are for family 10h and we have no positive or negative reports for family 11h. Another mandatory condition for the problem to manifest itself is having machine check enabled by either BIOS or OS. Also, the problem is reported only for long mode. So, the actual problem manifestation is a machine check report about parity error in DC TLB L1. All reporters have confirmed that they don't experience any problems if the superpages feature is turned off. So it seems likely that this machine check report is not indicative of a hardware fault. It looks that the way our code currently works it is possible that we could get into a situation where two TLB entries would exist for the same linear-to-physical translation. One through a large page and another through a normal page. Most likely both should be correct (point to the same physical location). Is it possible that such a situation could lead the integrity checking logic to believe that there is a parity error in TLB? I've searched though the errata for family 10h processors but couldn't find one that would match. Examples of processors affected by the problem (as reported by FreeBSD kernel): 1). CPU: AMD Athlon(tm) II X2 250 Processor (3013.75-MHz K8-class CPU) Origin = "AuthenticAMD" Id = 0x100f62 Stepping = 2 Features=0x178bfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,MMX,FXSR,SSE,SSE2,HTT> Features2=0x802009<SSE3,MON,CX16,POPCNT> AMD Features=0xee500800<SYSCALL,NX,MMX+,FFXSR,Page1GB,RDTSCP,LM,3DNow!+,3DNow!> AMD Features2=0x37ff<LAHF,CMP,SVM,ExtAPIC,CR8,ABM,SSE4A,MAS,Prefetch,OSVW,IBS,SKINIT,WDT> 2). CPU: Quad-Core AMD Opteron(tm) Processor 2352 (2100.09-MHz K8-class CPU) Origin = "AuthenticAMD" Id = 0x100f23 Stepping = 3 Features=0x178bfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,MMX,FXSR,SSE,SSE2,HTT> Features2=0x802009<SSE3,MON,CX16,POPCNT> AMD Features=0xee400800<SYSCALL,MMX+,FFXSR,Page1GB,RDTSCP,LM,3DNow!+,3DNow!> AMD Features2=0x7ff<LAHF,CMP,SVM,ExtAPIC,CR8,ABM,SSE4A,MAS,Prefetch,OSVW,IBS> This is how FreeBSD MCA code reported the machine check: MCA: CPU 5 UNCOR PCC OVER DTLB L1 error MCA: Address 0x80e5c8000 My guess of possible FreeBSD code issue: 4K mappings are not flushed when corresponding PDE is updated from pointing to PT to pointing to a 2M page. Thank you. -- Andriy Gapon

1 0

[commit] r4949 - trunk/src/northbridge/amd/amdk8
by svn＠coreboot.org 18 Nov '09

18 Nov '09

Author: myles Date: 2009-11-18 18:10:36 +0100 (Wed, 18 Nov 2009) New Revision: 4949 Modified: trunk/src/northbridge/amd/amdk8/amdk8.h trunk/src/northbridge/amd/amdk8/util.c Log: Update amdk8/util.c since __PRE_RAM__. Make node & link more unique. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/northbridge/amd/amdk8/amdk8.h =================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8.h 2009-11-18 03:47:34 UTC (rev 4948) +++ trunk/src/northbridge/amd/amdk8/amdk8.h 2009-11-18 17:10:36 UTC (rev 4949) @@ -8,6 +8,8 @@ #include "amdk8_pre_f.h" #endif +#ifndef __PRE_RAM__ void showallroutes(int level, device_t dev); +#endif #endif /* AMDK8_H */ Modified: trunk/src/northbridge/amd/amdk8/util.c =================================================================== --- trunk/src/northbridge/amd/amdk8/util.c 2009-11-18 03:47:34 UTC (rev 4948) +++ trunk/src/northbridge/amd/amdk8/util.c 2009-11-18 17:10:36 UTC (rev 4949) @@ -25,7 +25,7 @@ * It can be called after RAM is set up by including amdk8.h and enabling the * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc. */ -#ifndef __ROMCC__ +#ifndef __PRE_RAM__ #include <console/console.h> #include <string.h> #include <device/pci.h> @@ -95,7 +95,7 @@ * Return the node number. * For one case (config registers) these are not the right bit fields. */ -static int node(u32 reg) +static int r_node(u32 reg) { return BITS(reg, 0, 0x7); } @@ -104,7 +104,7 @@ * Return the link number. * For one case (config registers) these are not the right bit fields. */ -static int link(u32 reg) +static int r_link(u32 reg) { return BITS(reg, 4, 0x3); } @@ -125,7 +125,7 @@ do_printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", which, (((u64) base & 0xffff0000) << 8), (((u64) lim & 0xffff0000) << 8) + 0xffffff, - node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); + r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); } /** @@ -140,7 +140,7 @@ */ static void showconfig(int level, u8 which, u32 reg) { - /* Don't use node() and link() here. */ + /* Don't use r_node() and r_link() here. */ do_printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), @@ -163,7 +163,7 @@ { do_printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", which, BITS(base, 12, 0x3fff) << 12, - (BITS(lim, 12, 0x3fff) << 12) + 0xfff, node(lim), link(lim), + (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); } @@ -183,8 +183,8 @@ do_printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " "CPU disable %d, Lock %d, Non posted %d\n", which, ((u64) BITS(base, 0, 0xffffff00)) << 8, - (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, node(lim), - link(lim), re(base), we(base), BITS(base, 4, 0x1), + (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), + r_link(lim), re(base), we(base), BITS(base, 4, 0x1), BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); }

1 0

[PATCH] The GPIO base address for TIM-5690.
by Libra Li 18 Nov '09

18 Nov '09

Hi, This is a patch for control DIP switch and digital I/O. Thanks. Signed-off-by: Libra Li <libra.li(a)technexion.com>

2 1

[commit] r4948 - trunk/src/mainboard/technexion/tim5690
by svn＠coreboot.org 18 Nov '09

18 Nov '09

Author: myles Date: 2009-11-18 04:47:34 +0100 (Wed, 18 Nov 2009) New Revision: 4948 Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c Log: This is a patch to control the DIP switch and digital I/O. Signed-off-by: Libra Li <libra.li(a)technexion.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c =================================================================== --- trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-17 15:20:22 UTC (rev 4947) +++ trunk/src/mainboard/technexion/tim5690/cache_as_ram_auto.c 2009-11-18 03:47:34 UTC (rev 4948) @@ -145,6 +145,20 @@ } #endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ +/* Early mainboard specific GPIO setup. */ +static void mb_gpio_init(void) +{ + /* Init Super I/O GPIOs. Done early. */ + it8712f_enter_conf(); + outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); + outb(IT8712F_GPIO, SIO_DATA); + outb(0x62, SIO_INDEX); // set Simple I/O Base Address 0x200 + outb(0x02, SIO_DATA); + outb(0x63, SIO_INDEX); + outb(0x00, SIO_DATA); + it8712f_exit_conf(); +} + void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -177,6 +191,7 @@ /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + mb_gpio_init(); it8712f_kill_watchdog(); uart_init(); console_init();

1 0

irq routing in multi-core environment
by Baski 18 Nov '09

18 Nov '09

Hi,In a multi-core environment, how can we selectively route the irq's of certain devices to certain cpu-cores via coreboot ?Thanks -- baski

1 0

[commit] r4947 - in trunk/src: cpu/amd/dualcore devices
by svn＠coreboot.org 17 Nov '09

17 Nov '09

Author: myles Date: 2009-11-17 16:20:22 +0100 (Tue, 17 Nov 2009) New Revision: 4947 Modified: trunk/src/cpu/amd/dualcore/amd_sibling.c trunk/src/devices/pci_rom.c Log: Silence two warnings. Only use the Qemu hard-coded address for VGA devices. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/amd/dualcore/amd_sibling.c =================================================================== --- trunk/src/cpu/amd/dualcore/amd_sibling.c 2009-11-17 11:52:18 UTC (rev 4946) +++ trunk/src/cpu/amd/dualcore/amd_sibling.c 2009-11-17 15:20:22 UTC (rev 4947) @@ -13,7 +13,6 @@ #include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/amdk8_sysconf.h> -static int first_time = 1; static int disable_siblings = !CONFIG_LOGICAL_CPUS; #include "dualcore_id.c" @@ -116,7 +115,10 @@ return apicid_base; } + #if 0 +static int first_time = 1; + void amd_sibling_init(device_t cpu) { unsigned i, siblings; Modified: trunk/src/devices/pci_rom.c =================================================================== --- trunk/src/devices/pci_rom.c 2009-11-17 11:52:18 UTC (rev 4946) +++ trunk/src/devices/pci_rom.c 2009-11-17 15:20:22 UTC (rev 4947) @@ -46,11 +46,13 @@ rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { - #if CONFIG_BOARD_EMULATION_QEMU_X86 - rom_address = 0xc0000; - #else - return NULL; + #if defined(CONFIG_BOARD_EMULATION_QEMU_X86) \ + && CONFIG_BOARD_EMULATION_QEMU_X86 + if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) + rom_address = 0xc0000; + else #endif + return NULL; } else { /* enable expansion ROM address decoding */ pci_write_config32(dev, PCI_ROM_ADDRESS,

1 0

Qemu and SeaBios.
by Knut Kujat 17 Nov '09

17 Nov '09

Hi, since I want to use SeaBios on my real MoBo I wanted to try it out first using Qemu so I compiled coreboot v2 with the emulation MoBo and using the latest seabios-0.4.2. Now the problem is that qemu is booting all the time without getting seabios fully loaded: Got a payload Loading segment from rom address 0xfffc6878 data (compression=1) malloc Enter, size 36, free_mem_ptr 00119130 malloc 00119130 New segment dstaddr 0xef000 memsize 0x11000 srcaddr 0xfffc68b0 filesize 0x8612 (cleaned up) New segment addr 0xef000 size 0x11000 offset 0xfffc68b0 filesize 0x8612 Loading segment from rom address 0xfffc6894 Entry Point 0x000fc1ec Loading Segment: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x0000000000008612 lb: [0x0000000000100000, 0x000000000011c000) Post relocation: addr: 0x00000000000ef000 memsz: 0x0000000000011000 filesz: 0x0000000000008612 using LZMA lzma: Decoding error = 1 [ 0x00000000000ef000, 00000000000ef000, 0x0000000000100000) <- 00000000fffc68b0 Clearing Segment: addr: 0x00000000000ef000 memsz: 0x0000000000011000 dest 000ef000, end 00100000, bouncebuffer 3fc8000 Loaded segments Jumping to boot code at fc1ec entry = 0x000fc1ec lb_start = 0x00100000 lb_size = 0x0001c000 adjust = 0x03ee4000 buffer = 0x03fc8000 elf_boot_notes = 0x0010c25c adjusted_boot_notes = 0x03ff025c -->> reboots Now I'm concerned that this could be happening on the real board,too. I already tried to compile seabios from the source same result. I tried to use it with a linux.img to see if it boots but nothing! I'm having the same problem with the "ready to use" coreboot v2 + SeaBios from the coreboot wiki. any suggestions? I have a coreboot + seabios compiled and ready to flash it to the real board but I'm now scared like hell it just will boot and boot. thx, Knut Kujat

2 1

[commit] r4946 - trunk/util/nvramtool
by svn＠coreboot.org 17 Nov '09

17 Nov '09

Author: oxygene Date: 2009-11-17 12:52:18 +0100 (Tue, 17 Nov 2009) New Revision: 4946 Modified: trunk/util/nvramtool/cmos_lowlevel.c Log: Initialize memory before using it. put_bits wants it that way. Trivial. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/nvramtool/cmos_lowlevel.c =================================================================== --- trunk/util/nvramtool/cmos_lowlevel.c 2009-11-16 17:29:22 UTC (rev 4945) +++ trunk/util/nvramtool/cmos_lowlevel.c 2009-11-17 11:52:18 UTC (rev 4946) @@ -93,7 +93,7 @@ result = 0; if (e->config == CMOS_ENTRY_STRING) - { char *newstring = malloc((length+7)/8); + { char *newstring = calloc(1, (length+7)/8); unsigned usize = (8 * sizeof(unsigned long long)); if(!newstring) { out_of_memory(); }

1 0

← Newer
1
...
7
8
9
10
11
12
13
...
24
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2009