coreboot November 2009

coreboot@coreboot.org

55 participants
232 discussions

[commit] r4961 - trunk/src/arch/i386/init
by svn＠coreboot.org 27 Nov '09

27 Nov '09

Author: oxygene Date: 2009-11-27 15:32:17 +0100 (Fri, 27 Nov 2009) New Revision: 4961 Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Log: Let ld(1) calculate the required size for code in the bootblock automatically. Signed-off-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb =================================================================== --- trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb 2009-11-27 11:04:08 UTC (rev 4960) +++ trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb 2009-11-27 14:32:17 UTC (rev 4961) @@ -40,8 +40,10 @@ _x = .; . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x; + __my_rom_start = .; + /* This section might be better named .setup */ - .rom . : { + .rom _myrom : { _rom = .; *(.rom.text); *(.rom.data); @@ -54,6 +56,7 @@ } _lrom = LOADADDR(.rom); + _elrom = LOADADDR(.rom) + SIZEOF(.rom); /DISCARD/ : { @@ -62,4 +65,13 @@ *(.comment.*) *(.note.*) } + + __my_rom_end = .; + + __my_rom_size = (( ( __my_rom_end - __my_rom_start ) / 256) + 2 ) * 256; + /* Next line gives same output for me as above one but causes + * ld to complain about non constant offset so + __my_rom_size = (( (SIZEOF(.rom) + SIZEOF(.data) + SIZEOF(.text)) / 256 ) + 2 ) * 256; + */ + _myrom = _rom + (0x10000 - __my_rom_size); }

1 0

[PATCH]clean up bootblocksize handling in cbfstool, kconfig
by Patrick Georgi 27 Nov '09

27 Nov '09

Hi, attached patch cleans up the bootblock size handling: 1. cbfstool create does no longer take a value it doesn't parse anyway (bootblocksize), but creates a bootblock of the size of the file that's filled in. 2. kconfig and newconfig are adapted to not pass the value 3. CONFIG_ROMBASE in kconfig isn't set to the ROM size, but to 4GB-64KB, ie. the standard start address of the bootblock. That's how it's used anyway (which didn't show because the linker script moves into top 64K if necessary) 4. BOOTBLOCK_SIZE in src/arch/i386/Makefile.inc isn't used anymore, so it's dropped. Change #1 requires #2, so mixing cbfstool versions must not happen (but usually won't happen) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Patrick

7 29

[commit] r4960 - trunk/src/mainboard/tyan
by svn＠coreboot.org 27 Nov '09

27 Nov '09

Author: oxygene Date: 2009-11-27 12:04:08 +0100 (Fri, 27 Nov 2009) New Revision: 4960 Modified: trunk/src/mainboard/tyan/Kconfig Log: Really hook up s2850 and s2875. Trivial. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/tyan/Kconfig =================================================================== --- trunk/src/mainboard/tyan/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) +++ trunk/src/mainboard/tyan/Kconfig 2009-11-27 11:04:08 UTC (rev 4960) @@ -24,6 +24,8 @@ source "src/mainboard/tyan/s1846/Kconfig" source "src/mainboard/tyan/s2735/Kconfig" +source "src/mainboard/tyan/s2850/Kconfig" +source "src/mainboard/tyan/s2875/Kconfig" source "src/mainboard/tyan/s2880/Kconfig" source "src/mainboard/tyan/s2881/Kconfig" source "src/mainboard/tyan/s2882/Kconfig"

1 0

[commit] r4959 - in trunk/src/mainboard: amd/dbm690t amd/pistachio amd/serengeti_cheetah asus/a8n_e asus/a8v-e_se asus/m2v-mx_se broadcom/blast dell/s1850 gigabyte/ga_2761gxdk intel/jarrell intel/mtarvon intel/truxton intel/xe7501devkit iwill/dk8_htx iwill/dk8s2 msi/ms9185 newisys/khepri sunw/ultra40 supermicro/h8dme supermicro/h8dmr supermicro/x6dhr_ig supermicro/x6dhr_ig2 technexion/tim8690 tyan/s1846 tyan/s2735 tyan/s2850 tyan/s2875 tyan/s2912 tyan/s4880 tyan/s4882 via/epia via/epia-cn via/epi
by svn＠coreboot.org 27 Nov '09

27 Nov '09

Author: oxygene Date: 2009-11-27 12:03:20 +0100 (Fri, 27 Nov 2009) New Revision: 4959 Modified: trunk/src/mainboard/amd/dbm690t/Kconfig trunk/src/mainboard/amd/pistachio/Kconfig trunk/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/src/mainboard/asus/a8n_e/Kconfig trunk/src/mainboard/asus/a8v-e_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/broadcom/blast/Kconfig trunk/src/mainboard/dell/s1850/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/src/mainboard/intel/jarrell/Kconfig trunk/src/mainboard/intel/mtarvon/Kconfig trunk/src/mainboard/intel/truxton/Kconfig trunk/src/mainboard/intel/xe7501devkit/Kconfig trunk/src/mainboard/iwill/dk8_htx/Kconfig trunk/src/mainboard/iwill/dk8s2/Kconfig trunk/src/mainboard/msi/ms9185/Kconfig trunk/src/mainboard/newisys/khepri/Kconfig trunk/src/mainboard/sunw/ultra40/Kconfig trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig trunk/src/mainboard/technexion/tim8690/Kconfig trunk/src/mainboard/tyan/s1846/Options.lb trunk/src/mainboard/tyan/s2735/Kconfig trunk/src/mainboard/tyan/s2850/Kconfig trunk/src/mainboard/tyan/s2875/Kconfig trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s4880/Kconfig trunk/src/mainboard/tyan/s4882/Kconfig trunk/src/mainboard/via/epia-cn/Options.lb trunk/src/mainboard/via/epia-m/Options.lb trunk/src/mainboard/via/epia-n/Options.lb trunk/src/mainboard/via/epia/Options.lb Log: Make newconfig and kconfig agree on MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID Usually, this means adding values to Kconfig, but in a few cases, adding values to newconfig, too (which doesn't hurt). Also really hook up tyan/s2850 and tyan/s2875 to kconfig, and have them still build. Trivial and stupid kconfig changes, just lots of them. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/amd/dbm690t/Kconfig =================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/amd/dbm690t/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -102,3 +102,13 @@ int default 11 depends on BOARD_AMD_DBM690T + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_AMD_DBM690T + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3050 + depends on BOARD_AMD_DBM690T Modified: trunk/src/mainboard/amd/pistachio/Kconfig =================================================================== --- trunk/src/mainboard/amd/pistachio/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/amd/pistachio/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -101,3 +101,13 @@ int default 11 depends on BOARD_AMD_PISTACHIO + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_AMD_PISTACHIO + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3050 + depends on BOARD_AMD_PISTACHIO Modified: trunk/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -114,3 +114,14 @@ int default 11 depends on BOARD_AMD_SERENGETI_CHEETAH + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_AMD_SERENGETI_CHEETAH + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2b80 + depends on BOARD_AMD_SERENGETI_CHEETAH + Modified: trunk/src/mainboard/asus/a8n_e/Kconfig =================================================================== --- trunk/src/mainboard/asus/a8n_e/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/asus/a8n_e/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -103,3 +103,14 @@ int default 13 depends on BOARD_ASUS_A8N_E + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + depends on BOARD_ASUS_A8N_E + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x815a + depends on BOARD_ASUS_A8N_E + Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig =================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/asus/a8v-e_se/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -103,3 +103,9 @@ int default 13 depends on BOARD_ASUS_A8V_E_SE + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + depends on BOARD_ASUS_A8V_E_SE + Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig =================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -111,3 +111,8 @@ default 0x20 depends on BOARD_ASUS_M2V_MX_SE +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + depends on BOARD_ASUS_M2V_MX_SE + Modified: trunk/src/mainboard/broadcom/blast/Kconfig =================================================================== --- trunk/src/mainboard/broadcom/blast/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/broadcom/blast/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -104,3 +104,14 @@ int default 11 depends on BOARD_BROADCOM_BLAST + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x161f + depends on BOARD_BROADCOM_BLAST + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3050 + depends on BOARD_BROADCOM_BLAST + Modified: trunk/src/mainboard/dell/s1850/Kconfig =================================================================== --- trunk/src/mainboard/dell/s1850/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/dell/s1850/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -9,6 +9,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_1024 + select UDELAY_TSC config MAINBOARD_DIR string @@ -32,12 +33,12 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x016c + default 0x5580 depends on BOARD_DELL_S1850 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex - default 0x1028 + default 0x15d9 depends on BOARD_DELL_S1850 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig =================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -133,12 +133,12 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex - default 0x1022 + default 0x1039 depends on BOARD_GIGABYTE_GA_2761GXDK config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x2b80 + default 0x1234 depends on BOARD_GIGABYTE_GA_2761GXDK config IRQ_SLOT_COUNT Modified: trunk/src/mainboard/intel/jarrell/Kconfig =================================================================== --- trunk/src/mainboard/intel/jarrell/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/intel/jarrell/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -43,3 +43,13 @@ default 9 depends on BOARD_INTEL_JARRELL +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + depends on BOARD_INTEL_JARRELL + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1079 + depends on BOARD_INTEL_JARRELL + Modified: trunk/src/mainboard/intel/mtarvon/Kconfig =================================================================== --- trunk/src/mainboard/intel/mtarvon/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/intel/mtarvon/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -39,3 +39,13 @@ int default 1 depends on BOARD_INTEL_MTARVON + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + depends on BOARD_INTEL_MTARVON + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2680 + depends on BOARD_INTEL_MTARVON Modified: trunk/src/mainboard/intel/truxton/Kconfig =================================================================== --- trunk/src/mainboard/intel/truxton/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/intel/truxton/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -41,3 +41,13 @@ default 1 depends on BOARD_INTEL_TRUXTON +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + depends on BOARD_INTEL_TRUXTON + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2680 + depends on BOARD_INTEL_TRUXTON + Modified: trunk/src/mainboard/intel/xe7501devkit/Kconfig =================================================================== --- trunk/src/mainboard/intel/xe7501devkit/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/intel/xe7501devkit/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -52,3 +52,14 @@ int default 2 depends on BOARD_INTEL_XE7501DEVKIT + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + depends on BOARD_INTEL_XE7501DEVKIT + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2480 + depends on BOARD_INTEL_XE7501DEVKIT + Modified: trunk/src/mainboard/iwill/dk8_htx/Kconfig =================================================================== --- trunk/src/mainboard/iwill/dk8_htx/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/iwill/dk8_htx/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -108,3 +108,14 @@ int default 11 depends on BOARD_IWILL_DK8_HTX + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_IWILL_DK8_HTX + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2b80 + depends on BOARD_IWILL_DK8_HTX + Modified: trunk/src/mainboard/iwill/dk8s2/Kconfig =================================================================== --- trunk/src/mainboard/iwill/dk8s2/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/iwill/dk8s2/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -107,3 +107,14 @@ int default 11 depends on BOARD_IWILL_DK8S2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x161f + depends on BOARD_IWILL_DK8S2 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3016 + depends on BOARD_IWILL_DK8S2 + Modified: trunk/src/mainboard/msi/ms9185/Kconfig =================================================================== --- trunk/src/mainboard/msi/ms9185/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/msi/ms9185/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -105,3 +105,14 @@ int default 11 depends on BOARD_MSI_MS9185 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_MSI_MS9185 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2b80 + depends on BOARD_MSI_MS9185 + Modified: trunk/src/mainboard/newisys/khepri/Kconfig =================================================================== --- trunk/src/mainboard/newisys/khepri/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/newisys/khepri/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -104,3 +104,14 @@ int default 11 depends on BOARD_NEWISYS_KHEPRI + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17c2 + depends on BOARD_NEWISYS_KHEPRI + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x10 + depends on BOARD_NEWISYS_KHEPRI + Modified: trunk/src/mainboard/sunw/ultra40/Kconfig =================================================================== --- trunk/src/mainboard/sunw/ultra40/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/sunw/ultra40/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -103,3 +103,14 @@ int default 11 depends on BOARD_SUNW_ULTRA40 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x108e + depends on BOARD_SUNW_ULTRA40 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x40 + depends on BOARD_SUNW_ULTRA40 + Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig =================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -110,3 +110,14 @@ int default 11 depends on BOARD_SUPERMICRO_H8DME + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_H8DME + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1511 + depends on BOARD_SUPERMICRO_H8DME + Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig =================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -109,3 +109,14 @@ int default 11 depends on BOARD_SUPERMICRO_H8DMR + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_H8DMR + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1511 + depends on BOARD_SUPERMICRO_H8DMR + Modified: trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig =================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/supermicro/x6dhr_ig/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -37,7 +37,7 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x6780 + default 0x5580 depends on BOARD_SUPERMICRO_X6DHR_IG config MAX_CPUS Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig =================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -37,7 +37,7 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x6780 + default 0x5580 depends on BOARD_SUPERMICRO_X6DHR_IG2 config MAX_CPUS Modified: trunk/src/mainboard/technexion/tim8690/Kconfig =================================================================== --- trunk/src/mainboard/technexion/tim8690/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/technexion/tim8690/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -102,3 +102,13 @@ int default 11 depends on BOARD_TECHNEXION_TIM8690 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_TECHNEXION_TIM8690 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3050 + depends on BOARD_TECHNEXION_TIM8690 Modified: trunk/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/src/mainboard/tyan/s1846/Options.lb 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s1846/Options.lb 2009-11-27 11:03:20 UTC (rev 4959) @@ -62,6 +62,7 @@ uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID default CONFIG_ROM_SIZE = 256 * 1024 default CONFIG_HAVE_FALLBACK_BOOT = 1 @@ -92,4 +93,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 end Modified: trunk/src/mainboard/tyan/s2735/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s2735/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s2735/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -62,3 +62,9 @@ int default 2 depends on BOARD_TYAN_S2735 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2735 + depends on BOARD_TYAN_S2735 + Modified: trunk/src/mainboard/tyan/s2850/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s2850/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s2850/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -59,3 +59,29 @@ int default 12 depends on BOARD_TYAN_S2850 + +config HT_CHAIN_UNITID_BASE + hex + default 1 + depends on BOARD_TYAN_S2850 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2850 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default y + depends on BOARD_TYAN_S2850 + +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + depends on BOARD_TYAN_S2850 + +config APIC_ID_OFFSET + hex + default 0x0 + depends on BOARD_TYAN_S2850 + Modified: trunk/src/mainboard/tyan/s2875/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s2875/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s2875/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -10,6 +10,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select IOAPIC config MAINBOARD_DIR string @@ -65,3 +66,29 @@ int default 13 depends on BOARD_TYAN_S2875 + +config HT_CHAIN_UNITID_BASE + hex + default 1 + depends on BOARD_TYAN_S2875 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_TYAN_S2875 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default y + depends on BOARD_TYAN_S2875 + +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + depends on BOARD_TYAN_S2875 + +config APIC_ID_OFFSET + hex + default 0x0 + depends on BOARD_TYAN_S2875 + Modified: trunk/src/mainboard/tyan/s2912/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s2912/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -139,7 +139,7 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x2b80 + default 0x2912 depends on BOARD_TYAN_S2912 config IRQ_SLOT_COUNT Modified: trunk/src/mainboard/tyan/s4880/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s4880/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s4880/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -104,3 +104,9 @@ int default 11 depends on BOARD_TYAN_S4880 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x4880 + depends on BOARD_TYAN_S4880 + Modified: trunk/src/mainboard/tyan/s4882/Kconfig =================================================================== --- trunk/src/mainboard/tyan/s4882/Kconfig 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/tyan/s4882/Kconfig 2009-11-27 11:03:20 UTC (rev 4959) @@ -104,3 +104,9 @@ int default 11 depends on BOARD_TYAN_S4882 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x4882 + depends on BOARD_TYAN_S4882 + Modified: trunk/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/src/mainboard/via/epia/Options.lb 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/via/epia/Options.lb 2009-11-27 11:03:20 UTC (rev 4959) @@ -49,6 +49,10 @@ uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 + default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate default CONFIG_TTYS0_BAUD=115200 Modified: trunk/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/src/mainboard/via/epia-cn/Options.lb 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/via/epia-cn/Options.lb 2009-11-27 11:03:20 UTC (rev 4959) @@ -64,7 +64,9 @@ uses CONFIG_TTYS0_BAUD uses CONFIG_VIDEO_MB uses CONFIG_IOAPIC +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_IOAPIC = 0 default CONFIG_VIDEO_MB = 32 Modified: trunk/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/src/mainboard/via/epia-m/Options.lb 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/via/epia-m/Options.lb 2009-11-27 11:03:20 UTC (rev 4959) @@ -42,7 +42,10 @@ uses CONFIG_PCI_ROM_RUN uses CONFIG_CONSOLE_VGA uses CONFIG_TTYS0_BAUD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 + ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE = 256*1024 Modified: trunk/src/mainboard/via/epia-n/Options.lb =================================================================== --- trunk/src/mainboard/via/epia-n/Options.lb 2009-11-26 14:03:25 UTC (rev 4958) +++ trunk/src/mainboard/via/epia-n/Options.lb 2009-11-27 11:03:20 UTC (rev 4959) @@ -70,7 +70,9 @@ uses CONFIG_COMPRESS uses CONFIG_EPIA_VT8237R_INIT uses CONFIG_HAVE_MAINBOARD_RESOURCES +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 default CONFIG_EPIA_VT8237R_INIT = 1 #default CONFIG_RAMTOP = 4 * 1024*1024 default CONFIG_ROM_SIZE = 512 * 1024

1 0

Re: [coreboot] [PATCH] Linux cannot bootable without old onboard pcidriver on RS690 system.
by Myles Watson 26 Nov '09

26 Nov '09

> I think this is not caused by RS690, but seems to be related > device-tree structure. > Because the stopped point of linux kernel is the bus scan stage. > Successful for RS690 tree, but halted at SB600's PCI bridge. It seems like Zheng is having trouble at a different point. Since you've gotten it to work with the onboard driver, could you send the complete logs with and without it? > I know it is not proper solution that add the old onboard pci driver, > but it is a temporary solution till we found the problem. Since it's a temporary solution, lets add it somewhere local. Thanks, Myles

3 3

[PATCH] CONFIG_DEBUG directive of x86emu.
by Yoo, Taik-Yon 26 Nov '09

26 Nov '09

x86emu module confuse compilation with CONFIG_DEBUG directive. This patch makes it with or without.

1 0

[PATCH] IRQ service is not returned back.
by Yoo, Taik-Yon 26 Nov '09

26 Nov '09

The basic IRQ handler that is serviced by x86emu module is not returned back to caller. So must be patched. -- jaagar

4 4

[commit] r4958 - trunk/util/msrtool
by svn＠coreboot.org 26 Nov '09

26 Nov '09

Author: stuge Date: 2009-11-26 15:03:25 +0100 (Thu, 26 Nov 2009) New Revision: 4958 Modified: trunk/util/msrtool/geodelx.c trunk/util/msrtool/k8.c Log: Remove commented out example MSR definitions Now there are definitions for actual MSRs that can be referenced instead. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/msrtool/geodelx.c =================================================================== --- trunk/util/msrtool/geodelx.c 2009-11-26 13:54:40 UTC (rev 4957) +++ trunk/util/msrtool/geodelx.c 2009-11-26 14:03:25 UTC (rev 4958) @@ -454,11 +454,5 @@ { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS }, { BITS_EOT } }}, -/* - { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", { - { 63, 64, RESERVED }, - { BITS_EOT } - }}, -*/ { MSR_EOT } }; Modified: trunk/util/msrtool/k8.c =================================================================== --- trunk/util/msrtool/k8.c 2009-11-26 13:54:40 UTC (rev 4957) +++ trunk/util/msrtool/k8.c 2009-11-26 14:03:25 UTC (rev 4958) @@ -355,12 +355,5 @@ { BITS_EOT } }}, -/* - { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", { - { 63, 64, RESERVED }, - { BITS_EOT } - }}, -*/ - { MSR_EOT } };

1 0

[commit] r4957 - trunk/util/msrtool
by svn＠coreboot.org 26 Nov '09

26 Nov '09

Author: stuge Date: 2009-11-26 14:54:40 +0100 (Thu, 26 Nov 2009) New Revision: 4957 Modified: trunk/util/msrtool/geodelx.c Log: Add the following GeodeLX memory controller MSRs 0x20000018 MC_CF07_DATA 0x20000019 MC_CF8F_DATA 0x2000001a MC_CF1017_DATA 0x2000001b MC_CFPERF_CNT1 0x2000001c MC_PERFCNT2 0x2000001d MC_CFCLK_DBUG Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Nathan Williams <nathan(a)traverse.com.au> Modified: trunk/util/msrtool/geodelx.c =================================================================== --- trunk/util/msrtool/geodelx.c 2009-11-25 08:35:59 UTC (rev 4956) +++ trunk/util/msrtool/geodelx.c 2009-11-26 13:54:40 UTC (rev 4957) @@ -25,6 +25,298 @@ } const struct msrdef geodelx_msrs[] = { + { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", { + { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, { + { MSR1(0), "Reserved" }, + { MSR1(1), "8 MB" }, + { MSR1(2), "16 MB" }, + { MSR1(3), "32 MB" }, + { MSR1(4), "64 MB" }, + { MSR1(5), "128 MB" }, + { MSR1(6), "256 MB" }, + { MSR1(7), "512 MB" }, + { MSR1(8), "1 GB" }, + { MSR1(9), "Reserved" }, + { MSR1(10), "Reserved" }, + { MSR1(11), "Reserved" }, + { MSR1(12), "Reserved" }, + { MSR1(13), "Reserved" }, + { MSR1(14), "Reserved" }, + { MSR1(15), "Reserved" }, + { BITVAL_EOT } + }}, + { 59, 3, RESERVED }, + { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, { + { MSR1(0), "1 Module bank" }, + { MSR1(1), "2 Module banks" }, + { BITVAL_EOT } + }}, + { 55, 3, RESERVED }, + { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, { + { MSR1(0), "2 Component banks" }, + { MSR1(1), "4 Component banks" }, + { BITVAL_EOT } + }}, + { 51, 1, RESERVED }, + { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, { + { MSR1(0), "1 KB" }, + { MSR1(1), "2 KB" }, + { MSR1(2), "4 KB" }, + { MSR1(3), "8 KB" }, + { MSR1(4), "16 KB" }, + { MSR1(5), "32 KB" }, + { MSR1(6), "Reserved" }, + { MSR1(7), "DIMM1 Not Installed" }, + { BITVAL_EOT } + }}, + { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, { + { MSR1(0), "Reserved" }, + { MSR1(1), "8 MB" }, + { MSR1(2), "16 MB" }, + { MSR1(3), "32 MB" }, + { MSR1(4), "64 MB" }, + { MSR1(5), "128 MB" }, + { MSR1(6), "256 MB" }, + { MSR1(7), "512 MB" }, + { MSR1(8), "1 GB" }, + { MSR1(9), "Reserved" }, + { MSR1(10), "Reserved" }, + { MSR1(11), "Reserved" }, + { MSR1(12), "Reserved" }, + { MSR1(13), "Reserved" }, + { MSR1(14), "Reserved" }, + { MSR1(15), "Reserved" }, + { BITVAL_EOT } + }}, + { 43, 3, RESERVED }, + { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, { + { MSR1(0), "1 Module bank" }, + { MSR1(1), "2 Module banks" }, + { BITVAL_EOT } + }}, + { 39, 3, RESERVED }, + { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, { + { MSR1(0), "2 Component banks" }, + { MSR1(1), "4 Component banks" }, + { BITVAL_EOT } + }}, + { 35, 1, RESERVED }, + { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, { + { MSR1(0), "1 KB" }, + { MSR1(1), "2 KB" }, + { MSR1(2), "4 KB" }, + { MSR1(3), "8 KB" }, + { MSR1(4), "16 KB" }, + { MSR1(5), "32 KB" }, + { MSR1(6), "Reserved" }, + { MSR1(7), "DIMM0 Not Installed" }, + { BITVAL_EOT } + }}, + { 31, 2, RESERVED }, + { 29, 2, "MSR_BA", "Mode Register Set Bank Address", PRESENT_BIN, { + { MSR1(0), "Program the DIMM Mode Register" }, + { MSR1(1), "Program the DIMM Extended Mode Register" }, + { MSR1(2), "Reserved" }, + { MSR1(3), "Reserved" }, + { BITVAL_EOT } + }}, + { 27, 1, "RST_DLL", "Mode Register Reset DLL", PRESENT_BIN, { + { MSR1(0), "Do not reset DLL" }, + { MSR1(1), "Reset DLL" }, + { BITVAL_EOT } + }}, + { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, { + { MSR1(0), "Enable" }, + { MSR1(1), "Disable" }, + { BITVAL_EOT } + }}, + { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, { + { MSR1(0), "Normal" }, + { MSR1(1), "Reduced" }, + { BITVAL_EOT } + }}, + { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, { + { MSR1(0), "Enable" }, + { MSR1(1), "Disable" }, + { BITVAL_EOT } + }}, + { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS }, + { 7, 4, "REF_STAG", "Refresh Staggering", PRESENT_DEC, NOBITS }, + { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS }, + { 2, 1, RESERVED }, + { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS }, + { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS }, + { BITS_EOT } + }}, + { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", { + { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS }, + { 55, 3, RESERVED }, + { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, { + { MSR1(0), "ADDR[18]" }, + { MSR1(1), "ADDR[19]" }, + { MSR1(2), "ADDR[20]" }, + { MSR1(3), "ADDR[21]" }, + { BITVAL_EOT } + }}, + { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 47, 6, RESERVED }, + { 41, 1, "TRUNC_DIS", "Burst Truncate Disable", PRESENT_BIN, { + { MSR1(0), "Bursts Enabled" }, + { MSR1(1), "Bursts Disabled" }, + { BITVAL_EOT } + }}, + { 40, 1, "REORDER_DIS", "Reorder Disable", PRESENT_BIN, { + { MSR1(0), "Reordering Enabled" }, + { MSR1(1), "Reordering Disabled" }, + { BITVAL_EOT } + }}, + { 39, 6, RESERVED }, + { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, { + { MSR1(0), "Low Order Interleave" }, + { MSR1(1), "High Order Interleave" }, + { BITVAL_EOT } + }}, + { 32, 1, RESERVED }, + { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS }, + { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, { + { MSR1(0), "Reserved" }, + { MSR1(1), "Reserved" }, + { MSR1(2), "2" }, + { MSR1(3), "3" }, + { MSR1(4), "4" }, + { MSR1(5), "1.5" }, + { MSR1(6), "2.5" }, + { MSR1(7), "3.5" }, + { BITVAL_EOT } + }}, + { 27, 4, "ACT2ACTREF", "ACT to ACT/REF Period. tRC", PRESENT_DEC, NOBITS }, + { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_DEC, NOBITS }, + { 19, 1, RESERVED }, + { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_DEC, NOBITS }, + { 15, 1, RESERVED }, + { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_DEC, NOBITS }, + { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_DEC, NOBITS }, + { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, { + { MSR1(0), "Invalid value" }, + { MSR1(1), "1" }, + { MSR1(2), "2" }, + { MSR1(3), "3" }, + { BITVAL_EOT } + }}, + { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, { + { MSR1(0), "Invalid value" }, + { MSR1(1), "1" }, + { MSR1(2), "2" }, + { MSR1(3), "3" }, + { BITVAL_EOT } + }}, + { 3, 4, RESERVED }, + { BITS_EOT } + }}, + { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0x11080001), "MC_CF1017_DATA", "Feature Enables", { + { 63, 34, RESERVED }, + { 29, 2, "WR_TO_RD", "Write to Read Delay. tWTR", PRESENT_DEC, NOBITS }, + { 27, 1, RESERVED }, + { 26, 3, "RD_TMG_CTL", "Read Timing Control", PRESENT_DEC, NOBITS }, + { 23, 3, RESERVED }, + { 20, 5, "REF2ACT", "Refresh to Activate Delay. tRFC", PRESENT_DEC, NOBITS }, + { 15, 8, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, NOBITS }, + { 7, 5, RESERVED }, + { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, { + { MSR1(0), "No delay" }, + { MSR1(1), "1-clock delay for unbuffered DIMMs" }, + { MSR1(2), "2-clock delay" }, + { MSR1(3), "Invalid value" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", { + { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS }, + { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS }, + { BITS_EOT } + }}, + { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", { + { 63, 28, RESERVED }, + { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, NOBITS }, + { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, NOBITS }, + { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, NOBITS }, + { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, NOBITS }, + { 31, 32, RESERVED }, + { BITS_EOT } + }}, + { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x1300), "MC_CFCLK_DBUG", "Clocking and Debug", { + { 63, 29, RESERVED }, + { 34, 1, "B2B_DIS", "Back-to-Back Command Disable", PRESENT_BIN, { + { MSR1(0), "Allow back-to-back commands" }, + { MSR1(1), "Disable back-to-back commands" }, + { BITVAL_EOT } + }}, + { 33, 1, "MTEST_RBEX_EN", "MTEST RBEX Enable", PRESENT_BIN, { + { MSR1(0), "Disable" }, + { MSR1(1), "Enable" }, + { BITVAL_EOT } + }}, + { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, { + { MSR1(0), "Disable" }, + { MSR1(1), "Enable" }, + { BITVAL_EOT } + }}, + { 31, 15, RESERVED }, + { 16, 1, "FORCE_PRE", "Force Precharge-all", PRESENT_BIN, { + { MSR1(0), "Disable" }, + { MSR1(1), "Enable" }, + { BITVAL_EOT } + }}, + { 15, 3, RESERVED }, + { 12, 1, "TRISTATE_DIS", "TRI-STATE Disable", PRESENT_BIN, { + { MSR1(0), "Tri-stating enabled" }, + { MSR1(1), "Tri-stating disabled" }, + { BITVAL_EOT } + }}, + { 11, 2, RESERVED }, + { 9, 1, "MASK_CKE1", "CKE1 Mask", PRESENT_BIN, { + { MSR1(0), "CKE1 output enable unmasked" }, + { MSR1(1), "CKE1 output enable masked" }, + { BITVAL_EOT } + }}, + { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, { + { MSR1(0), "CKE0 output enable unmasked" }, + { MSR1(1), "CKE0 output enable masked" }, + { BITVAL_EOT } + }}, + { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, { + { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" }, + { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" }, + { BITVAL_EOT } + }}, + { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, { + { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" }, + { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" }, + { BITVAL_EOT } + }}, + { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, { + { MSR1(0), "MA and BA output enable unmasked" }, + { MSR1(1), "MA and BA output enable masked" }, + { BITVAL_EOT } + }}, + { 4, 5, RESERVED }, + { BITS_EOT } + }}, { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", { { 63, 1, "EN", "Enable", PRESENT_DEC, { { MSR1(0), "Use default values" },

1 0

[PATCH] Seabios: Fix PkgLength calculation for the SSDT.
by Magnus Christensson 26 Nov '09

26 Nov '09

See attached patch. M.

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
24
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2009