coreboot October 2009

coreboot@coreboot.org

63 participants
534 discussions

[v2] r4723 - trunk/util/msrtool
by svn＠coreboot.org 05 Oct '09

05 Oct '09

Author: stepan Date: 2009-10-05 12:23:36 +0200 (Mon, 05 Oct 2009) New Revision: 4723 Modified: trunk/util/msrtool/darwin.c Log: fix building on Linux again, working around crude runtime OS detection. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/msrtool/darwin.c =================================================================== --- trunk/util/msrtool/darwin.c 2009-10-05 00:07:12 UTC (rev 4722) +++ trunk/util/msrtool/darwin.c 2009-10-05 10:23:36 UTC (rev 4723) @@ -37,11 +37,15 @@ int darwin_open(uint8_t cpu, enum SysModes mode) { +#ifdef __DARWIN__ if (cpu > 0) { fprintf(stderr, "%s: only core 0 is supported on Mac OS X right now.\n", __func__); return 0; } return 1; +#else + return 0; +#endif } int darwin_close(uint8_t cpu) @@ -51,6 +55,7 @@ int darwin_rdmsr(uint8_t cpu, uint32_t addr, struct msr *val) { +#ifdef __DARWIN__ msr_t msr; msr = rdmsr(addr); @@ -58,4 +63,7 @@ val->hi = msr.lo; val->lo = msr.hi; return 1; +#else + return 0; +#endif }

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USB stack issues
by Daniel Mack 05 Oct '09

05 Oct '09

When developing the OHCI stack, I stumbled over two things in the libpayload USB stack which I didn't want to leave unmentioned. 1. The MSC driver issues BULK messages to its devices with 0 bytes in length. That is, in fact, a vliad operation according to the USB standard, but mass storage devices dodn't like that and time out on such a request. The UHCI stack bails out in this case and returns success, and so does the OHCI stack currently. However, this is a hack. The real fix would be to not let the MSC driver issue these empty packets. 2. Calling usb_detach_device() makes Coreboot crash.I don't see how the OHCI stack could possibly cause that, so I blame the generic USB stack for that :) Daniel

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[PATCH] kconfig support for all GX1 boards
by Uwe Hermann 05 Oct '09

05 Oct '09

See patch. Build-tested, but not yet run-time-tested on any board. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Re: [coreboot] [Qemu-devel] Release plan for 0.12.0
by Carl-Daniel Hailfinger 05 Oct '09

05 Oct '09

On 04.10.2009 18:06, Natalia Portillo wrote: > > El 04/10/2009, a las 12:16, Carl-Daniel Hailfinger escribió: > >> Hi Natalia, >> >> I tried to understand your points. Please correct me where I'm wrong. >> >> On 04.10.2009 06:10, Natalia Portillo wrote: >>> EFI actually DOES HAVE ground. >>> >>> Itanium machines are still worldwide used, manufactured and sold. >> >> Unless I'm mistaken, Itanium is not x86. Now if we consider EFI for x86 >> because it has solid standing on Itanium, shouldn't we also consider >> U-Boot and OpenFirmware for x86 because they have solid standing on >> ARM/PowerPC? > EFI is used in x86 as well, contrary to OF. All OLPC laptops (which are x86) have OF. Not sure how many of them are already deployed, but I think it's roughly a million. (Side note: That OF implementation has a builtin BIOS emulator/CSM in newer versions to be able to boot Windows). >>> The disadvantages can be a lot. >>> The advantages that I see, are the following (implemented by Apple's >>> EFI): >>> Hardware drivers, so the OS loader can use ANY hardware present. >> >> Same for BIOS. > BIOS searches for them in ROM space. > No manufacturer ROM, no driver. EFI searches the drivers on disk, so it's like booting DOS from disk which has drivers. >>> Hardware testing easily programable, as you can use the EFI to call >>> the hardware (unlike PC diagnostics that makes direct and real mode >>> calls to the hardware, making them imposible to test different >>> hardware without implementing all variations -SCSI cards, wifi cards, >>> so on-) >> >> Same for BIOS (the only difference is that the interface to the BIOS >> provides a 16bit interface and EFI provides a 32bit interface). > Not only a 16 bit interface, REAL MODE interface. > Your driver can crash my driver easily. OK, now I'm intrigued. This implies that an EFI driver can not crash the OS easily. Given that programming bugs sometimes are really nasty, does the "not crashing easily" promise apply even if it deliberately tries to overwrite all of the physical RAM (such driver bugs have existed in the past, I even have a link somewhere). But that also means (if we ignore virtualization for a moment) that any OS using an EFI driver has to call the EFI driver in ring 3 because the calling the EFI driver in ring 0 would negate any memory protection. Is that really the case? >>> Filesystem independent bootloader (it just expects the EFI to have the >>> filesystem and disk driver, then searches the disk for the OS loader) >> >> Burn a BIOS together with DOS in the ROM and you get the same >> functionality. I have seen youtube videos of such systems. > DOS is not a filesystem independent bootloader. Neither is EFI. Linux and DOS and EFI can have file system drivers for various file systems. They all can execute binaries and those binaries can be bootloaders. Such bootloaders have the option of either using the existing VFS interface (to use a Linux term for the generic interface to file systems) or to implement their own file system drivers to search the various file systems on disk for bootable operating systems. loadlin is an example which uses the file system drivers present in DOS and (assuming that DOS has NTFS or ext2 drivers installed) fits your description of a file system independent bootloader. > And filesystem drivers for DOS are not drivers, hacks and traps to INT > 21h. Erm. Which filesystem driver for DOS is not hooking INT 21h? >>> Extensive input devices support (USB keyb and mice, bluetooth keyb and >>> mice and infrared remote) >> >> AFAIK USB keyboard+mouse is supported in pretty much every BIOS out >> there. Not sure about bluetooth keyboard and infrared remote, but the >> boards with builtin bluetooth support probably also have a bluetooth >> keyboard driver in the BIOS. > Take any of it, no support. > I know a couple of Asus and Abit motherboards with integrated Wifi and > Bluetooth. > > Yet to see wifi netboot in ANY wifi card with bios. > Seen EFI netboot in Apple wifis. Given that EFI loads these wifi drivers for netbooting from disk as per your earlier statement about on-disk EFI drivers, does that mean wifi netbooting breaks once you remove the disk? >> I don't understand what an EFI System Partition is used for. The >> wikipedia entry suggests that it is essentially a special partition >> where bootloaders live (instead of using a normal partition for that) >> and where EFI loads drivers and DOS/Windows PE commandline executables >> from. That sounds suspiciously like a DOS partition with NTLDR and >> loadlin. > The partition is empty by default. > EFI expects a directory structure and loads drivers from this > partition if present, without loading any bootloader. > That allows it to load a bootloader from an ext3 filesystem, a direct > ELF kernel from XFS, or a netboot updated driver for a WiMAX (for > example). Wikipedia says the EFI System Partition is a FAT variant. "load a bootloader" implies that the thing loading the bootloader is a bootloader as well. Such a construct is not uncommon, take a look at GRUB booting Windows where it just acts as a bootloader for the Windows bootloader. >>> A bootloader can fuckinly easy put a good splash without limiting to >>> 12 colors or making calls to the VGA system (for example). What will >>> happen with the GRUB if tomorrow VGA disappears? What a mess... >> >> I've seen quite a few GRUB installations with 24-bit color splash >> screens in high resolutions. Graphics hardware won't disappear from >> computers any time soon, only the interfaces may change. > So, say me how! What do you want to know? How to use 24-bit color for boot loader splash screens on systems with BIOS? I think there are patches floating around for GRUB and LILO, and some other bootloaders sport graphical interfaces by default. Or how to deal with systems that don't have a VGA realmode interface anymore? Such systems already exist (VIA EPIA has that option), and let me tell you that they run coreboot+Linux instead of EFI. >> Interesting. Do these boards still have a 20-30 second wait time from >> poweron to bootloader? I've seen coreboot+SeaBIOS achieve 1 second from >> poweron to bootloader on real x86 hardware, so I always wonder what the >> commercial BIOSes do during the time we wait for them. > Nope. The only "wait" is the normal Apple POST. Then the CSM takes 1 > or 2 seconds to load the OS. How long does the normal Apple POST take? Longer than a second? If yes, where does it spend that time? >> Many years ago, some EFI proponent told me: "EFI is great. It is a >> 32-bit BIOS with builtin 32-bit DOS. Now every operating system can use >> EFI drivers in compatibility mode like Windows 95 used DOS drivers in >> compatibility mode." >> That statement had a lasting impression on me and I've yet to see any >> explanation why that statement would be incorrect. I'm very willing to >> learn, so if I got something wrong, please educate me. > > EFI is not a 32-bit BIOS, it is a 32 or 64 bit protected mode hardware > initialization and booting interface. I see. Thanks for clarifying this. Looking at the wikipedia definition for operating systems, EFI fits that definition pretty well. It has drivers, hardware abstraction, and runs applications. There are good reasons to have full operating systems in the firmware. The programming model is easier, the environment is userfriendly, and if there are good recovery and diagnosis tools available for that operating system, you can simply reuse them. And since having an OS in the firmware is good, people have created systems which have coreboot+Linux in the firmware flash chip. Some variants with coreboot+Linux+KVM (the virtualization solution) and coreboot+Linux+busybox+X(Kdrive)+windowmanager(matchbox)+terminal(rxvt) are already out there. A boot demo video of the latter variant is here: http://www.youtube.com/watch?v=nuzRsXKm_NQ Of course, Linux can act as a boot loader as well (see kboot and petitboot and runnix), and I've heard of people using Linux in firmware to boot some Windows variant over Fibrechannel. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[v2] r4722 - in trunk/coreboot-v2/src/mainboard: a-trend/atc-6220 a-trend/atc-6240 abit/be6-ii_v2_0 asus/mew-am asus/mew-vm asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p3b-f azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p600 gigabyte/ga-6bxc gigabyte/m57sli mitac/6513wu msi/ms6119 msi/ms6147 msi/ms6178 nec/powermate2000 soyo/sy-6ba-plus-iii tyan/s1846
by svn＠coreboot.org 05 Oct '09

05 Oct '09

Author: uwe Date: 2009-10-05 02:07:12 +0200 (Mon, 05 Oct 2009) New Revision: 4722 Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig Log: PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig and should not be set in per-mainboard Kconfigs. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_SMSC_LPC47B272 select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -30,8 +30,6 @@ select SMP select IOAPIC select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -30,8 +30,6 @@ select SMP select IOAPIC select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -28,8 +28,6 @@ select SUPERIO_NSC_PC97317 select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -18,8 +18,6 @@ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select K8_REV_F_SUPPORT - select PCI_ROM_RUN - select CONSOLE_VGA select HAVE_FANCTL config MAINBOARD_DIR Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -27,8 +27,6 @@ select SUPERIO_ITE_IT8671F select HAVE_PIRQ_TABLE select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig 2009-10-04 23:50:06 UTC (rev 4721) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Kconfig 2009-10-05 00:07:12 UTC (rev 4722) @@ -26,8 +26,6 @@ select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_NSC_PC87309 select UDELAY_IO - select PCI_ROM_RUN - select CONSOLE_VGA config MAINBOARD_DIR string

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CBFS issues on 440BX boards
by Uwe Hermann 04 Oct '09

04 Oct '09

Uncompressing coreboot to RAM. Jumping to image. Check CBFS header at fffedfe0 magic is ffffffff ERROR: No valid CBFS header found! CBFS: Could not find file fallback/coreboot_ram Jumping to image. I can reproduce this on hardware on ASUS P2B-F and Biostar M6TBA, but I guess it happens on all 440BX boards, maybe also for other chipsets, didn't check yet. RAM init works ok (tested with ram_check()) so I think bad RAM init can be ruled out. Also, disabling HIGH TABLES didn't seem to improve anything here. Here's a sample CBFS output: ./coreboot.rom: 256 kB, bootblocksize 73728, romsize 262144, offset 0x0 Alignment: 64 bytes Name Offset Type Size normal/payload 0x0 payload 28850 normal/coreboot_ram 0x7100 stage 46897 fallback/payload 0x12880 payload 28850 fallback/coreboot_ram 0x19980 stage 46893 0x25100 null 36536 Not sure why it says "Check CBFS header at fffedfe0" as CBFS_HEADPTR_ADDR is defined as 0xFFFFFFFc... I'm thankful for any hints. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4721 - in trunk/coreboot-v2/src: mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/abit/be6-ii_v2_0 mainboard/asus/p2b mainboard/asus/p2b-d mainboard/asus/p2b-ds mainboard/asus/p2b-f mainboard/asus/p3b-f mainboard/azza/pt-6ibd mainboard/biostar/m6tba mainboard/compaq/deskpro_en_sff_p600 mainboard/gigabyte/ga-6bxc mainboard/msi/ms6119 mainboard/msi/ms6147 mainboard/soyo/sy-6ba-plus-iii mainboard/tyan/s1846 southbridge/intel/i82371eb
by svn＠coreboot.org 04 Oct '09

04 Oct '09

Author: uwe Date: 2009-10-05 01:50:06 +0200 (Mon, 05 Oct 2009) New Revision: 4721 Added: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c Log: The new CBFS based build system requires the whole ROM to be accessible in very early stages, otherwise the boot may hang like this because the CBFS headers cannot be found/accessed: Uncompressing coreboot to RAM. Jumping to image. Check CBFS header at fffedfe0 magic is ffffffff ERROR: No valid CBFS header found! CBFS: Could not find file fallback/coreboot_ram Jumping to image. This patch enables full ROM access on all 440BX boards right after the serial init (and before CBFS headers are parsed). Build-tested and runtime-tested on ASUS P2B-F. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -31,6 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -31,6 +31,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -59,6 +60,10 @@ console_init(); report_bist_failure(bist); enable_smbus(); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + /* dump_spd_registers(); */ sdram_set_registers(); sdram_set_spd_registers(); Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -61,6 +62,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/auto.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -30,6 +30,7 @@ #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" @@ -58,6 +59,10 @@ uart_init(); console_init(); report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + enable_smbus(); /* dump_spd_registers(); */ sdram_set_registers(); Added: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "i82371eb.h" + +static void i82371eb_enable_rom(device_t dev) +{ + u16 reg16; + + /* Enable access to the whole ROM, disable ROM write access. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= LOWER_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ + pci_write_config16(dev, XBCS, reg16); +} Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-10-04 18:55:40 UTC (rev 4720) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2009-10-04 23:50:06 UTC (rev 4721) @@ -35,14 +35,6 @@ /* Initialize the real time clock (RTC). */ rtc_init(0); - /* Enable access to all BIOS regions. */ - reg16 = pci_read_config16(dev, XBCS); - reg16 |= LOWER_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE_1MB; - reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ - pci_write_config16(dev, XBCS, reg16); - /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) * bus, which is a subset of ISA. We select the full ISA bus here.

1 0

AMD 690/SB600 ACPI bug?
by Carl-Daniel Hailfinger 04 Oct '09

04 Oct '09

Hi, I read through the AMD 690/SB600 ACPI code and saw that src/mainboard/amd/pistachio/acpi/dsdt.asl src/mainboard/amd/dbm690t/acpi/dsdt.asl src/mainboard/technexion/tim8690/acpi/dsdt.asl all read STB5 from PCIe config space and then use the result as address of the SATA BAR5 without any proper bitmasking. For non-prefetchable 32-bit memory BARs this is OK, but if the BAR is either 64-bit or prefetchable or not memory, accesses to BAR5 will be screwed up. Comments are appreciated. I think that SATA BAR5 is 32-bit no-prefetch memory, but since SATA does not work if I boot with 4 GB RAM, I'm pretty paranoid about everything related to 32/64 bit issues. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[PATCH] Kill dead code in Intel E7520 raminit_test
by Carl-Daniel Hailfinger 04 Oct '09

04 Oct '09

/src/northbridge/intel/e7520/raminit_test.c is _the_ file which caused the stongest WTF!?! reaction ever when I read it. If redefines pci_read_config*() and pci_write_config*() as simple memory accesses to a local array without _any_ side effects. Same for pci_locate_device() which essentially operates on the fake pci_read_config*(). Its rdmsr() function is hardcoded to return zero and wrmsr() is empty. It has fake SPD arrays which are ignored. spd_read_byte() accesses the fake SPD arrays, then the result of spd_read_byte is discarded. It messes with setjmp() and longjmp(), but basically only uses them to hlt() upon invalid parameters to log2(). It calls raminit_main() at least 1 times and at most 73 times. It uses AMD Athlon dualcore PCI BDF in sdram_initialize() although it is an Intel chipset. It writes to stdout and stderr. (Yes, really.) Looking at this file is like watching a mass freeway pile-up. It's horrible, but you can't stop looking. Fix the majority of WTFs. Can we just rip this file out? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c =================================================================== --- LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c (Revision 4591) +++ LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c (Arbeitskopie) @@ -14,112 +14,18 @@ return 0; } -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x07) << 8) | \ - ((WHERE) & 0xFF)) - #define PCI_DEV(BUS, DEV, FN) ( \ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x7) << 8)) -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - typedef unsigned device_t; -unsigned char pci_register[256*5*3*256]; - -static uint8_t pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return pci_register[addr]; -} - -static uint16_t pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return pci_register[addr] | (pci_register[addr + 1] << 8); -} - -static uint32_t pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - uint32_t value; - addr = dev | where; - value = pci_register[addr] | - (pci_register[addr + 1] << 8) | - (pci_register[addr + 2] << 16) | - (pci_register[addr + 3] << 24); - -#if 0 - print_debug("pcir32("); - print_debug_hex32(addr); - print_debug("):"); - print_debug_hex32(value); - print_debug("\n"); -#endif - return value; - -} - -static void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value; -} - -static void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value & 0xff; - pci_register[addr + 1] = (value >> 8) & 0xff; -} - -static void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value & 0xff; - pci_register[addr + 1] = (value >> 8) & 0xff; - pci_register[addr + 2] = (value >> 16) & 0xff; - pci_register[addr + 3] = (value >> 24) & 0xff; - -#if 0 - print_debug("pciw32("); - print_debug_hex32(addr); - print_debug(", "); - print_debug_hex32(value); - print_debug(")\n"); -#endif -} - -#define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - - - - static void uart_tx_byte(unsigned char data) { write(STDOUT_FILENO, &data, 1); } + static void hlt(void) { longjmp(end_buf, 2); @@ -144,161 +50,10 @@ return pow; } -typedef struct msr_struct -{ - unsigned lo; - unsigned hi; -} msr_t; - -static inline msr_t rdmsr(unsigned index) -{ - msr_t result; - result.lo = 0; - result.hi = 0; - return result; -} - -static inline void wrmsr(unsigned index, msr_t msr) -{ -} - #include "raminit.h" #define SIO_BASE 0x2e -static void hard_reset(void) -{ - /* FIXME implement the hard reset case... */ - longjmp(end_buf, 3); -} - -static void memreset_setup(void) -{ - /* Nothing to do */ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - /* Nothing to do */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - - -static uint8_t spd_mt4lsdt464a[256] = -{ - 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, - 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, - 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F, - - 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E, - 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04, - 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05, - 0x06, 0x07, 0x08, 0x09, 0x00, -}; - -static uint8_t spd_micron_512MB_DDR333[256] = -{ - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31, - 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, - 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; - -static uint8_t spd_micron_256MB_DDR333[256] = -{ - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36, - 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31, - 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -}; - -#define MAX_DIMMS 16 -static uint8_t spd_data[MAX_DIMMS*256]; - -static unsigned spd_count, spd_fail_count; -static int spd_read_byte(unsigned device, unsigned address) -{ - int result; - spd_count++; - if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) { - result = -1; - } - else { - device -= 0x50; - - if (address > 256) { - result = -1; - } - else if (spd_data[(device << 8) | 2] != 7) { - result = -1; - } - else { - result = spd_data[(device << 8) | address]; - } - } -#if 0 - print_debug("spd_read_byte("); - print_debug_hex32(device); - print_debug(", "); - print_debug_hex32(address); - print_debug(") -> "); - print_debug_hex32(result); - print_debug("\n"); -#endif - if (spd_count >= spd_fail_count) { - result = -1; - } - return result; -} - /* no specific code here. this should go away completely */ static void coherent_ht_mainboard(unsigned cpus) { @@ -341,62 +96,13 @@ #endif }; console_init(); - memreset_setup(); sdram_initialize(ARRAY_SIZE(cpu), cpu); } -static void reset_tests(void) -{ - /* Clear the results of any previous tests */ - memset(pci_register, 0, sizeof(pci_register)); - memset(spd_data, 0, sizeof(spd_data)); - spd_count = 0; - spd_fail_count = UINT_MAX; - - pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP, - NBCAP_128Bit | - NBCAP_MP| NBCAP_BIG_MP | - /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ - (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | - NBCAP_MEMCTRL); - - pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP, - NBCAP_128Bit | - NBCAP_MP| NBCAP_BIG_MP | - /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ - (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | - NBCAP_MEMCTRL); - -#if 0 - pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#endif -} - static void test1(void) { - reset_tests(); - - memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); -#if 0 - memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256); - - memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256); -#endif - raminit_main(); - -#if 0 - print_debug("spd_count: "); - print_debug_hex32(spd_count); - print_debug("\r\n"); -#endif - } @@ -407,16 +113,7 @@ if (setjmp(end_buf) != 0) { goto done; } - reset_tests(); - spd_fail_count = i; - print_debug("\r\nSPD will fail after: "); - print_debug_hex32(spd_fail_count); - print_debug(" accesses.\r\n"); - - memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); - raminit_main(); done: -- http://www.hailfinger.org/

3 2

[v2] r4720 - in trunk/coreboot-v2: src/arch/i386/lib src/config src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61 src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_
by svn＠coreboot.org 04 Oct '09

04 Oct '09

Author: oxygene Date: 2009-10-04 20:55:40 +0200 (Sun, 04 Oct 2009) New Revision: 4720 Modified: trunk/coreboot-v2/src/arch/i386/lib/failover.lds trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds trunk/coreboot-v2/src/arch/i386/lib/id.inc trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/config/failovercalculation.lb trunk/coreboot-v2/src/config/nofailovercalculation.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb trunk/coreboot-v2/src/mainboard/via/epia/Options.lb trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc trunk/coreboot-v2/src/southbridge/nvidia/mcp55/id.inc trunk/coreboot-v2/src/southbridge/sis/sis966/id.inc trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb trunk/coreboot-v2/targets/iwill/dk8x/Config.lb Log: This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE. Both were only really used in pre-cbfs, as the payload's size isn't relevant for the build process anymore. Various calculations in {no,}failovercalculation.lb are adapted accordingly. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/lib/failover.lds =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/failover.lds 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/arch/i386/lib/failover.lds 2009-10-04 18:55:40 UTC (rev 4720) @@ -1 +1 @@ - __normal_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8; + __normal_image = (CONFIG_ROMBASE & 0xfffffff0) - 8; Modified: trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/arch/i386/lib/failover_failover.lds 2009-10-04 18:55:40 UTC (rev 4720) @@ -1,2 +1,2 @@ - __fallback_image = (CONFIG_ROM_PAYLOAD_START & 0xfffffff0) - 8; - __normal_image = ((CONFIG_ROM_PAYLOAD_START - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8; + __fallback_image = (CONFIG_ROMBASE & 0xfffffff0) - 8; + __normal_image = ((CONFIG_ROMBASE - CONFIG_FALLBACK_SIZE) & 0xfffffff0) - 8; Modified: trunk/coreboot-v2/src/arch/i386/lib/id.inc =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/id.inc 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/arch/i386/lib/id.inc 2009-10-04 18:55:40 UTC (rev 4720) @@ -8,7 +8,7 @@ .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x10 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x10 - part /* Reverse offset to the part number */ -.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end __id_end: Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/config/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -246,14 +246,8 @@ export used comment "Default rom section offset" end -define CONFIG_PAYLOAD_SIZE - default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE} - format "0x%x" - export always - comment "Default payload size" -end define CONFIG_ROMBASE - default {CONFIG_PAYLOAD_SIZE} + default {0xffffffff - CONFIG_ROM_SIZE + 1} format "0x%x" export always comment "Base address of coreboot in ROM" @@ -646,12 +640,6 @@ export always comment "Boot image is located in ROM" end -define CONFIG_ROM_PAYLOAD_START - default {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1} - format "0x%x" - export always - comment "ROM stream start location" -end define CONFIG_COMPRESSED_PAYLOAD_NRV2B default 0 export always Modified: trunk/coreboot-v2/src/config/failovercalculation.lb =================================================================== --- trunk/coreboot-v2/src/config/failovercalculation.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/config/failovercalculation.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,16 +16,9 @@ end ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - -## ## Compute where this copy of coreboot will start in the boot rom ## -default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) +default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute a range of ROM that can cached to speed up coreboot, Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb =================================================================== --- trunk/coreboot-v2/src/config/nofailovercalculation.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/config/nofailovercalculation.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -11,16 +11,9 @@ end ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - -## ## Compute where this copy of coreboot will start in the boot rom ## -default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) +default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute a range of ROM that can cached to speed up coreboot, Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,8 +40,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,10 +20,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -23,10 +23,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -42,10 +42,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,8 +40,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,12 +17,10 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -41,10 +41,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -36,8 +36,6 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -36,8 +36,6 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,10 +20,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,8 +40,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,8 +40,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -41,10 +41,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -19,10 +19,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -21,10 +21,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -22,10 +22,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,10 +20,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -6,19 +6,12 @@ ## default CONFIG_ROM_SIZE = 256 * 1024 default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_ROM_SECTION_OFFSET = 0 +default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - -## ## Compute where this copy of coreboot will start in the boot rom ## -default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) +default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute a range of ROM that can cached to speed up coreboot, Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -24,8 +24,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -46,11 +46,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,11 +44,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -45,10 +45,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -5,16 +5,9 @@ default CONFIG_ROM_SIZE = 256 * 1024 ## -## Compute the start location and size size of -## The coreboot bootloader. -## -default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - -## ## Compute where this copy of coreboot will start in the boot rom ## -default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) +default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute a range of ROM that can cached to speed up coreboot, Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -25,8 +25,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,8 +20,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,12 +40,10 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/intel/eagleheights/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -48,11 +48,9 @@ uses CONFIG_ROM_SECTION_OFFSET # Payload uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE # Build Internals uses CONFIG_RAMBASE uses CONFIG_ROMBASE Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -34,9 +34,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -34,10 +34,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_LB_MEM_TOPK -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -46,10 +46,6 @@ #uses CONFIG_CPU_OPT uses CONFIG_IDE -## The default definitions are used for these -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE - ## These are defined in target Config.lb, don't add here uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -23,10 +23,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -41,10 +41,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -49,10 +49,8 @@ uses CONFIG_ROM_SECTION_OFFSET # Payload uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE # Build Internals uses CONFIG_RAMBASE uses CONFIG_ROMBASE Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,10 +20,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -42,12 +42,10 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -42,12 +42,10 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -37,13 +37,11 @@ uses CONFIG_MAINBOARD_VENDOR uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_OBJCOPY -uses CONFIG_PAYLOAD_SIZE uses CONFIG_PCI_ROM_RUN uses CONFIG_RAMBASE uses CONFIG_ROMBASE uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -42,9 +42,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,11 +40,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,10 +44,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -41,8 +41,6 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,11 +44,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,11 +40,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -26,7 +26,6 @@ uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_PCI_ROM_RUN uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_UDELAY_TSC uses CONFIG_VIDEO_MB @@ -48,7 +47,6 @@ uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_OBJCOPY -uses CONFIG_PAYLOAD_SIZE uses CONFIG_RAMBASE uses CONFIG_ROMBASE uses CONFIG_ROM_IMAGE_SIZE Modified: trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/soyo/sy-6ba-plus-iii/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,11 +44,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,11 +44,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,10 +44,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -16,10 +16,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,9 +40,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -22,10 +22,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,8 +40,6 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -26,7 +26,6 @@ uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_PCI_ROM_RUN uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_UDELAY_TSC uses CONFIG_VIDEO_MB @@ -48,7 +47,6 @@ uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_OBJCOPY -uses CONFIG_PAYLOAD_SIZE uses CONFIG_RAMBASE uses CONFIG_ROMBASE uses CONFIG_ROM_IMAGE_SIZE Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -19,10 +19,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,10 +20,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,11 +44,9 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -44,10 +44,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -17,10 +17,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -29,10 +29,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -41,10 +41,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -20,11 +20,9 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -40,10 +40,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -43,10 +43,8 @@ uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE @@ -96,9 +94,7 @@ default CONFIG_HAVE_ACPI_TABLES = 1 default CONFIG_HAVE_OPTION_TABLE = 1 #default CONFIG_ROM_IMAGE_SIZE = 67 * 1024 -#default CONFIG_PAYLOAD_SIZE = 125 * 1024 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 -default CONFIG_PAYLOAD_SIZE = 256 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_USE_FALLBACK_IMAGE = 1 default CONFIG_STACK_SIZE = 8 * 1024 Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -42,10 +42,8 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE uses CONFIG_XIP_ROM_SIZE Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -46,10 +46,8 @@ uses CONFIG_COMPRESS uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_RAMBASE Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc 2009-10-04 18:55:40 UTC (rev 4720) @@ -8,7 +8,7 @@ .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor ID */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this ROM image */ +.long CONFIG_ROM_SIZE /* Size of this ROM image */ .globl __id_end __id_end: Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/id.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/id.inc 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/id.inc 2009-10-04 18:55:40 UTC (rev 4720) @@ -29,7 +29,7 @@ .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end __id_end: Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/id.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/id.inc 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/id.inc 2009-10-04 18:55:40 UTC (rev 4720) @@ -29,7 +29,7 @@ .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ -.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end __id_end: Modified: trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb =================================================================== --- trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/targets/arima/hdama/Config.kernelimage.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -10,7 +10,6 @@ uses CONFIG_COMPRESS uses CONFIG_IOAPIC uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_UDELAY_TSC uses CPU_FIXUP uses CONFIG_HAVE_FALLBACK_BOOT @@ -29,7 +28,6 @@ uses CONFIG_SMP uses CONFIG_MAX_CPUS uses CONFIG_MEMORY_HOLE -uses CONFIG_PAYLOAD_SIZE uses CONFIG_RAMBASE uses CONFIG_ROMBASE uses CONFIG_ROM_IMAGE_SIZE Modified: trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/targets/iwill/dk8s2/Config.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -133,10 +133,6 @@ option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) option CONFIG_ROM_SECTION_OFFSET= 0 - option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) - # option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE option CONFIG_XIP_ROM_SIZE = 65536 @@ -152,10 +148,6 @@ option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) - option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) - # option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE option CONFIG_XIP_ROM_SIZE = 65536 option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE) Modified: trunk/coreboot-v2/targets/iwill/dk8x/Config.lb =================================================================== --- trunk/coreboot-v2/targets/iwill/dk8x/Config.lb 2009-10-04 17:15:39 UTC (rev 4719) +++ trunk/coreboot-v2/targets/iwill/dk8x/Config.lb 2009-10-04 18:55:40 UTC (rev 4720) @@ -133,10 +133,6 @@ option CONFIG_ROM_SECTION_SIZE = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) option CONFIG_ROM_SECTION_OFFSET= 0 - option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) - # option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE option CONFIG_XIP_ROM_SIZE = 65536 @@ -152,10 +148,6 @@ option CONFIG_ROM_SECTION_SIZE = CONFIG_FALLBACK_SIZE option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE) - option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) - option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) - option CONFIG_ROMBASE = (CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE) - # option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE option CONFIG_XIP_ROM_SIZE = 65536 option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)

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coreboot October 2009