coreboot October 2009

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Re: [coreboot] [v2] r4735 - in trunk/coreboot-v2/src/mainboard:amd/serengeti_cheetah intel/xe7501devkit msi/ms7135msi/ms9185 newisys/khepri sunw/ultra40 supermicro/h8dmetyan/s2881 tyan/s2891 tyan/s2892 tyan/s2895 via/epia-n
by Myles Watson 07 Oct '09

07 Oct '09

> -----Original Message----- > From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] > Author: uwe > Date: 2009-10-07 18:29:12 +0200 (Wed, 07 Oct 2009) > New Revision: 4735 > Convert all "default y" options to "select FOO" (shorter). I think cosmetic cleanups like this ought to wait until all boards are supported since Patrick is moving so quickly. I think it would be easy to break boards that are working. > Also, drop per-board CONSOLE_VGA/PCI_ROM_RUN while I'm at it, they're > global options in kconfig. I agree. > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Thanks, Myles

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[v2] r4735 - in trunk/coreboot-v2/src/mainboard: amd/serengeti_cheetah intel/xe7501devkit msi/ms7135 msi/ms9185 newisys/khepri sunw/ultra40 supermicro/h8dme tyan/s2881 tyan/s2891 tyan/s2892 tyan/s2895 via/epia-n
by svn＠coreboot.org 07 Oct '09

07 Oct '09

Author: uwe Date: 2009-10-07 18:29:12 +0200 (Wed, 07 Oct 2009) New Revision: 4735 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig Log: Convert all "default y" options to "select FOO" (shorter). Also, drop per-board CONSOLE_VGA/PCI_ROM_RUN while I'm at it, they're global options in kconfig. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -11,6 +11,12 @@ select HAVE_PIRQ_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select MEM_TRAIN_SEQ + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT config MAINBOARD_DIR string @@ -37,16 +43,6 @@ default 0x8 depends on BOARD_AMD_SERENGETI_CHEETAH -config HAVE_HARD_RESET - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - -config IOAPIC - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - config LB_CKS_RANGE_END int default 122 @@ -67,11 +63,6 @@ default 0x100000 depends on BOARD_AMD_SERENGETI_CHEETAH -config MEM_TRAIN_SEQ - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - config MAX_CPUS int default 8 @@ -82,26 +73,11 @@ default 4 depends on BOARD_AMD_SERENGETI_CHEETAH -config MEM_TRAIN_SEQ - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - config HW_MEM_HOLE_SIZE_AUTO_INC bool default n depends on BOARD_AMD_SERENGETI_CHEETAH -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - config SB_HT_CHAIN_ON_BUS0 int default 2 @@ -127,26 +103,6 @@ default n depends on BOARD_AMD_SERENGETI_CHEETAH -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - -config WAIT_BEFORE_CPUS_INIT - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - -config CONSOLE_VGA - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - -config PCI_ROM_RUN - bool - default y - depends on BOARD_AMD_SERENGETI_CHEETAH - config IRQ_SLOT_COUNT int default 11 Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -8,6 +8,7 @@ select SUPERIO_SMSC_LPC47B272 select HAVE_PIRQ_TABLE select UDELAY_TSC + select HAVE_OPTION_TABLE config MAINBOARD_DIR string @@ -34,11 +35,6 @@ default "EIDXE7501DEVKIT" depends on BOARD_INTEL_XE7501DEVKIT -config HAVE_OPTION_TABLE - bool - default y - depends on BOARD_INTEL_XE7501DEVKIT - config IRQ_SLOT_COUNT int default 12 Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -10,6 +10,8 @@ select PIRQ_TABLE select USE_DCACHE_RAM select USE_PRINTK_IN_CAR + select SERIAL_CPU_INIT + select AP_CODE_IN_CAR config MAINBOARD_DIR string @@ -96,16 +98,6 @@ default n depends on BOARD_MSI_MS7135 -config SERIAL_CPU_INIT - bool - default y - depends on BOARD_MSI_MS7135 - -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_MSI_MS7135 - config WAIT_BEFORE_CPUS_INIT bool default n Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -11,6 +11,8 @@ select HAVE_PIRQ_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC config MAINBOARD_DIR string @@ -37,16 +39,6 @@ default 0x10 depends on BOARD_MSI_MS9185 -config HAVE_HARD_RESET - bool - default y - depends on BOARD_MSI_MS9185 - -config IOAPIC - bool - default y - depends on BOARD_MSI_MS9185 - config SB_HT_CHAIN_ON_BUS0 int default 2 @@ -107,16 +99,6 @@ default 2 depends on BOARD_MSI_MS9185 -config CONSOLE_VGA - bool - default y - depends on BOARD_MSI_MS9185 - -config PCI_ROM_RUN - bool - default y - depends on BOARD_MSI_MS9185 - config IRQ_SLOT_COUNT int default 11 Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -11,6 +11,8 @@ select HAVE_PIRQ_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC config MAINBOARD_DIR string @@ -32,16 +34,6 @@ default 0x10 depends on BOARD_NEWISYS_KHEPRI -config HAVE_HARD_RESET - bool - default y - depends on BOARD_NEWISYS_KHEPRI - -config IOAPIC - bool - default y - depends on BOARD_NEWISYS_KHEPRI - config K8_REV_F_SUPPORT bool default n @@ -107,16 +99,6 @@ default 2 depends on BOARD_NEWISYS_KHEPRI -config CONSOLE_VGA - bool - default y - depends on BOARD_NEWISYS_KHEPRI - -config PCI_ROM_RUN - bool - default y - depends on BOARD_NEWISYS_KHEPRI - config IRQ_SLOT_COUNT int default 11 Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -10,6 +10,8 @@ select HAVE_PIRQ_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC config MAINBOARD_DIR string @@ -31,16 +33,6 @@ default 0x10 depends on BOARD_SUNW_ULTRA40 -config HAVE_HARD_RESET - bool - default y - depends on BOARD_SUNW_ULTRA40 - -config IOAPIC - bool - default y - depends on BOARD_SUNW_ULTRA40 - config K8_REV_F_SUPPORT bool default n @@ -106,16 +98,6 @@ default 2 depends on BOARD_SUNW_ULTRA40 -config CONSOLE_VGA - bool - default y - depends on BOARD_SUNW_ULTRA40 - -config PCI_ROM_RUN - bool - default y - depends on BOARD_SUNW_ULTRA40 - config IRQ_SLOT_COUNT int default 11 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -10,6 +10,8 @@ select HAVE_PIRQ_TABLE select USE_PRINTK_IN_CAR select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC config MAINBOARD_DIR string @@ -36,16 +38,6 @@ default 0x10 depends on BOARD_SUPERMICRO_H8DME -config HAVE_HARD_RESET - bool - default y - depends on BOARD_SUPERMICRO_H8DME - -config IOAPIC - bool - default y - depends on BOARD_SUPERMICRO_H8DME - config SB_HT_CHAIN_ON_BUS0 int default 2 @@ -106,16 +98,6 @@ default 2 depends on BOARD_SUPERMICRO_H8DME -config CONSOLE_VGA - bool - default y - depends on BOARD_SUPERMICRO_H8DME - -config PCI_ROM_RUN - bool - default y - depends on BOARD_SUPERMICRO_H8DME - config IRQ_SLOT_COUNT int default 11 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -9,6 +9,8 @@ select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF select PIRQ_TABLE + select SERIAL_CPU_INIT + select AP_CODE_IN_CAR config MAINBOARD_DIR string @@ -95,16 +97,6 @@ default n depends on BOARD_TYAN_S2881 -config SERIAL_CPU_INIT - bool - default y - depends on BOARD_TYAN_S2881 - -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_TYAN_S2881 - config WAIT_BEFORE_CPUS_INIT bool default n Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -9,6 +9,8 @@ select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF select PIRQ_TABLE + select SERIAL_CPU_INIT + select AP_CODE_IN_CAR config MAINBOARD_DIR string @@ -95,16 +97,6 @@ default n depends on BOARD_TYAN_S2891 -config SERIAL_CPU_INIT - bool - default y - depends on BOARD_TYAN_S2891 - -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_TYAN_S2891 - config WAIT_BEFORE_CPUS_INIT bool default n @@ -120,6 +112,7 @@ default n depends on BOARD_TYAN_S2891 +# TODO: Should be "select". And not user-visible. config HAVE_ACPI_TABLES bool "Generate ACPI tables" default y Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -9,6 +9,8 @@ select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_WINBOND_W83627HF select PIRQ_TABLE + select SERIAL_CPU_INIT + select AP_CODE_IN_CAR config MAINBOARD_DIR string @@ -95,16 +97,6 @@ default n depends on BOARD_TYAN_S2892 -config SERIAL_CPU_INIT - bool - default y - depends on BOARD_TYAN_S2892 - -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_TYAN_S2892 - config WAIT_BEFORE_CPUS_INIT bool default n @@ -120,6 +112,7 @@ default n depends on BOARD_TYAN_S2892 +# TODO config HAVE_ACPI_TABLES bool "Generate ACPI tables" default y Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -9,6 +9,8 @@ select SOUTHBRIDGE_AMD_AMD8131 select SUPERIO_SMSC_LPC47B397 select PIRQ_TABLE + select SERIAL_CPU_INIT + select AP_CODE_IN_CAR config MAINBOARD_DIR string @@ -95,16 +97,6 @@ default n depends on BOARD_TYAN_S2895 -config SERIAL_CPU_INIT - bool - default y - depends on BOARD_TYAN_S2895 - -config AP_CODE_IN_CAR - bool - default y - depends on BOARD_TYAN_S2895 - config WAIT_BEFORE_CPUS_INIT bool default n @@ -120,6 +112,7 @@ default n depends on BOARD_TYAN_S2895 +# TODO config HAVE_ACPI_TABLES bool "Generate ACPI tables" default y Modified: trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) +++ trunk/coreboot-v2/src/mainboard/via/epia-n/Kconfig 2009-10-07 16:29:12 UTC (rev 4735) @@ -6,6 +6,7 @@ select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_WINBOND_W83697HF select HAVE_PIRQ_TABLE + select EPIA_VT8237R_INIT config MAINBOARD_DIR string @@ -42,7 +43,3 @@ default 7 depends on BOARD_VIA_EPIA_N -config EPIA_VT8237R_INIT - bool - default y - depends on BOARD_VIA_EPIA_N

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[v2] r4734 - in trunk/coreboot-v2/src: . arch/i386 arch/ppc console devices mainboard
by svn＠coreboot.org 07 Oct '09

07 Oct '09

Author: uwe Date: 2009-10-07 18:15:40 +0200 (Wed, 07 Oct 2009) New Revision: 4734 Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/arch/i386/Kconfig trunk/coreboot-v2/src/arch/ppc/Kconfig trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/devices/Kconfig trunk/coreboot-v2/src/mainboard/Kconfig Log: Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) +++ trunk/coreboot-v2/src/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) @@ -30,10 +30,15 @@ menu "General setup" config LOCALVERSION - string "Local version - append to coreboot release" + string "Local version string" help Append an extra string to the end of the coreboot version. + This can be useful if, for instance, you want to append the + respective board's hostname or some other identifying string to + the coreboot version number, so that you can easily distinguish + boot logs of different boards from each other. + endmenu source src/mainboard/Kconfig @@ -225,10 +230,10 @@ # TODO # menu "Drivers" -# +# # endmenu -menu "Generated System Tables" +menu "System tables" config HAVE_LOW_TABLES bool @@ -239,7 +244,7 @@ default y config MULTIBOOT - bool "Add Multiboot tables (for grub2)" + bool "Generate Multiboot tables (for GRUB2)" default n config HAVE_ACPI_TABLES @@ -258,16 +263,22 @@ menu "Payload" -config COMPRESSED_PAYLOAD_LZMA - bool "Use LZMA compression for payloads" - default yes - choice - prompt "Payload type" + prompt "Add a payload" default PAYLOAD_NONE +config PAYLOAD_NONE + bool "None" + help + Select this option if you want to create an "empty" coreboot + ROM image for a certain mainboard, i.e. a coreboot ROM image + which does not yet contain a payload. + + For such an image to be useful, you have to use 'cbfstool' + to add a payload to the ROM image later. + config PAYLOAD_ELF - bool "An ELF executable payload file" + bool "An ELF executable payload" help Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware @@ -275,16 +286,7 @@ You will be able to specify the location and file name of the payload image later. -config PAYLOAD_NONE - bool "No payload" - help - Select this option if you want to create an "empty" coreboot - ROM image for a certain mainboard, i.e. a coreboot ROM image - which does not yet contain a payload. - For such an image to be useful, you have to use the 'cbfs' tool - to add a payload to the ROM image later. - endchoice config FALLBACK_PAYLOAD_FILE @@ -294,6 +296,15 @@ help The path and filename of the ELF executable file to use as payload. +# TODO: Defined if no payload? Breaks build? +config COMPRESSED_PAYLOAD_LZMA + bool "Use LZMA compression for payloads" + default y + depends on PAYLOAD_ELF + help + In order to reduce the size payloads take up in the ROM chip + coreboot can compress them using the LZMA algorithm. + endmenu menu "VGA BIOS" @@ -319,11 +330,20 @@ depends on VGA_BIOS default "1106,3230" help - The ID that would associate your VGA BIOS to your video card. - (PCI VendorID, PCI Device ID) + The comma-separated PCI vendor and device ID that would associate + your VGA BIOS to your video card. + Example: 1106,3230 + + In the above example 1106 is the PCI vendor ID (in hex, but without + the "0x" prefix) and 3230 specifies the PCI device ID of the + video card (also in hex, without "0x" prefix). + endmenu +menu "Debugging" + +# TODO: Better help text and detailed instructions. config GDB_STUB bool "GDB debugging support" default y @@ -331,3 +351,5 @@ If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/i386/lib/c_start.S for details. +endmenu + Modified: trunk/coreboot-v2/src/arch/i386/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/i386/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) +++ trunk/coreboot-v2/src/arch/i386/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) @@ -1,23 +1,22 @@ +# This option is used to set the architecture of a mainboard to X86. +# It is usually set in mainboard/*/Kconfig. config ARCH_X86 bool - help - This option is used to set the architecture of a mainboard. - It is usually set in mainboard/*/Kconfig. + default n +# This is an SMP option. It relates to starting up APs. +# It is usually set in mainboard/*/Kconfig. +# TODO: Improve description. config AP_IN_SIPI_WAIT bool default n depends on ARCH_X86 - help - This is an SMP option. It relates to starting up APs. - It is usually set in mainboard/*/Kconfig. +# This is the name of the respective architecture subdirectory in arch/. config ARCH string default i386 depends on ARCH_X86 - help - This is the name of the respective subdirectory in arch/. config ROMBASE hex @@ -58,11 +57,9 @@ hex default 0x8000 -menu "Misc options" - +# Maximum reboot count +# TODO: Improve description. config MAX_REBOOT_CNT - int "Maximum reboot count" + int default 3 -endmenu - Modified: trunk/coreboot-v2/src/arch/ppc/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/ppc/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) +++ trunk/coreboot-v2/src/arch/ppc/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) @@ -1,13 +1,12 @@ +# This option is used to set the architecture of a mainboard to PowerPC. +# It is usually set in mainboard/*/Kconfig. config ARCH_POWERPC bool - help - This option is used to set the architecture of a mainboard. - It is usually set in mainboard/*/Kconfig. + default n +# This is the name of the respective architecture subdirectory in arch/. config ARCH string default ppc depends on ARCH_POWERPC - help - This is the name of the respective subdirectory in arch/. Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) +++ trunk/coreboot-v2/src/console/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) @@ -1,53 +1,96 @@ menu "Console options" +# TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete. config CONSOLE_SERIAL8250 - #TODO Rename to SERIAL_CONSOLE once Kconfig transition is complete. - bool "See output on the serial port console" + bool "Enable serial port console output" default y + help + Send coreboot debug output to a serial port console. -config SERIAL_POST - bool "See POST output on the serial port console" - default n - +# TODO: COM1, COM2 etc. config TTYS0_BASE hex "I/O base for the serial port" depends on CONSOLE_SERIAL8250 default 0x3f8 config SERIAL_SET_SPEED - bool "Override the serial console BAUD rate" + bool "Override the serial port BAUD rate" default y depends on CONSOLE_SERIAL8250 config TTYS0_BAUD - int "Serial console BAUD rate" + int "Serial port BAUD rate" depends on SERIAL_SET_SPEED default 115200 +# TODO: Allow user-friendly selection of settings other than 8n1. config TTYS0_LCS int default 3 depends on CONSOLE_SERIAL8250 +config SERIAL_POST + bool "Enable POST output on the serial port console" + depends on CONSOLE_SERIAL8250 + default n + help + If enabled, coreboot will additionally print POST codes (which are + usually displayed using a so-called "POST card" ISA/PCI/PCI-E + device) on the serial console. + +# TODO: FIX DEPENDENCY HERE config USBDEBUG_DIRECT - bool "USB debug dongle support. Not supported on all chipsets." + bool "USB 2.0 EHCI debug dongle support" default n - # TODO: FIX DEPENDENCY HERE + help + This option allows you to use a so-called USB EHCI Debug device + to retrieve the coreboot debug messages (instead, or in addition + to, a serial port). + This feature is NOT supported on all chipsets in coreboot! + + It also requires a USB2 controller which supports the EHCI + Debug Port capability. Controllers which are known to work: + + * 10b9:5239 ALi Corporation USB 2.0 (USB PCI card) + * 8086:24cd Intel ICH4/ICH4-M + * 8086:24dd Intel ICH5 + * 8086:265c Intel ICH6 + * 8086:268c Intel 631xESB/632xESB/3100 + * 8086:27cc Intel ICH7 + * 8086:2836 Intel ICH8 + * 8086:283a Intel ICH8 + * 8086:293a Intel ICH9 + * 10de:0088 NVIDIA MCP2A + * 10de:005b NVIDIA CK804 + * 10de:026e NVIDIA MCP51 + * 10de:036d NVIDIA MCP55 + * 10de:03f2 NVIDIA MCP61 + * 1002:4386 ATI/AMD SB600 + * 1106:3104 VIA VX800 + + See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list. + config CONSOLE_VGA - bool "Use VGA console, once initialized." + bool "Use VGA console once initialized" default n +# TODO: Deps? +# TODO: Improve description. config CONSOLE_VGA_ONBOARD_AT_FIRST - bool "Use onboard VGA as primary" + bool "Use onboard VGA as primary video device" default n help If not selected, the last adapter found will be used. +# TODO: User-friendly "choice" selection. +# TODO: Add help text. config MAXIMUM_CONSOLE_LOGLEVEL int "Maximum console loglevel" default 9 +# TODO: User-friendly "choice" selection. +# TODO: Add help text. config DEFAULT_CONSOLE_LOGLEVEL int "Default console loglevel" default 9 Modified: trunk/coreboot-v2/src/devices/Kconfig =================================================================== --- trunk/coreboot-v2/src/devices/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) +++ trunk/coreboot-v2/src/devices/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) @@ -24,43 +24,58 @@ bool "Setup bridges on path to VGA adapter" default y help - Allow bridges to set up legacy decoding ranges for VGA. Don't disable + Allow bridges to set up legacy decoding ranges for VGA. Don't disable this unless you're sure you don't want the briges setup for VGA. +# TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN - bool "Run VGA Option ROMs" + bool "Run VGA option ROMs" + default y help - Execute VGA option ROMs if found. This is required to enable PCI/AGP - VGA plugin cards. + Execute VGA option ROMs, if found. This is required to enable + PCI/AGP/PCI-E video cards. config PCI_ROM_RUN - bool "Run non-VGA Option ROMs" + bool "Run non-VGA option ROMs" + default y help - Execute non-VGA PCI option ROMs if found. + Execute non-VGA PCI option ROMs, if found. + Examples include IDE/SATA controller option ROMs and option ROMs + for network cards (NICs). + +# TODO: Describe YABEL vs. x86emu differences in more detail. choice - prompt "Option ROM Execution" - default PCI_OPTION_ROM_RUN_REALMODE + prompt "Option ROM execution type" + default PCI_OPTION_ROM_RUN_REALMODE depends on PCI_ROM_RUN || VGA_ROM_RUN + +config PCI_OPTION_ROM_RUN_REALMODE + prompt "Real mode" + bool help - You can choose to execute PCI option ROMs natively (32bit x86 system - required) or in an emulator (x86emu or YABEL). + If you select this option, PCI option ROMs will be executed + natively on the hardware (a 32bit x86 system is required). - config PCI_OPTION_ROM_RUN_REALMODE - prompt "Real mode" - bool +config PCI_OPTION_ROM_RUN_YABEL + prompt "YABEL" + bool + help + If you select this option, the YABEL BIOS emulator will be used to + execute PCI option ROMs. - config PCI_OPTION_ROM_RUN_YABEL - prompt "YABEL" - bool +config PCI_OPTION_ROM_RUN_X86EMU + prompt "x86emu" + bool + help + If you select this option, the x86emu BIOS emulator will be used to + execute PCI option ROMs. - config PCI_OPTION_ROM_RUN_X86EMU - prompt "X86EMU" - bool endchoice +# TODO: Describe better, and/or make a "choice" selection for this. config YABEL_DEBUG_FLAGS - prompt "Hex value for debug flags" + prompt "Hex value for YABEL debug flags" hex default 0x0 depends on PCI_OPTION_ROM_RUN_YABEL Modified: trunk/coreboot-v2/src/mainboard/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) +++ trunk/coreboot-v2/src/mainboard/Kconfig 2009-10-07 16:15:40 UTC (rev 4734) @@ -370,10 +370,16 @@ source "src/mainboard/tyan/Kconfig" source "src/mainboard/via/Kconfig" +# TODO: No help text possible for choice fields? choice prompt "ROM chip size" default COREBOOT_ROMSIZE_KB_256 + help + Select the size of the ROM chip you intend to flash coreboot on. + The build system will take care of creating a coreboot.rom file + of the matching size. + config COREBOOT_ROMSIZE_KB_128 bool "128 KB" help @@ -406,6 +412,7 @@ endchoice +# Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int default 128 if COREBOOT_ROMSIZE_KB_128 @@ -414,9 +421,8 @@ default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 - help - Map the config names to an integer. +# Map the config names to a hex value (bytes). config ROM_SIZE hex default 0x20000 if COREBOOT_ROMSIZE_KB_128

1 0

Tyan S2912 (Fam10)
by Maximilian Thuermer 07 Oct '09

07 Oct '09

Hi all, seems as if the switch to CBFS has broken the Tyan S2912 boards. It reports that CONFIG_XIP_ROM_BASE needs to be a multiple of CONFIG_XIP_ROM_SIZE. The fix in failovercalculation.ld seems to be pretty straight forward, however after having read some posts on the mailing list, it seemed to me as if the whole Config.lb scheme of those boards are outdated (they still contain the failover sections in contrast to CBFS being incompatible with this). In addition to this, the boot process of fixed boards (with failover still enabled) hangs after finishing CAR which seems to fit into the picture (sorry, no log attached). Does anyone have a thought on this? Thanks a bunch, Maximilian Thuermer

2 1

[v2] r4733 - in trunk/coreboot-v2/src/mainboard/intel: jarrell xe7501devkit
by svn＠coreboot.org 07 Oct '09

07 Oct '09

Author: oxygene Date: 2009-10-07 18:00:40 +0200 (Wed, 07 Oct 2009) New Revision: 4733 Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig Log: Fix intel board build on kconfig. MAX_CPUS was missing Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) @@ -29,3 +29,12 @@ default "Jarrell" depends on BOARD_INTEL_JARRELL +config MAX_CPUS + int + default 4 + depends on BOARD_INTEL_JARRELL + +config IRQ_SLOT_COUNT + int + default 9 + depends on BOARD_INTEL_JARRELL Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Kconfig 2009-10-07 16:00:40 UTC (rev 4733) @@ -43,3 +43,13 @@ int default 12 depends on BOARD_INTEL_XE7501DEVKIT + +config MAX_CPUS + int + default 2 + depends on BOARD_INTEL_XE7501DEVKIT + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_INTEL_XE7501DEVKIT

1 0

[PATCH]kconfig: fix intel boards
by Patrick Georgi 07 Oct '09

07 Oct '09

Hi, intel/jarrell and and intel/xe7501devkit didn't build as they lacked CONFIG_MAX_CPUS. I copied the values from Config.lb Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[v2] r4732 - in trunk/coreboot-v2/src: cpu/amd cpu/amd/socket_754 mainboard/gigabyte/m57sli mainboard/msi mainboard/msi/ms7135 mainboard/msi/ms7260 mainboard/msi/ms9185 mainboard/msi/ms9282 mainboard/supermicro/h8dme
by svn＠coreboot.org 07 Oct '09

07 Oct '09

Author: oxygene Date: 2009-10-07 17:30:58 +0200 (Wed, 07 Oct 2009) New Revision: 4732 Added: trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7135/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms7260/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms9185/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms9282/Makefile.inc Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig trunk/coreboot-v2/src/cpu/amd/Makefile.inc trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc Log: Kconfig: - Add AMD Socket 754, - Fix MCP55 boards (romstrap) - Implement remaining MSI boards Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-10-07 14:36:16 UTC (rev 4731) +++ trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -2,7 +2,7 @@ bool default n -#source src/cpu/amd/socket_754/Kconfig +source src/cpu/amd/socket_754/Kconfig #source src/cpu/amd/socket_939/Kconfig source src/cpu/amd/socket_940/Kconfig source src/cpu/amd/socket_AM2/Kconfig Modified: trunk/coreboot-v2/src/cpu/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-10-07 14:36:16 UTC (rev 4731) +++ trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -1,4 +1,5 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F +subdirs-$(CONFIG_CPU_AMD_SOCKET_754) += socket_754 subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 Added: trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,9 @@ +config CPU_AMD_SOCKET_754 + bool + default n + select CPU_AMD_MODEL_FXX + +config CPU_SOCKET_TYPE + hex + default 0x10 + depends on CPU_AMD_SOCKET_754 Added: trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,14 @@ +obj-y += socket_754.o +subdirs-y += ../model_fxx +subdirs-y += ../dualcore +subdirs-y += ../mtrr +subdirs-y += ../microcode +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/pae Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-07 14:36:16 UTC (rev 4731) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -36,14 +36,16 @@ crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc -crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc crt0-y += auto.inc ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds -ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds ldscript-y += ../../../../src/arch/i386/lib/failover.lds ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb Modified: trunk/coreboot-v2/src/mainboard/msi/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-10-07 14:36:16 UTC (rev 4731) +++ trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -25,6 +25,10 @@ source "src/mainboard/msi/ms6119/Kconfig" source "src/mainboard/msi/ms6147/Kconfig" source "src/mainboard/msi/ms6178/Kconfig" +source "src/mainboard/msi/ms7135/Kconfig" +source "src/mainboard/msi/ms7260/Kconfig" +source "src/mainboard/msi/ms9185/Kconfig" +source "src/mainboard/msi/ms9282/Kconfig" endchoice Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,137 @@ +config BOARD_MSI_MS7135 + bool "MS7135" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_754 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_WINBOND_W83627THF + select PIRQ_TABLE + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default msi/ms7135 + depends on BOARD_MSI_MS7135 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_MSI_MS7135 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_MSI_MS7135 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_MSI_MS7135 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_MSI_MS7135 + +config MAINBOARD_PART_NUMBER + string + default "ms7135" + depends on BOARD_MSI_MS7135 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2895 + depends on BOARD_MSI_MS7135 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_MSI_MS7135 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_MSI_MS7135 + +config MAX_CPUS + int + default 2 + depends on BOARD_MSI_MS7135 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_MSI_MS7135 + +config MEM_TRAIN_SEQ + bool + default n + depends on BOARD_MSI_MS7135 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_MSI_MS7135 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_MSI_MS7135 + +config HT_CHAIN_UNITID_BASE + hex + default 0 + depends on BOARD_MSI_MS7135 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + depends on BOARD_MSI_MS7135 + +config USE_INIT + bool + default n + depends on BOARD_MSI_MS7135 + +config SERIAL_CPU_INIT + bool + default y + depends on BOARD_MSI_MS7135 + +config AP_CODE_IN_CAR + bool + default y + depends on BOARD_MSI_MS7135 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_MSI_MS7135 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_MSI_MS7135 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_MSI_MS7135 + +config IRQ_SLOT_COUNT + int + default 13 + depends on BOARD_MSI_MS7135 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_MSI_MS7135 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + depends on BOARD_MSI_MS7135 Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1 @@ +include $(src)/mainboard/tyan/Makefile.s289x.inc Added: trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,148 @@ +config BOARD_MSI_MS7260 + bool "MS7260" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_AM2 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627EHG + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select HAVE_HIGH_TABLES + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select K8_REV_F_SUPPORT + +config MAINBOARD_DIR + string + default msi/ms7260 + depends on BOARD_MSI_MS7260 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_MSI_MS7260 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_MSI_MS7260 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_MSI_MS7260 + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_MSI_MS7260 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_MSI_MS7260 + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_MSI_MS7260 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_MSI_MS7260 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_MSI_MS7260 + +config MAINBOARD_PART_NUMBER + string + default "ms7260" + depends on BOARD_MSI_MS7260 + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_MSI_MS7260 + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_MSI_MS7260 + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_MSI_MS7260 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_MSI_MS7260 + +config MAX_CPUS + int + default 2 + depends on BOARD_MSI_MS7260 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_MSI_MS7260 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_MSI_MS7260 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_MSI_MS7260 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_MSI_MS7260 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_MSI_MS7260 + +config USE_INIT + bool + default n + depends on BOARD_MSI_MS7260 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_MSI_MS7260 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_MSI_MS7260 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1462 + depends on BOARD_MSI_MS7260 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x7260 + depends on BOARD_MSI_MS7260 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_MSI_MS7260 Added: trunk/coreboot-v2/src/mainboard/msi/ms7260/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o +obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o + +# This is part of the conversion to init-obj and away from included code. +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif Added: trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,123 @@ +config BOARD_MSI_MS9185 + bool "MS9185" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_BROADCOM_BCM5780 + select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_NSC_PC87417 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + +config MAINBOARD_DIR + string + default msi/ms9185 + depends on BOARD_MSI_MS9185 + +config DCACHE_RAM_BASE + hex + default 0xcc000 + depends on BOARD_MSI_MS9185 + +config DCACHE_RAM_SIZE + hex + default 0x04000 + depends on BOARD_MSI_MS9185 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_MSI_MS9185 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_MSI_MS9185 + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_MSI_MS9185 + +config IOAPIC + bool + default y + depends on BOARD_MSI_MS9185 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_MSI_MS9185 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_MSI_MS9185 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_MSI_MS9185 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_MSI_MS9185 + +config MAINBOARD_PART_NUMBER + string + default "ultra40" + depends on BOARD_MSI_MS9185 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_MSI_MS9185 + +config MAX_CPUS + int + default 4 + depends on BOARD_MSI_MS9185 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_MSI_MS9185 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_MSI_MS9185 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_MSI_MS9185 + +config USE_INIT + bool + default n + depends on BOARD_MSI_MS9185 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_MSI_MS9185 + +config CONSOLE_VGA + bool + default y + depends on BOARD_MSI_MS9185 + +config PCI_ROM_RUN + bool + default y + depends on BOARD_MSI_MS9185 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_MSI_MS9185 Added: trunk/coreboot-v2/src/mainboard/msi/ms9185/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,33 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Kconfig 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,148 @@ +config BOARD_MSI_MS9282 + bool "MS9282" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627EHG + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select HAVE_HIGH_TABLES + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select K8_REV_F_SUPPORT + +config MAINBOARD_DIR + string + default msi/ms9282 + depends on BOARD_MSI_MS9282 + +config DCACHE_RAM_BASE + hex + default 0xcc000 + depends on BOARD_MSI_MS9282 + +config DCACHE_RAM_SIZE + hex + default 0x04000 + depends on BOARD_MSI_MS9282 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_MSI_MS9282 + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_MSI_MS9282 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_MSI_MS9282 + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_MSI_MS9282 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_MSI_MS9282 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_MSI_MS9282 + +config MAINBOARD_PART_NUMBER + string + default "ms9282" + depends on BOARD_MSI_MS9282 + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_MSI_MS9282 + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_MSI_MS9282 + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_MSI_MS9282 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_MSI_MS9282 + +config MAX_CPUS + int + default 2 + depends on BOARD_MSI_MS9282 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_MSI_MS9282 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_MSI_MS9282 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_MSI_MS9282 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_MSI_MS9282 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_MSI_MS9282 + +config USE_INIT + bool + default n + depends on BOARD_MSI_MS9282 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_MSI_MS9282 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_MSI_MS9282 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1462 + depends on BOARD_MSI_MS9282 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x9282 + depends on BOARD_MSI_MS9282 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_MSI_MS9282 Added: trunk/coreboot-v2/src/mainboard/msi/ms9282/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -0,0 +1,66 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o +driver-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o +driver-y += ../../../drivers/i2c/adm1027/adm1027.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o +obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o + +# This is part of the conversion to init-obj and away from included code. +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc 2009-10-07 14:36:16 UTC (rev 4731) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Makefile.inc 2009-10-07 15:30:58 UTC (rev 4732) @@ -34,14 +34,16 @@ crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc -crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc crt0-y += auto.inc ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds -ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds ldscript-y += ../../../../src/arch/i386/lib/failover.lds ifdef POST_EVALUATION

1 0

[PATCH] AMD CS5530(A) ROM enable
by Uwe Hermann 07 Oct '09

07 Oct '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

7 9

[v2] r4731 - in trunk/coreboot-v2/src: mainboard/advantech/pcm-5820 mainboard/asi/mb_5blgp mainboard/asi/mb_5blmp mainboard/axus/tc320 mainboard/bcom/winnet100 mainboard/eaglelion/5bcm mainboard/iei/juki-511p mainboard/iei/nova4899r mainboard/televideo/tc7020 southbridge/amd/cs5530
by svn＠coreboot.org 07 Oct '09

07 Oct '09

Author: uwe Date: 2009-10-07 16:36:16 +0200 (Wed, 07 Oct 2009) New Revision: 4731 Added: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_enable_rom.c Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530.h trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c Log: Enable full ROM access on AMD CS5530(A) (needed for CBFS). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -31,6 +31,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977f/w83977f_early_serial.c" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) @@ -40,6 +41,7 @@ uart_init(); console_init(); report_bist_failure(bist); + cs5530_enable_rom(); sdram_init(); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -31,6 +31,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87351/pc87351_early_serial.c" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) @@ -40,6 +41,7 @@ uart_init(); console_init(); report_bist_failure(bist); + cs5530_enable_rom(); sdram_init(); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -32,6 +32,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" #include "cpu/x86/bist.h" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) @@ -45,6 +46,8 @@ /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + cs5530_enable_rom(); + /* Initialize RAM. */ sdram_init(); Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -32,6 +32,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) @@ -41,6 +42,7 @@ uart_init(); console_init(); report_bist_failure(bist); + cs5530_enable_rom(); sdram_init(); /* ram_check(0, 640 * 1024); */ } Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -32,6 +32,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) @@ -45,6 +46,8 @@ /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + cs5530_enable_rom(); + /* Initialize RAM. */ sdram_init(); Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -14,6 +14,7 @@ #include "superio/nsc/pc97317/pc97317_early_serial.c" //#include "northbridge/intel/i440bx/raminit.h" #include "cpu/x86/bist.h" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) @@ -30,6 +31,8 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); + cs5530_enable_rom(); + sdram_init(); /* Check all of memory */ Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -30,6 +30,7 @@ #include "arch/i386/lib/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" @@ -51,6 +52,8 @@ inb(0x043); inb(0x843); + cs5530_enable_rom(); + /* Initialize RAM. */ sdram_init(); Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -30,6 +30,7 @@ #include "arch/i386/lib/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -46,6 +47,8 @@ /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + cs5530_enable_rom(); + /* Initialize RAM. */ sdram_init(); Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/auto.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -32,6 +32,7 @@ #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) @@ -45,6 +46,8 @@ /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + cs5530_enable_rom(); + /* Initialize RAM. */ sdram_init(); Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530.h =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530.h 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530.h 2009-10-07 14:36:16 UTC (rev 4731) @@ -27,7 +27,13 @@ #endif #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ +#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ +#define LOWER_ROM_ADDRESS_RANGE (1 << 0) +#define ROM_WRITE_ENABLE (1 << 1) +#define UPPER_ROM_ADDRESS_RANGE (1 << 2) +#define BIOS_ROM_POSITIVE_DECODE (1 << 5) + /* Selects PCI positive decoding for accesses to the configured ROM space. */ #define BIOS_ROM_POSITIVE_DECODE (1 << 5) Added: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_enable_rom.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_enable_rom.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_enable_rom.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "cs5530.h" + +static void cs5530_enable_rom(void) +{ + uint8_t reg8; + + /* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */ + device_t dev = PCI_DEV(0, 0x12, 0); + + /* + * Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and + * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. + * + * Make the ROM write-protected. + */ + reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG); + reg8 |= LOWER_ROM_ADDRESS_RANGE; + reg8 |= UPPER_ROM_ADDRESS_RANGE; + reg8 &= ~ROM_WRITE_ENABLE; + pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); + + /* Set positive decode on ROM. */ + reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2); + reg8 |= BIOS_ROM_POSITIVE_DECODE; + pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); +} Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c 2009-10-07 14:13:36 UTC (rev 4730) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/cs5530_isa.c 2009-10-07 14:36:16 UTC (rev 4731) @@ -45,14 +45,6 @@ static void isa_init(struct device *dev) { - uint8_t reg8; - - // TODO: Test if needed, otherwise drop. - - /* Set positive decode on ROM. */ - reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2); - reg8 |= BIOS_ROM_POSITIVE_DECODE; - pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); } static void cs5530_pci_dev_enable_resources(device_t dev)

1 0

[v2] r4730 - in trunk/coreboot-v2/src/mainboard: . advantech/pcm-5820 asi/mb_5blgp asi/mb_5blmp axus/tc320 bcom bcom/winnet100 bcom/winnetp680 dell/s1850 eaglelion/5bcm gigabyte gigabyte/ga_2761gxdk iei/juki-511p iei/nova4899r intel/jarrell intel/mtarvon intel/truxton intel/xe7501devkit jetway jetway/j7f24 newisys newisys/khepri nvidia nvidia/l1_2pvv rca rca/rm4100 televideo/tc7020
by svn＠coreboot.org 07 Oct '09

07 Oct '09

Author: oxygene Date: 2009-10-07 16:13:36 +0200 (Wed, 07 Oct 2009) New Revision: 4730 Added: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Kconfig trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Makefile.inc trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc trunk/coreboot-v2/src/mainboard/jetway/j7f24/Kconfig trunk/coreboot-v2/src/mainboard/jetway/j7f24/Makefile.inc trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig trunk/coreboot-v2/src/mainboard/newisys/khepri/Makefile.inc trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Makefile.inc trunk/coreboot-v2/src/mainboard/rca/rm4100/Kconfig trunk/coreboot-v2/src/mainboard/rca/rm4100/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc trunk/coreboot-v2/src/mainboard/bcom/Kconfig trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc trunk/coreboot-v2/src/mainboard/jetway/Kconfig trunk/coreboot-v2/src/mainboard/newisys/Kconfig trunk/coreboot-v2/src/mainboard/nvidia/Kconfig trunk/coreboot-v2/src/mainboard/rca/Kconfig trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc Log: More boards in kconfig, and moved -O2 flag for romcc into ROMCCFLAGS, so boards can override it where necessary. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -51,17 +51,17 @@ ifdef POST_EVALUATION -ROMCCFLAGS ?= -mcpu=p2 +ROMCCFLAGS ?= -mcpu=p2 -O2 $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - $(obj)/romcc $(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c - $(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ endif endif Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/bcom/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/Kconfig 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/bcom/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -23,7 +23,7 @@ depends on VENDOR_BCOM source "src/mainboard/bcom/winnet100/Kconfig" -# source "src/mainboard/bcom/winnetp680/Kconfig" +source "src/mainboard/bcom/winnetp680/Kconfig" endchoice Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Added: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,36 @@ +config BOARD_BCOM_WINNETP680 + bool "WinNET P680" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_WINBOND_W83697HF + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default bcom/winnetp680 + depends on BOARD_BCOM_WINNETP680 + +config MAINBOARD_PART_NUMBER + string + default "WinNET P680" + depends on BOARD_BCOM_WINNETP680 + +config IRQ_SLOT_COUNT + int + default 10 + depends on BOARD_BCOM_WINNETP680 + +config VIDEO_MB + int + default 32 + depends on BOARD_BCOM_WINNETP680 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_BCOM_WINNETP680 + Added: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,61 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -46,17 +46,17 @@ ifdef POST_EVALUATION -ROMCCFLAGS ?= -mcpu=p4 +ROMCCFLAGS ?= -mcpu=p4 -O2 $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c - $(obj)/romcc $(ROMCCFLAGS) -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ ifeq ($(CONFIG_HAVE_OPTION_TABLE),y) $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ else $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c - $(obj)/romcc $(ROMCCFLAGS) -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ endif endif Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -22,6 +22,7 @@ prompt "Mainboard model" depends on VENDOR_GIGABYTE +source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" Added: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,148 @@ +config BOARD_GIGABYTE_GA_2761GXDK + bool "GA-2761GXDK" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_AM2 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_SIS_SIS966 + select SUPERIO_ITE_IT8716F + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select HAVE_HIGH_TABLES + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select K8_REV_F_SUPPORT + +config MAINBOARD_DIR + string + default gigabyte/ga_2761gxdk + depends on BOARD_GIGABYTE_GA_2761GXDK + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config LB_CKS_LOC + int + default 123 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config MAINBOARD_PART_NUMBER + string + default "ga2761gxdk" + depends on BOARD_GIGABYTE_GA_2761GXDK + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config MAX_CPUS + int + default 2 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config USE_INIT + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_GIGABYTE_GA_2761GXDK + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2b80 + depends on BOARD_GIGABYTE_GA_2761GXDK + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_GIGABYTE_GA_2761GXDK Added: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o +obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o + +# This is part of the conversion to init-obj and away from included code. +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/sis/sis966/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/sis/sis966/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -1,4 +1,4 @@ obj-y += reset.o -ROMCCFLAGS := -mcpu=p4 +ROMCCFLAGS := -mcpu=p4 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -1,3 +1,3 @@ -ROMCCFLAGS := -mcpu=p4 +ROMCCFLAGS := -mcpu=p4 -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -1,3 +1,3 @@ -ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi +ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -1,4 +1,4 @@ -ROMCCFLAGS := -mcpu=p4 +ROMCCFLAGS := -mcpu=p4 -O2 obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/jetway/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/Kconfig 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/jetway/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_JETWAY + +source "src/mainboard/jetway/j7f24/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,43 @@ +config BOARD_JETWAY_J7F24 + bool "J7F24" + select ARCH_X86 + select CPU_VIA_C7 + select NORTHBRIDGE_VIA_CN700 + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_FINTEK_F71805F + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default jetway/j7f24 + depends on BOARD_JETWAY_J7F24 + +#config DCACHE_RAM_BASE +# hex +# default 0xffef0000 +# depends on BOARD_JETWAY_J7F24 +# +#config DCACHE_RAM_SIZE +# hex +# default 0x8000 +# depends on BOARD_JETWAY_J7F24 + +config MAINBOARD_PART_NUMBER + string + default "j7f24" + depends on BOARD_JETWAY_J7F24 + +config VIDEO_MB + int + default 32 + depends on BOARD_JETWAY_J7F24 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_JETWAY_J7F24 + +config IRQ_SLOT_COUNT + int + default 10 + depends on BOARD_JETWAY_J7F24 Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 VIA Technologies, Inc. +## (Written by Aaron Lwe <aaron.lwe(a)gmail.com> for VIA) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +initobj-y += crt0.o +obj-y += mainboard.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc +crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-y += auto.inc +crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/newisys/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/Kconfig 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/newisys/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_NEWISYS + +source "src/mainboard/newisys/khepri/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,123 @@ +config BOARD_NEWISYS_KHEPRI + bool "Khepri" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + +config MAINBOARD_DIR + string + default newisys/khepri + depends on BOARD_NEWISYS_KHEPRI + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_NEWISYS_KHEPRI + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on BOARD_NEWISYS_KHEPRI + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_NEWISYS_KHEPRI + +config HAVE_HARD_RESET + bool + default y + depends on BOARD_NEWISYS_KHEPRI + +config IOAPIC + bool + default y + depends on BOARD_NEWISYS_KHEPRI + +config K8_REV_F_SUPPORT + bool + default n + depends on BOARD_NEWISYS_KHEPRI + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_NEWISYS_KHEPRI + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_NEWISYS_KHEPRI + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_NEWISYS_KHEPRI + +config LB_CKS_LOC + int + default 123 + depends on BOARD_NEWISYS_KHEPRI + +config MAINBOARD_PART_NUMBER + string + default "Khepri" + depends on BOARD_NEWISYS_KHEPRI + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_NEWISYS_KHEPRI + +config MAX_CPUS + int + default 4 + depends on BOARD_NEWISYS_KHEPRI + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_NEWISYS_KHEPRI + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_NEWISYS_KHEPRI + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_NEWISYS_KHEPRI + +config USE_INIT + bool + default n + depends on BOARD_NEWISYS_KHEPRI + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_NEWISYS_KHEPRI + +config CONSOLE_VGA + bool + default y + depends on BOARD_NEWISYS_KHEPRI + +config PCI_ROM_RUN + bool + default y + depends on BOARD_NEWISYS_KHEPRI + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_NEWISYS_KHEPRI Added: trunk/coreboot-v2/src/mainboard/newisys/khepri/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/nvidia/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/Kconfig 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/nvidia/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_NVIDIA + +source "src/mainboard/nvidia/l1_2pvv/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,148 @@ +config BOARD_NVIDIA_L1_2PVV + bool "L1 2PVV" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627EHG + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select HAVE_HIGH_TABLES + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select K8_REV_F_SUPPORT + +config MAINBOARD_DIR + string + default nvidia/l1_2pvv + depends on BOARD_NVIDIA_L1_2PVV + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_NVIDIA_L1_2PVV + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_NVIDIA_L1_2PVV + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_NVIDIA_L1_2PVV + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_NVIDIA_L1_2PVV + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_NVIDIA_L1_2PVV + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_NVIDIA_L1_2PVV + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_NVIDIA_L1_2PVV + +config LB_CKS_LOC + int + default 123 + depends on BOARD_NVIDIA_L1_2PVV + +config MAINBOARD_PART_NUMBER + string + default "l1_2pvv" + depends on BOARD_NVIDIA_L1_2PVV + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_NVIDIA_L1_2PVV + +config MAX_CPUS + int + default 2 + depends on BOARD_NVIDIA_L1_2PVV + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_NVIDIA_L1_2PVV + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_NVIDIA_L1_2PVV + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_NVIDIA_L1_2PVV + +config USE_INIT + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_NVIDIA_L1_2PVV + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_NVIDIA_L1_2PVV + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2b80 + depends on BOARD_NVIDIA_L1_2PVV + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_NVIDIA_L1_2PVV Added: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o +obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o + +# This is part of the conversion to init-obj and away from included code. +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif Modified: trunk/coreboot-v2/src/mainboard/rca/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/Kconfig 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/rca/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_RCA + +source "src/mainboard/rca/rm4100/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/rca/rm4100/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Kconfig 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,36 @@ +config BOARD_RCA_RM4100 + bool "RM4100" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82830 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default rca/rm4100 + depends on BOARD_RCA_RM4100 + +config MAINBOARD_PART_NUMBER + string + default "RM4100" + depends on BOARD_RCA_RM4100 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_RCA_RM4100 + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_RCA_RM4100 + +config VIDEO_MB + int + default 0 + depends on BOARD_RCA_RM4100 + Added: trunk/coreboot-v2/src/mainboard/rca/rm4100/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -0,0 +1,4 @@ +ROMCCFLAGS=-mcpu=p3 -O + +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc 2009-10-06 22:25:21 UTC (rev 4729) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc 2009-10-07 14:13:36 UTC (rev 4730) @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ROMCCFLAGS := -mcpu=i386 +ROMCCFLAGS := -mcpu=i386 -O2 include $(src)/mainboard/Makefile.romccboard.inc

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coreboot October 2009