coreboot October 2009

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534 discussions

SeaBIOS and USB UHCI keyboard support
by Kevin O'Connor 30 Sep '09

30 Sep '09

The latest SeaBIOS git has preliminary support for USB keyboards. I've tested this on qemu and on my epia-cn. For info on obtaining SeaBIOS see: http://www.coreboot.org/SeaBIOS This support is still a little "rough" - help with testing would be appreciated, but don't expect it to be fully functional. Known issues: - only uhci controllers are supported - no ohci (nor ehci) - not all keys are mapped (eg, no numeric keypad) - no keyboard auto-repeat - no keyboard led support - if one types fast, they may see dup keys or missing keys - no hub support (keyboard must be directly attached) - usb bandwidth is not optimized (no scheduling) That said, I can control the SeaBIOS boot and navigate through a grub console with my usb keyboard. -Kevin

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Re: [coreboot] [v2] r4698 - trunk/coreboot-v2/src/mainboard/dell/s1850
by Ed Swierk 30 Sep '09

30 Sep '09

On Wed, Sep 30, 2009 at 5:02 PM, <svn(a)coreboot.org> wrote: > + /* using SerialICE, we've seen this basic reset sequence on the dell. > + * we don't understand it as it uses undocumented registers, but > + * we're going to clone it. > + */ > + /* enable a hidden device. */ > + b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); > + b |= 0x8; > + pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); > + > + /* read-write lock in CMOS on LPC bridge on ICH5 */ > + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); > + > + /* operate on undocumented device */ > + l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); > + l |= 0x1000; > + pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); > + > + l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); > + l |= 0x8000; > + pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); > + > + /* disable undocumented device */ > + b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); > + b &= ~0x8; > + pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); http://downloadmirror.intel.com/8815/ENG/README.TXT offers a hint about what this is doing, but doesn't really explain why: "According MCH BSU 0.82, document#64:Required Register Settings. To take full advantage of the changes in the MCH Silicon, for stability on MCH B0 stepping and above, Intel recommends that BIOS clear bit 12 of D0:F2:R0A4h and set bit 15 of D0:F2:R09Ch very early during boot." --Ed

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build service results for r4698
by coreboot information 30 Sep '09

30 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4698 to the coreboot repository. This caused the following changes: Change Log: This is now set up more like the real hardware likes it. Some of this trickery was determined with serialice. There are several lovely undocumented features to the chipset. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4698&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4698&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4698&device=briq&vendor=to… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4698 - trunk/coreboot-v2/src/mainboard/dell/s1850
by svn＠coreboot.org 30 Sep '09

30 Sep '09

Author: rminnich Date: 2009-10-01 02:02:28 +0200 (Thu, 01 Oct 2009) New Revision: 4698 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c Log: This is now set up more like the real hardware likes it. Some of this trickery was determined with serialice. There are several lovely undocumented features to the chipset. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-09-30 21:36:38 UTC (rev 4697) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-01 00:02:28 UTC (rev 4698) @@ -173,8 +173,13 @@ } /* end IPMI garbage */ + static void main(unsigned long bist) { + u8 b; + u16 w; + u32 l; + int do_reset; /* * * @@ -191,6 +196,80 @@ } }; + /* using SerialICE, we've seen this basic reset sequence on the dell. + * we don't understand it as it uses undocumented registers, but + * we're going to clone it. + */ + /* enable a hidden device. */ + b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); + b |= 0x8; + pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); + + /* read-write lock in CMOS on LPC bridge on ICH5 */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4); + + /* operate on undocumented device */ + l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4); + l |= 0x1000; + pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l); + + l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c); + l |= 0x8000; + pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l); + + /* disable undocumented device */ + b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); + b &= ~0x8; + pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); + + /* set up LPC bridge bits, some of which reply on undocumented + * registers + */ + + b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8); + b |= 4; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b); + + b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4); + b |= 2; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b); + + /* ACPI base address */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800); + + /* Enable specific ACPI features */ + b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44); + b |= 0x10; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b); + + /* ACPI control */ + w = inw(0x868); + outw(w|0x800, 0x868); + w = inw(0x866); + outw(w|2, 0x866); + + /* SMBUS */ + pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); + + /* unknown */ + b = inb(0x8c2); + outb(0xdf, 0x8c2); + + /* another device enable? */ + b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); + b |= 2; + pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b); + + /* ?? */ + l = pci_read_config32(PCI_DEV(0, 0, 8), 0xc0); + do_reset = l & 0x8000000; + l |= 0x8000000; + pci_write_config32(PCI_DEV(0, 0, 2), 0xc0, l); + + if (! do_reset) { + outb(2, 0xcf9); + outb(6, 0xcf9); + } if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init();

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coreboot October 2009