coreboot October 2009

coreboot@coreboot.org

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534 discussions

[v2] r4719 - in trunk/coreboot-v2/src: . cpu/amd cpu/amd/model_gx1 mainboard mainboard/advantech mainboard/advantech/pcm-5820 mainboard/asi mainboard/asi/mb_5blgp mainboard/asi/mb_5blmp mainboard/axus mainboard/axus/tc320 mainboard/bcom mainboard/bcom/winnet100 mainboard/eaglelion mainboard/eaglelion/5bcm mainboard/iei mainboard/iei/juki-511p mainboard/iei/nova4899r mainboard/televideo mainboard/televideo/tc7020 northbridge/amd northbridge/amd/gx1 southbridge/amd/cs5530
by svn＠coreboot.org 04 Oct '09

04 Oct '09

Author: uwe Date: 2009-10-04 19:15:39 +0200 (Sun, 04 Oct 2009) New Revision: 4719 Added: trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/cpu/amd/Kconfig trunk/coreboot-v2/src/cpu/amd/Makefile.inc trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc trunk/coreboot-v2/src/mainboard/advantech/Kconfig trunk/coreboot-v2/src/mainboard/asi/Kconfig trunk/coreboot-v2/src/mainboard/axus/Kconfig trunk/coreboot-v2/src/mainboard/bcom/Kconfig trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig trunk/coreboot-v2/src/mainboard/iei/Kconfig trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb trunk/coreboot-v2/src/mainboard/televideo/Kconfig trunk/coreboot-v2/src/northbridge/amd/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig Log: Add initial kconfig support for all AMD GX1 boards. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -190,6 +190,10 @@ bool default n +config VIDEO_MB + int + default 0 + config USE_WATCHDOG_ON_BOOT bool default n Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -12,4 +12,5 @@ source src/cpu/amd/socket_S1G1/Kconfig source src/cpu/amd/model_fxx/Kconfig +source src/cpu/amd/model_gx1/Kconfig source src/cpu/amd/model_gx2/Kconfig Modified: trunk/coreboot-v2/src/cpu/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -1,5 +1,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 +subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 Added: trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_AMD_GX1 + bool + default n + Added: trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_gx1/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +driver-y += model_gx1_init.o Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -26,9 +26,16 @@ crt0-y += ../../../../src/arch/i386/lib/id.inc crt0-y += failover.inc crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc + +ifeq ($(CONFIG_CPU_AMD_GX1),y) +crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc +crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc +crt0-y += auto.inc +else crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc crt0-y += auto.inc crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc +endif ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds Modified: trunk/coreboot-v2/src/mainboard/advantech/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/advantech/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_ADVANTECH + +source "src/mainboard/advantech/pcm-5820/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ADVANTECH_PCM_5820 + bool "PCM-5820" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_WINBOND_W83977F + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default advantech/pcm-5820 + depends on BOARD_ADVANTECH_PCM_5820 + +config MAINBOARD_PART_NUMBER + string + default "PCM-5820" + depends on BOARD_ADVANTECH_PCM_5820 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ADVANTECH_PCM_5820 + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_ADVANTECH_PCM_5820 + Added: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/asi/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/asi/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,29 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_ASI + +source "src/mainboard/asi/mb_5blgp/Kconfig" +source "src/mainboard/asi/mb_5blmp/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASI_MB_5BLGP + bool "MB-5BLGP" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_NSC_PC87351 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default asi/mb_5blgp + depends on BOARD_ASI_MB_5BLGP + +config MAINBOARD_PART_NUMBER + string + default "MB-5BLGP" + depends on BOARD_ASI_MB_5BLGP + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASI_MB_5BLGP + +config IRQ_SLOT_COUNT + int + default 3 + depends on BOARD_ASI_MB_5BLGP + Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASI_MB_5BLMP + bool "MB-5BLMP" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_NSC_PC87351 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default asi/mb_5blmp + depends on BOARD_ASI_MB_5BLMP + +config MAINBOARD_PART_NUMBER + string + default "MB-5BLMP" + depends on BOARD_ASI_MB_5BLMP + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASI_MB_5BLMP + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_ASI_MB_5BLMP + Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/axus/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/axus/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_AXUS + +source "src/mainboard/axus/tc320/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_AXUS_TC320 + bool "TC320" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_NSC_PC97317 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default axus/tc320 + depends on BOARD_AXUS_TC320 + +config MAINBOARD_PART_NUMBER + string + default "TC320" + depends on BOARD_AXUS_TC320 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_AXUS_TC320 + +# Soldered NIC, internal USB, no real PCI slots. +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_AXUS_TC320 + Added: trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/bcom/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/bcom/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,29 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_BCOM + +source "src/mainboard/bcom/winnet100/Kconfig" +# source "src/mainboard/bcom/winnetp680/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_BCOM_WINNET100 + bool "WinNET100" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_NSC_PC97317 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default bcom/winnet100 + depends on BOARD_BCOM_WINNET100 + +config MAINBOARD_PART_NUMBER + string + default "WinNET100" + depends on BOARD_BCOM_WINNET100 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_BCOM_WINNET100 + +# Soldered NIC, internal USB, no real PCI slots. +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_BCOM_WINNET100 + Added: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_EAGLELION_5BCM + bool "5BCM" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_NSC_PC97317 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default eaglelion/5bcm + depends on BOARD_EAGLELION_5BCM + +config MAINBOARD_PART_NUMBER + string + default "5BCM" + depends on BOARD_EAGLELION_5BCM + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_EAGLELION_5BCM + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_EAGLELION_5BCM + Added: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/irq_tables.c 2009-10-04 17:15:39 UTC (rev 4719) @@ -10,7 +10,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*2, /* there can be total 2 devices on the bus */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total 2 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x800, /* IRQs devoted exclusively to PCI usage */ Modified: trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_EAGLELION + +source "src/mainboard/eaglelion/5bcm/Kconfig" + +endchoice + Modified: trunk/coreboot-v2/src/mainboard/iei/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/iei/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,29 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_IEI + +source "src/mainboard/iei/juki-511p/Kconfig" +source "src/mainboard/iei/nova4899r/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,48 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_IEI_JUKI_511P + bool "JUKI-511P" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_WINBOND_W83977F + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select HAVE_OPTION_TABLE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default iei/juki-511p + depends on BOARD_IEI_JUKI_511P + +config MAINBOARD_PART_NUMBER + string + default "JUKI-511P" + depends on BOARD_IEI_JUKI_511P + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_IEI_JUKI_511P + Added: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,48 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_IEI_NOVA_4899R + bool "NOVA-4899R" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_WINBOND_W83977TF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select HAVE_OPTION_TABLE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default iei/nova4899r + depends on BOARD_IEI_NOVA_4899R + +config MAINBOARD_PART_NUMBER + string + default "NOVA-4899R" + depends on BOARD_IEI_NOVA_4899R + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_IEI_NOVA_4899R + Added: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-10-04 17:15:39 UTC (rev 4719) @@ -82,7 +82,7 @@ ## Build code to export a programmable irq routing table ## default CONFIG_HAVE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=7 +default CONFIG_IRQ_SLOT_COUNT=5 default CONFIG_PIRQ_ROUTE=1 #object irq_tables.o Modified: trunk/coreboot-v2/src/mainboard/televideo/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/mainboard/televideo/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_TELEVIDEO + +source "src/mainboard/televideo/tc7020/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_TELEVIDEO_TC7020 + bool "TC7020" + select ARCH_X86 + select CPU_AMD_GX1 + select NORTHBRIDGE_AMD_GX1 + select SOUTHBRIDGE_AMD_CS5530 + select SUPERIO_NSC_PC97317 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default televideo/tc7020 + depends on BOARD_TELEVIDEO_TC7020 + +config MAINBOARD_PART_NUMBER + string + default "TC7020" + depends on BOARD_TELEVIDEO_TC7020 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_TELEVIDEO_TC7020 + +config IRQ_SLOT_COUNT + int + default 3 + depends on BOARD_TELEVIDEO_TC7020 + Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS := -mcpu=i386 +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/northbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1,5 +1,5 @@ source src/northbridge/amd/amdk8/Kconfig +source src/northbridge/amd/gx1/Kconfig source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig -#source src/northbridge/amd/gx1/Kconfig #source src/northbridge/amd/lx/Kconfig Added: trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_AMD_GX1 + bool + default n + Added: trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/Makefile.inc 2009-10-04 17:15:39 UTC (rev 4719) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += northbridge.o + Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig 2009-10-04 12:30:44 UTC (rev 4718) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig 2009-10-04 17:15:39 UTC (rev 4719) @@ -1,3 +1,76 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config SOUTHBRIDGE_AMD_CS5530 bool default n + +menu "AMD Geode GX1 video support" + depends on SOUTHBRIDGE_AMD_CS5530 + +config GX1_VIDEO + bool "AMD Geode GX1 video mode support" + default y + depends on SOUTHBRIDGE_AMD_CS5530 + +choice + prompt "AMD Geode GX1 video mode" + default GX1_VIDEOMODE_0 + depends on GX1_VIDEO + +config GX1_VIDEOMODE_0 + bool "640x480" +config GX1_VIDEOMODE_1 + bool "800x600" +config GX1_VIDEOMODE_2 + bool "1024x768" +config GX1_VIDEOMODE_3 + bool "1280x960" +config GX1_VIDEOMODE_4 + bool "1280x1024" + +endchoice + +config GX1_VIDEOMODE + int + default 0 if GX1_VIDEOMODE_0 + default 1 if GX1_VIDEOMODE_1 + default 2 if GX1_VIDEOMODE_2 + default 3 if GX1_VIDEOMODE_3 + default 4 if GX1_VIDEOMODE_4 + depends on GX1_VIDEO + +# TODO: Check how much RAM each of the modes actually needs. +config VIDEO_MB + int + default 2 if GX1_VIDEOMODE_0 + default 2 if GX1_VIDEOMODE_1 + default 2 if GX1_VIDEOMODE_2 + default 2 if GX1_VIDEOMODE_3 + default 2 if GX1_VIDEOMODE_4 + depends on GX1_VIDEO + +config SPLASH_GRAPHIC + bool "Enable splash screen on AMD Geode GX1 boards" + default y + depends on GX1_VIDEO + +endmenu +

1 0

[PATCH]remove pre-cbfs build system, pt. 3
by Patrick Georgi 04 Oct '09

04 Oct '09

Hi, this patch does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE. Both were only really used in pre-cbfs, as the payload's size isn't relevant for the build process anymore. abuild is happily chugging along, but it isn't runtime tested. esp. failover boards are affected by this, so if someone with a board configured for failover could test this, and report back (basically: do both fallback and normal still work?), I'd be grateful. Various calculations in {no,}failovercalculation.lb are adapted accordingly. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 2

[v2] r4718 - in trunk/coreboot-v2: src/arch/i386 src/arch/ppc src/config util
by svn＠coreboot.org 04 Oct '09

04 Oct '09

Author: oxygene Date: 2009-10-04 14:30:44 +0200 (Sun, 04 Oct 2009) New Revision: 4718 Removed: trunk/coreboot-v2/util/buildrom/ Modified: trunk/coreboot-v2/src/arch/i386/Config.lb trunk/coreboot-v2/src/arch/ppc/Config.lb trunk/coreboot-v2/src/config/Config.lb trunk/coreboot-v2/src/config/coreboot_ram.ld Log: This removes the uses of the buildrom utility and the coreboot.strip intermediate file. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/Config.lb 2009-10-04 12:27:48 UTC (rev 4717) +++ trunk/coreboot-v2/src/arch/i386/Config.lb 2009-10-04 12:30:44 UTC (rev 4718) @@ -44,16 +44,6 @@ if CONFIG_USE_FAILOVER_IMAGE makedefine COREBOOT_APC:= makedefine COREBOOT_RAM_ROM:= - - makerule coreboot.rom - depends "coreboot.strip" - action "cp $< $@" - end -else - makerule coreboot.rom - depends "coreboot.strip buildrom" - action "./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)" - end end makerule crt0.S Modified: trunk/coreboot-v2/src/arch/ppc/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/ppc/Config.lb 2009-10-04 12:27:48 UTC (rev 4717) +++ trunk/coreboot-v2/src/arch/ppc/Config.lb 2009-10-04 12:30:44 UTC (rev 4718) @@ -1,12 +1,7 @@ ldscript init/ldscript.lb -makerule coreboot.strip - depends "coreboot" - action "cp $< $@" -end - makerule coreboot.rom - depends "coreboot.strip" + depends "coreboot" action "cp $< $@" end Modified: trunk/coreboot-v2/src/config/Config.lb =================================================================== --- trunk/coreboot-v2/src/config/Config.lb 2009-10-04 12:27:48 UTC (rev 4717) +++ trunk/coreboot-v2/src/config/Config.lb 2009-10-04 12:30:44 UTC (rev 4718) @@ -33,9 +33,9 @@ # action "perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@" #end -makerule coreboot.strip +makerule coreboot.rom depends "coreboot" - action "$(CONFIG_OBJCOPY) -O binary coreboot coreboot.strip" + action "$(CONFIG_OBJCOPY) -O binary coreboot coreboot.rom" end makerule coreboot.a @@ -133,12 +133,6 @@ action "$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm" end -# the buildrom tool -makerule buildrom - depends "$(TOP)/util/buildrom/buildrom.c" - action "$(HOSTCC) -o $@ $<" -end - # Force crt0.s (which has build time version code in it to rebuild every time) makedefine .PHONY : crt0.s makerule crt0.s @@ -204,7 +198,7 @@ action "rm -f ldscript.ld" action "rm -f a.out *.s *.l *.o *.E *.inc" action "rm -f TAGS tags romcc*" - action "rm -f docipl buildrom* chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*" + action "rm -f docipl chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*" action "rm -f build_opt_tbl* nrv2b* option_table.c option_table.h crt0.S crt0.disasm" action "rm -f smm smm.elf smm.map smm_bin.c" action "rm -f dsdt.aml dsdt.c" Modified: trunk/coreboot-v2/src/config/coreboot_ram.ld =================================================================== --- trunk/coreboot-v2/src/config/coreboot_ram.ld 2009-10-04 12:27:48 UTC (rev 4717) +++ trunk/coreboot-v2/src/config/coreboot_ram.ld 2009-10-04 12:30:44 UTC (rev 4718) @@ -57,7 +57,7 @@ /* * kevinh/Ispiri - Added an align, because the objcopy tool * incorrectly converts sections that are not long word aligned. - * This breaks the coreboot.strip target. + * This breaks the coreboot.rom target. */ . = ALIGN(4);

1 0

[v2] r4717 - trunk/coreboot-v2/src/arch/i386
by svn＠coreboot.org 04 Oct '09

04 Oct '09

Author: oxygene Date: 2009-10-04 14:27:48 +0200 (Sun, 04 Oct 2009) New Revision: 4717 Modified: trunk/coreboot-v2/src/arch/i386/Config.lb Log: Remove a bit of pre-cbfs build system infrastructure. Payloads are compressed by cbfstool itself, no need for external tools. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/arch/i386/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/Config.lb 2009-10-03 21:13:36 UTC (rev 4716) +++ trunk/coreboot-v2/src/arch/i386/Config.lb 2009-10-04 12:27:48 UTC (rev 4717) @@ -41,36 +41,6 @@ action "$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@" end -makerule payload - depends "$(PAYLOAD)" - action "cp $< $@" -end - -makerule payload.nrv2b - depends "$(PAYLOAD) nrv2b" - action "./nrv2b e $(PAYLOAD) $@" -end - -# unlike nrv2b, lzma is a huge build mess. If they want lzma, they have to have built it -makerule payload.lzma - depends "$(PAYLOAD) " - action "lzma -zc $(PAYLOAD) > $@ || lzma e $(PAYLOAD) $@" -end - - -# this one example shows the mess that has occurred. People are now mixing -# conditional if in the make style with if in the config language style. -# The -1 is linux standard. -# I don't much like it but it is the mode nowadays. So coreboot will change -# what a mess. -- RGM -# catch the case where there is no compression -makedefine PAYLOAD-1:=payload - -# catch the case where there is precompression. Yes, this bites. -if CONFIG_PRECOMPRESSED_PAYLOAD - makedefine PAYLOAD-1:=payload -end - if CONFIG_USE_FAILOVER_IMAGE makedefine COREBOOT_APC:= makedefine COREBOOT_RAM_ROM:= @@ -81,9 +51,8 @@ end else makerule coreboot.rom - depends "coreboot.strip buildrom $(PAYLOAD-1)" - action "touch cbfs-support; ./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)" - action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 ]; then echo l > cbfs-support; fi" + depends "coreboot.strip buildrom" + action "./buildrom $< $@ /dev/null $(CONFIG_ROM_IMAGE_SIZE) $(CONFIG_ROM_SECTION_SIZE)" end end

1 0

[PATCH]remove pre-cbfs build system, pt. 2
by Patrick Georgi 04 Oct '09

04 Oct '09

Hi, This removes the uses of the buildrom utility and the coreboot.strip intermediate file. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[PATCH]remove pre-cbfs build system, pt. 1
by Patrick Georgi 04 Oct '09

04 Oct '09

Hi, attached patch removes a bit of pre-cbfs build system infrastructure. Payloads are compressed by cbfstool itself, no need for external tools. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[PATCH]Remove non-CBFS
by Patrick Georgi 03 Oct '09

03 Oct '09

Hi, attached patch removes: - CONFIG_CBFS - anything that's conditional on CONFIG_CBFS == 0 - files that were only included for CONFIG_CBFS == 0 In particular: - elfboot - stream boot code - mini-filo and filesystems (depends on stream boot code) After this patch, there is no way to build an image that is not using CBFS anymore. I might not have caught everything, but an abuild run over everything built fine, and there is no mention of "CBFS" in the tree anymore that doesn't belong there. Kconfig is almost not affected, as it's CBFS-only, anyway. I only had to remove the CBFS configuration variable that defaulted to "true". I consider the tree ready for this as there are no known bugs anymore (except the one fixed by that other patch). Speak up if you disagree (I intend to wait with committing this patch until saturday evening CEST) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

9 48

[v2] r4716 - trunk/coreboot-v2/src/mainboard/gigabyte/m57sli
by svn＠coreboot.org 03 Oct '09

03 Oct '09

Author: oxygene Date: 2009-10-03 23:13:36 +0200 (Sat, 03 Oct 2009) New Revision: 4716 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig Log: Remove another FAILOVER variable. (trivial) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-03 21:06:53 UTC (rev 4715) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-03 21:13:36 UTC (rev 4716) @@ -92,11 +92,6 @@ default 0x100000 depends on BOARD_GIGABYTE_M57SLI -config USE_FAILOVER_IMAGE - bool - default n - depends on BOARD_GIGABYTE_M57SLI - config MAX_CPUS int default 2

1 0

[v2] r4715 - in trunk/coreboot-v2/src/mainboard/gigabyte: . m57sli
by svn＠coreboot.org 03 Oct '09

03 Oct '09

Author: oxygene Date: 2009-10-03 23:06:53 +0200 (Sat, 03 Oct 2009) New Revision: 4715 Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb Log: Add gigabyte/m57sli support to Kconfig. Whitespace fixes to devicetree.cb Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig 2009-10-03 21:04:13 UTC (rev 4714) +++ trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig 2009-10-03 21:06:53 UTC (rev 4715) @@ -21,8 +21,9 @@ choice prompt "Mainboard model" depends on VENDOR_GIGABYTE - + source "src/mainboard/gigabyte/ga-6bxc/Kconfig" +source "src/mainboard/gigabyte/m57sli/Kconfig" endchoice Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Kconfig 2009-10-03 21:06:53 UTC (rev 4715) @@ -0,0 +1,153 @@ + +config BOARD_GIGABYTE_M57SLI + bool "M57SLI" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_AM2 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_ITE_IT8716F + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select HAVE_HIGH_TABLES + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select HAVE_ACPI_TABLES + select K8_REV_F_SUPPORT + select PCI_ROM_RUN + select CONSOLE_VGA + select HAVE_FANCTL + +config MAINBOARD_DIR + string + default gigabyte/m57sli + depends on BOARD_GIGABYTE_M57SLI + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_GIGABYTE_M57SLI + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_GIGABYTE_M57SLI + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_GIGABYTE_M57SLI + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_GIGABYTE_M57SLI + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_GIGABYTE_M57SLI + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_GIGABYTE_M57SLI + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_GIGABYTE_M57SLI + +config LB_CKS_LOC + int + default 123 + depends on BOARD_GIGABYTE_M57SLI + +config MAINBOARD_PART_NUMBER + string + default "m57sli" + depends on BOARD_GIGABYTE_M57SLI + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_GIGABYTE_M57SLI + +config USE_FAILOVER_IMAGE + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config MAX_CPUS + int + default 2 + depends on BOARD_GIGABYTE_M57SLI + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_GIGABYTE_M57SLI + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_GIGABYTE_M57SLI + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_GIGABYTE_M57SLI + +config USE_INIT + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_GIGABYTE_M57SLI + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_GIGABYTE_M57SLI + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2b80 + depends on BOARD_GIGABYTE_M57SLI Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Makefile.inc 2009-10-03 21:06:53 UTC (rev 4715) @@ -0,0 +1,67 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o +obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_FANCTL) += fanctl.o + +# This is part of the conversion to init-obj and away from included code. +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb 2009-10-03 21:04:13 UTC (rev 4714) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb 2009-10-03 21:06:53 UTC (rev 4715) @@ -1,202 +1,175 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_AM2 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f - # Floppy and any LDN - device pnp 2e.0 off - # Watchdog from CLKIN, CLKIN = 24 MHz - irq 0x23 = 0x11 + device apic_cluster 0 on + chip cpu/amd/socket_AM2 + device apic 0 on end + end +end +device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on + chip southbridge/nvidia/mcp55 + device pci 0.0 on end + device pci 1.0 on + chip superio/ite/it8716f + # Floppy and any LDN + device pnp 2e.0 on + # Watchdog from CLKIN, CLKIN = 24 MHz + irq 0x23 = 0x11 # Serial Flash (SPI only) - #0x24 = 0x1a - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO, SPI flash - # pin 84 is not GP10 - irq 0x25 = 0x0 - # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 - irq 0x26 = 0x43 - # pin 13 is GP35 - irq 0x27 = 0x20 - # pin 70 is not GP46 - #irq 0x28 = 0x0 - # pin 6,3,128,127,126 is GP63,64,65,66,67 - irq 0x29 = 0x81 - # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V - #irq 0x2c = 0x1f - # Simple I/O base - io 0x62 = 0x800 - # Serial Flash I/O (SPI only) - io 0x64 = 0x820 - # watch dog force timeout (parallel flash only) - #irq 0x71 = 0x1 - # No WDT interrupt - irq 0x72 = 0x0 - # GPIO pin set 1 disable internal pullup - irq 0xb8 = 0x0 - # GPIO pin set 5 enable internal pullup - irq 0xbc = 0x01 - # SIO pin set 1 alternate function - #irq 0xc0 = 0x0 - # SIO pin set 2 mixed function - irq 0xc1 = 0x43 - # SIO pin set 3 mixed function - irq 0xc2 = 0x20 - # SIO pin set 4 alternate function - #irq 0xc3 = 0x0 - # SIO pin set 1 input mode - #irq 0xc8 = 0x0 - # SIO pin set 2 input mode - irq 0xc9 = 0x0 - # SIO pin set 4 input mode - #irq 0xcb = 0x0 - # Generate SMI# on EC IRQ - #irq 0xf0 = 0x10 - # SMI# level trigger - #irq 0xf1 = 0x40 - # HWMON alert beep pin location - irq 0xf6 = 0x28 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR + #0x24 = 0x1a + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO, SPI flash + # pin 84 is not GP10 + irq 0x25 = 0x0 + # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x26 = 0x43 + # pin 13 is GP35 + irq 0x27 = 0x20 + # pin 70 is not GP46 + #irq 0x28 = 0x0 + # pin 6,3,128,127,126 is GP63,64,65,66,67 + irq 0x29 = 0x81 + # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V + #irq 0x2c = 0x1f + # Simple I/O base + io 0x62 = 0x800 + # Serial Flash I/O (SPI only) + io 0x64 = 0x820 + # watch dog force timeout (parallel flash only) + #irq 0x71 = 0x1 + # No WDT interrupt + irq 0x72 = 0x0 + # GPIO pin set 1 disable internal pullup + irq 0xb8 = 0x0 + # GPIO pin set 5 enable internal pullup + irq 0xbc = 0x01 + # SIO pin set 1 alternate function + #irq 0xc0 = 0x0 + # SIO pin set 2 mixed function + irq 0xc1 = 0x43 + # SIO pin set 3 mixed function + irq 0xc2 = 0x20 + # SIO pin set 4 alternate function + #irq 0xc3 = 0x0 + # SIO pin set 1 input mode + #irq 0xc8 = 0x0 + # SIO pin set 2 input mode + irq 0xc9 = 0x0 + # SIO pin set 4 input mode + #irq 0xcb = 0x0 + # Generate SMI# on EC IRQ + #irq 0xf0 = 0x10 + # SMI# level trigger + #irq 0xf1 = 0x40 + # HWMON alert beep pin location + irq 0xf6 = 0x28 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off # CIR + end end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM -#WTF?!? We already have device pci 1.1 in the section above - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + end + device pci 1.1 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # SM + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AUDIO + device pci 8.0 on end # NIC + device pci 9.0 off end # N/A + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end #device pci 18.0 device pci 18.0 on end # Link 1 - device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end + +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 on end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end + end #root_complex

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[PATCH]kconfig cleanup (failover config flags)
by Patrick Georgi 03 Oct '09

03 Oct '09

Hi, attached patch moves the failover configuration symbols to a global file, defined as bool, defaulting to false. Given that Kconfig doesn't support failover, there hardly will be a reason to enable it, and if there is, they can still be enabled as needed. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

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coreboot October 2009