coreboot October 2009

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534 discussions

[PATCH] serialice for M2V-MX SE
by Rudolf Marek 10 Oct '09

10 Oct '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, I did small hackaton today evening. Attached patch adds support for the M2V-MX SE board and also enabled the password for MSR on AMD arch. You will need to use the XMM stack version because I did not want to change the romcc. It rocks ;) Orig BIOS works until it tries to reset itself: IO: inb 0cff => 01 IO: outl 0cf8 <= 8000004c PCI 0:00.0 R.4c IO: outb 0cff <= 00 IO: outb 0cf9 <= 02 IO: outb 0cf9 <= 06 And it fails of course... The patch may need to switch off default MB. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkrPnWAACgkQ3J9wPJqZRNVkDQCgxdVkTRQSbU1DfN/oApwSFvwj PgkAoNeCkkVmcBL/QHO3fPUM5ffCAITx =IHBU -----END PGP SIGNATURE-----

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[v2] r4757 - trunk/coreboot-v2/src/mainboard/emulation/qemu-x86
by svn＠coreboot.org 10 Oct '09

10 Oct '09

Author: uwe Date: 2009-10-10 18:19:12 +0200 (Sat, 10 Oct 2009) New Revision: 4757 Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig Log: Drop "select CONSOLE_SERIAL8250" from QEMU, it's default-y anyway. Tested on QEMU. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig 2009-10-09 20:13:43 UTC (rev 4756) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig 2009-10-10 16:19:12 UTC (rev 4757) @@ -4,7 +4,6 @@ select CPU_I586 select SOUTHBRIDGE_INTEL_I82371EB select CPU_EMULATION_QEMU_X86 - select CONSOLE_SERIAL8250 config MAINBOARD_DIR string

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Re: [coreboot] [v2] r4745 - in trunk/coreboot-v2/src/cpu/intel: socket_PGA370 socket_mPGA479M socket_mPGA604
by Stefan Reinauer 10 Oct '09

10 Oct '09

svn(a)coreboot.org wrote: > Author: rminnich > Date: 2009-10-08 18:06:09 +0200 (Thu, 08 Oct 2009) > New Revision: 4745 > > Modified: > trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig > trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig > trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig > Log: > Set MMX and SSE where needed. Note that many boards don't even bother > with this as many boards (AMD in particular) use CAR. > > This list determined by a series of greps etc. on mainboards, no humans > were harmed in the making of this list. > > Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> > > Acked-by: Peter Stuge <peter(a)stuge.se> > Isn't MMX or SSE something attached to a given CPU rather than a socket? I see the correctness of our CPU model being compromised here.. > Modified: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-10-08 15:12:31 UTC (rev 4744) > +++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-10-08 16:06:09 UTC (rev 4745) > @@ -21,3 +21,4 @@ > config CPU_INTEL_SOCKET_PGA370 > bool > default n > + select MMX > > Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-10-08 15:12:31 UTC (rev 4744) > +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-10-08 16:06:09 UTC (rev 4745) > @@ -3,3 +3,5 @@ > default n > select CPU_INTEL_MODEL_69X > select CPU_INTEL_MODEL_6DX > + select MMX > + select SSE > > Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-10-08 15:12:31 UTC (rev 4744) > +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-10-08 16:06:09 UTC (rev 4745) > @@ -4,3 +4,5 @@ > select CPU_INTEL_MODEL_F2X > select CPU_INTEL_MODEL_F3X > select CPU_INTEL_MODEL_F4X > + select MMX > + select SSE > > >

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SeaBIOS VGA failure after ctrl-alt-delete
by Myles Watson 10 Oct '09

10 Oct '09

Kevin, SeaBIOS initializes my VGA correctly the first time through, but if I do ctrl-alt-delete, the screen is no longer updated. Do you have any suggestions as to how to fix it? Here's the snippet: Attempting to map option rom on dev 02:00.0 Option rom sizing returned f5000000 fffe0000 Inspecting possible rom at 0xf5000000 (dv=014110de bdf=200) Copying option rom (size 63488) from 0xf5000000 to c0000 Checking rom 0x000c0000 (sig aa55 size 124) Found option rom with bad checksum: loc=0x000c0000 len=63488 sum=7e The last line is the only new one. The others are exactly the same. This is another difference, but it is apparently unrelated to VGA: powerup iobase=1f0 st=50 powerup iobase=1f0 st=50 ata_detect ataid=0 sc=55 sn=aa dh=a0 The first time, st=0. Thanks, Myles

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[PATCH] more warnings
by Myles Watson 10 Oct '09

10 Oct '09

Kill a few dozen more warnings so I can see when I break things. 1. Add const when functions are passed quoted strings. 2. Remove redundant dev_root declaration and move its documentation. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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Re: [coreboot] [v2] r4755 - in trunk/coreboot-v2/src: mainboard/dell/s1850 southbridge/intel/i82801er
by Peter Stuge 09 Oct '09

09 Oct '09

svn(a)coreboot.org wrote: > +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-09 20:07:48 UTC (rev 4755) .. > @@ -278,12 +259,17 @@ > w = inw(0x866); > outw(w|2, 0x866); > > +#if 0 > + /*seriaice shows > + dell does this so leave it here so I don't forget > + */ > /* SMBUS */ > pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); > > /* unknown */ > b = inb(0x8c2); > outb(0xdf, 0x8c2); > +#endif Maybe this should be deleted until it's known to be neccessary? //Peter

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[PATCH] xmmstack fixes
by Rudolf Marek 09 Oct '09

09 Oct '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, I added support for pushl xxx(%esp) instruction and also I managed to create smarter wrapper code which means 10% drop in size (measured if -O0 is used). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkrPdyAACgkQ3J9wPJqZRNWhGwCeJcqRNRfZJf889PcP/RFhychk SUoAn2lcBzedRFFpxOcBwDg34VluHGUs =D22D -----END PGP SIGNATURE-----

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[v2] r4756 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/include/arch cpu/amd/model_fxx devices include/device include/pc80 mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/asus/m2v-mx_se mainboard/gigabyte/m57sli mainboard/iwill/dk8_htx mainboard/kontron/986lcd-m mainboard/technexion/tim8690 mainboard/tyan/s2891 mainboard/tyan/s2892 mainboard/tyan/s2895 northbridge/amd/amdk8 pc80
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: myles Date: 2009-10-09 22:13:43 +0200 (Fri, 09 Oct 2009) New Revision: 4756 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c trunk/coreboot-v2/src/arch/i386/boot/acpigen.c trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h trunk/coreboot-v2/src/arch/i386/include/arch/acpigen.h trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c trunk/coreboot-v2/src/devices/root_device.c trunk/coreboot-v2/src/include/device/device.h trunk/coreboot-v2/src/include/pc80/mc146818rtc.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c trunk/coreboot-v2/src/pc80/mc146818rtc.c Log: Add const to get rid of some warnings when passing quoted strings. Remove an unused extern declaration. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -224,11 +224,11 @@ /* this can be overriden by platform ACPI setup code, if it calls acpi_create_ssdt_generator */ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long current, - char *oem_table_id) { + const char *oem_table_id) { return current; } -void acpi_create_ssdt_generator(acpi_header_t *ssdt, char *oem_table_id) +void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) { unsigned long current=(unsigned long)ssdt+sizeof(acpi_header_t); memset((void *)ssdt, 0, sizeof(acpi_header_t)); Modified: trunk/coreboot-v2/src/arch/i386/boot/acpigen.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpigen.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/arch/i386/boot/acpigen.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -114,7 +114,7 @@ return 9; } -int acpigen_write_name_byte(char *name, uint8_t val) +int acpigen_write_name_byte(const char *name, uint8_t val) { int len; len = acpigen_write_name(name); @@ -122,7 +122,7 @@ return len; } -int acpigen_write_name_dword(char *name, uint32_t val) +int acpigen_write_name_dword(const char *name, uint32_t val) { int len; len = acpigen_write_name(name); @@ -130,7 +130,7 @@ return len; } -int acpigen_write_name_qword(char *name, uint64_t val) +int acpigen_write_name_qword(const char *name, uint64_t val) { int len; len = acpigen_write_name(name); @@ -138,7 +138,7 @@ return len; } -int acpigen_emit_stream(char *data, int size) +int acpigen_emit_stream(const char *data, int size) { int i; for (i = 0; i < size; i++) { @@ -152,7 +152,7 @@ and 5.3 of ACPI specs 3.0 for details */ -static int acpigen_emit_simple_namestring(char *name) { +static int acpigen_emit_simple_namestring(const char *name) { int i, len = 0; char ud[] = "____"; for (i = 0; i < 4; i++) { @@ -166,7 +166,7 @@ return len; } -static int acpigen_emit_double_namestring(char *name, int dotpos) { +static int acpigen_emit_double_namestring(const char *name, int dotpos) { int len = 0; /* mark dual name prefix */ len += acpigen_emit_byte(0x2e); @@ -175,7 +175,7 @@ return len; } -static int acpigen_emit_multi_namestring(char *name) { +static int acpigen_emit_multi_namestring(const char *name) { int len = 0, count = 0; unsigned char *pathlen; /* mark multi name prefix */ @@ -199,9 +199,9 @@ } -int acpigen_emit_namestring(char *namepath) { +int acpigen_emit_namestring(const char *namepath) { int dotcount = 0, i; - int dotpos; + int dotpos = 0; int len = 0; /* we can start with a \ */ @@ -237,7 +237,7 @@ return len; } -int acpigen_write_name(char *name) +int acpigen_write_name(const char *name) { int len; /* name op */ @@ -245,7 +245,7 @@ return len + acpigen_emit_namestring(name); } -int acpigen_write_scope(char *name) +int acpigen_write_scope(const char *name) { int len; /* scope op */ Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpi.h 2009-10-09 20:13:43 UTC (rev 4756) @@ -336,9 +336,9 @@ unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_srat(unsigned long current); unsigned long acpi_fill_slit(unsigned long current); -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id); -void acpi_create_ssdt_generator(acpi_header_t *ssdt, char *oem_table_id); -void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt); +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id); +void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); /* These can be used by the target port */ u8 acpi_checksum(u8 *table, u32 length); Modified: trunk/coreboot-v2/src/arch/i386/include/arch/acpigen.h =================================================================== --- trunk/coreboot-v2/src/arch/i386/include/arch/acpigen.h 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/arch/i386/include/arch/acpigen.h 2009-10-09 20:13:43 UTC (rev 4756) @@ -28,15 +28,15 @@ int acpigen_write_package(int nr_el); int acpigen_write_byte(unsigned int data); int acpigen_emit_byte(unsigned char data); -int acpigen_emit_stream(char *data, int size); -int acpigen_emit_namestring(char *namepath); +int acpigen_emit_stream(const char *data, int size); +int acpigen_emit_namestring(const char *namepath); int acpigen_write_dword(unsigned int data); int acpigen_write_qword(uint64_t data); -int acpigen_write_name(char *name); -int acpigen_write_name_dword(char *name, uint32_t val); -int acpigen_write_name_qword(char *name, uint64_t val); -int acpigen_write_name_byte(char *name, uint8_t val); -int acpigen_write_scope(char *name); +int acpigen_write_name(const char *name); +int acpigen_write_name_dword(const char *name, uint32_t val); +int acpigen_write_name_qword(const char *name, uint64_t val); +int acpigen_write_name_byte(const char *name, uint8_t val); +int acpigen_write_scope(const char *name); int acpigen_write_PPC(u8 nr); int acpigen_write_empty_PCT(void); int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/processor_name.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -42,7 +42,7 @@ */ #if CONFIG_K8_REV_F_SUPPORT == 0 -static char *processor_names[]={ +static const char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, /* 0x04 */ "AMD Athlon(tm) 64 Processor XX00+", Modified: trunk/coreboot-v2/src/devices/root_device.c =================================================================== --- trunk/coreboot-v2/src/devices/root_device.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/devices/root_device.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -182,11 +182,3 @@ .scan_bus = root_dev_scan_bus, .reset_bus = root_dev_reset, }; - -/** - * @brief The root of device tree. - * - * This is the root of the device tree. The device tree is defined in the - * static.c file and is generated by config tool during compile time. - */ -extern struct device dev_root; Modified: trunk/coreboot-v2/src/include/device/device.h =================================================================== --- trunk/coreboot-v2/src/include/device/device.h 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/include/device/device.h 2009-10-09 20:13:43 UTC (rev 4756) @@ -90,7 +90,11 @@ void *chip_info; }; -extern struct device dev_root; /* root bus */ +/** + * This is the root of the device tree. The device tree is defined in the + * static.c file and is generated by the config tool at compile time. + */ +extern struct device dev_root; extern struct device *all_devices; /* list of all devices */ Modified: trunk/coreboot-v2/src/include/pc80/mc146818rtc.h =================================================================== --- trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/include/pc80/mc146818rtc.h 2009-10-09 20:13:43 UTC (rev 4756) @@ -95,9 +95,9 @@ #if !defined(ASSEMBLY) void rtc_init(int invalid); #if CONFIG_USE_OPTION_TABLE == 1 -int get_option(void *dest, char *name); +int get_option(void *dest, const char *name); #else -static inline int get_option(void *dest, char *name) { return -2; } +static inline int get_option(void *dest, const char *name) { return -2; } #endif #endif Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -123,7 +123,7 @@ } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -123,7 +123,7 @@ } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -179,7 +179,7 @@ } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); return (unsigned long) (acpigen_get_current()); } Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -82,7 +82,7 @@ return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -93,7 +93,7 @@ return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -182,7 +182,7 @@ } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); return (unsigned long) (acpigen_get_current()); } Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -176,7 +176,7 @@ return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -123,7 +123,7 @@ } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -75,7 +75,7 @@ return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -75,7 +75,7 @@ return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/acpi_tables.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -86,7 +86,7 @@ return current; } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -248,7 +248,7 @@ return len; } -static int k8acpi_write_pci_data(int dlen, char *name, int offset) { +static int k8acpi_write_pci_data(int dlen, const char *name, int offset) { device_t dev; uint32_t dword; int len, lenp, i; Modified: trunk/coreboot-v2/src/pc80/mc146818rtc.c =================================================================== --- trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-10-09 20:07:48 UTC (rev 4755) +++ trunk/coreboot-v2/src/pc80/mc146818rtc.c 2009-10-09 20:13:43 UTC (rev 4756) @@ -231,7 +231,7 @@ return 0; } -int get_option(void *dest, char *name) +int get_option(void *dest, const char *name) { extern struct cmos_option_table option_table; struct cmos_option_table *ct;

1 0

patch: enable spd for dram on s1850
by ron minnich 09 Oct '09

09 Oct '09

attached.

2 2

[v2] r4755 - in trunk/coreboot-v2/src: mainboard/dell/s1850 southbridge/intel/i82801er
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: rminnich Date: 2009-10-09 22:07:48 +0200 (Fri, 09 Oct 2009) New Revision: 4755 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c trunk/coreboot-v2/src/mainboard/dell/s1850/s1850_fixups.c trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c Log: This change allows us to see the spd on the s850, finally. There is an i2c mux out there. We found it using a user level program that, as usual, began by inverting all gpios until we found out what we needed to know. In the end, we just set up the GPIOs as the factory bios does. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-09 17:40:34 UTC (rev 4754) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-09 20:07:48 UTC (rev 4755) @@ -65,25 +65,6 @@ } static inline int spd_read_byte(unsigned device, unsigned address) { - /* fake it out for this board */ - switch(device) { - case 0x52: - case 0x53: - print_debug("FAKE"); - device = 0x50; - break; - case 0x50: - case 0x51: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - print_debug("57"); - device = 0x57; - break; - default: - die("BAD DEV IN spd_read_byte"); - } return smbus_read_byte(device, address); } @@ -278,12 +259,17 @@ w = inw(0x866); outw(w|2, 0x866); +#if 0 + /*seriaice shows + dell does this so leave it here so I don't forget + */ /* SMBUS */ pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); /* unknown */ b = inb(0x8c2); outb(0xdf, 0x8c2); +#endif /* another device enable? */ b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); @@ -314,11 +300,12 @@ uart_init(); console_init(); + /* stuff we seem to need */ - pc8374_enable_dev(PC8374_KBCK, 0); + pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0); /* GPIOs */ - pc8374_enable_dev(PC8374_GPIO, 0xc20); + pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20); /* keep this in mind. SerialICE-hlp: outb 002e <= 23 @@ -351,7 +338,7 @@ #if 1 enable_smbus(); #endif -#if 0 +#if 1 // dump_spd_registers(&cpu[0]); int i; for(i = 0; i < 1; i++) { Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/s1850_fixups.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/s1850_fixups.c 2009-10-09 17:40:34 UTC (rev 4754) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/s1850_fixups.c 2009-10-09 20:07:48 UTC (rev 4755) @@ -33,6 +33,26 @@ * we leave it enabled and visible in config space -- 8f66 */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66); + /* GPIOs -- needed, possibly, for SPD */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10); + + /* now the fun begins ... enable the GPIOs as done on factory */ + /* factory config from IO ports + * It has a few more things enabled than default! + */ + outl(0x1ae0f183, 0x880); + outl(0x1b00ffff, 0x884); + outl(0x131f0000, 0x88c); + outl(0x00000000, 0x894); + outl(0x00040000, 0x898); + outl(0x00000000, 0x8a4); + outl(0x00000000, 0x8a8); + outl(0x000031c0, 0x8ac); + outl(0x00000007, 0x8b0); + outl(0x00000304, 0x8b4); + outl(0x00030303, 0x8b8); + } Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c 2009-10-09 17:40:34 UTC (rev 4754) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c 2009-10-09 20:07:48 UTC (rev 4755) @@ -9,6 +9,7 @@ print_spew("SMBus controller enabled\r\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + print_debug_hex32(pci_read_config32(dev, 0x20)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */

1 0

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coreboot October 2009