coreboot October 2009

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[PATCH] Kconfig extra variables
by Myles Watson 09 Oct '09

09 Oct '09

Remove a couple of unused variables. Kbuildall-tested. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[PATCH] Kconfig simplification
by Myles Watson 09 Oct '09

09 Oct '09

Remove default n statements to simplify .config files. I know the superio ones were put in recently, but I didn't realize what it did to the .config files. Without these extra lines it makes it much easier to compare ldoptions from Kconfig and ldoptions from newconfig. It is also helpful to see which components are selected without the clutter of the unselected components. Some of the ones I couldn't fix were CONFIG_VENDOR_* and CONFIG_ROMSIZE_* since they are part of choice menus. If someone knows how to make only the chosen vendor and ROM size show up, that would be nice. wc output Before patch: 316 1167 10370 .config 274 822 8498 build/ldoptions After patch: 227 722 6527 .config 185 555 5367 build/ldoptions kbuildall tested. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4754 - in trunk/coreboot-v2/src: arch/i386 console
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: myles Date: 2009-10-09 19:40:34 +0200 (Fri, 09 Oct 2009) New Revision: 4754 Modified: trunk/coreboot-v2/src/arch/i386/Kconfig trunk/coreboot-v2/src/console/Kconfig Log: Remove extra CONFIG variables. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/i386/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) +++ trunk/coreboot-v2/src/arch/i386/Kconfig 2009-10-09 17:40:34 UTC (rev 4754) @@ -27,19 +27,6 @@ default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256 default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128 -config PAYLOAD_SIZE - hex - default 0x0 - -config ROM_PAYLOAD_START - hex - default 0xffc00000 if COREBOOT_ROMSIZE_KB_4096 - default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048 - default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024 - default 0xfff80000 if COREBOOT_ROMSIZE_KB_512 - default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256 - default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128 - config ROM_IMAGE_SIZE hex default 0x400000 if COREBOOT_ROMSIZE_KB_4096 Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) +++ trunk/coreboot-v2/src/console/Kconfig 2009-10-09 17:40:34 UTC (rev 4754) @@ -13,14 +13,9 @@ depends on CONSOLE_SERIAL8250 default 0x3f8 -config SERIAL_SET_SPEED - bool "Override the serial port BAUD rate" - default y - depends on CONSOLE_SERIAL8250 - config TTYS0_BAUD int "Serial port BAUD rate" - depends on SERIAL_SET_SPEED + depends on CONSOLE_SERIAL8250 default 115200 # TODO: Allow user-friendly selection of settings other than 8n1.

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[v2] r4753 - in trunk/coreboot-v2/src: cpu cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/model_gx1 cpu/amd/model_gx2 cpu/amd/model_lx cpu/amd/sc520 cpu/amd/socket_754 cpu/amd/socket_939 cpu/amd/socket_940 cpu/amd/socket_AM2 cpu/amd/socket_AM2r2 cpu/amd/socket_F cpu/amd/socket_F_1207 cpu/amd/socket_S1G1 cpu/emulation/qemu-x86 cpu/intel/bga956 cpu/intel/ep80579 cpu/intel/model_1067x cpu/intel/model_69x cpu/intel/model_6dx cpu/intel/model_6ex cpu/intel/model_6xx cpu/intel/model_f0x cpu/intel/model_f
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: myles Date: 2009-10-09 19:39:35 +0200 (Fri, 09 Oct 2009) New Revision: 4753 Modified: trunk/coreboot-v2/src/cpu/Kconfig trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig trunk/coreboot-v2/src/cpu/amd/model_lx/Kconfig trunk/coreboot-v2/src/cpu/amd/sc520/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig trunk/coreboot-v2/src/cpu/via/model_c3/Kconfig trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig trunk/coreboot-v2/src/northbridge/amd/lx/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig trunk/coreboot-v2/src/northbridge/via/cn400/Kconfig trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig trunk/coreboot-v2/src/southbridge/amd/amd8131/Kconfig trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig trunk/coreboot-v2/src/southbridge/amd/rs690/Kconfig trunk/coreboot-v2/src/southbridge/amd/sb600/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Kconfig trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig trunk/coreboot-v2/src/southbridge/via/vt8237r/Kconfig trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig trunk/coreboot-v2/src/superio/fintek/Kconfig trunk/coreboot-v2/src/superio/intel/Kconfig trunk/coreboot-v2/src/superio/ite/Kconfig trunk/coreboot-v2/src/superio/nsc/Kconfig trunk/coreboot-v2/src/superio/serverengines/Kconfig trunk/coreboot-v2/src/superio/smsc/Kconfig trunk/coreboot-v2/src/superio/via/Kconfig trunk/coreboot-v2/src/superio/winbond/Kconfig Log: Remove default n statements to simplify .config and ldoptions files. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -30,19 +30,14 @@ default y if MAX_CPUS != 1 default n +# Set MMX and SSE in socket or model if the CPU has them. +# If all CPUs for the socket have MMX or SSE, set them there. +# These options are only needed for boards compiled with romcc. config MMX bool - default n - help - Set this in socket or model if the CPU has MMX. - If the CPUs for the socket always have MMX, set it there. config SSE bool - default n - help - Set this in socket or model if the CPU has SSE. - If the CPUs for the socket always have MX, set it there. config VAR_MTRR_HOLE bool Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_10XXX bool - default n config HAVE_INIT_TIMER bool Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_MODEL_FXX bool - default n config HAVE_INIT_TIMER bool Modified: trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/model_gx1/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,5 +20,4 @@ config CPU_AMD_GX1 bool - default n Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config CPU_AMD_GX2 bool - default n Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_AMD_LX bool - default n Modified: trunk/coreboot-v2/src/cpu/amd/sc520/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/sc520/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/sc520/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_AMD_SC520 bool - default n Modified: trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_754/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_754 bool - default n select CPU_AMD_MODEL_FXX config CPU_SOCKET_TYPE Modified: trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_939 bool - default n select CPU_AMD_MODEL_FXX config CPU_SOCKET_TYPE Modified: trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_940 bool - default n select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_AM2 bool - default n select K8_REV_F_SUPPORT # Opteron K8 1G HT support select K8_HT_FREQ_1G_SUPPORT Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_AM2R2 bool - default n select CPU_AMD_MODEL_10XXX select HT3_SUPPORT select CAR_FAM10 Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_F bool - default n select K8_REV_F_SUPPORT select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_F_1207 bool - default n select CPU_AMD_MODEL_10XXX config CPU_SOCKET_TYPE Modified: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_AMD_SOCKET_S1G1 bool - default n select K8_REV_F_SUPPORT select K8_HT_FREQ_1G_SUPPORT select CPU_AMD_MODEL_FXX Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_EMULATION_QEMU_X86 bool - default n Modified: trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/bga956/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_INTEL_SOCKET_BGA956 bool - default n select CPU_INTEL_CORE2 Modified: trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config CPU_INTEL_EP80579 bool - default n Modified: trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_1067x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_CORE2 bool - default n select SMP select HAVE_MOVNTI Modified: trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_69x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_69X bool - default n select SMP Modified: trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_6dx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_6DX bool - default n select SMP Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_INTEL_CORE bool - default n select SMP Modified: trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config CPU_INTEL_MODEL_6XX bool - default n select SMP Modified: trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_f0x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_F0X bool - default n select SMP select HAVE_MOVNTI Modified: trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_f1x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_F1X bool - default n select SMP select HAVE_MOVNTI Modified: trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_f2x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_F2X bool - default n select SMP select HAVE_MOVNTI Modified: trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_f3x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_F3X bool - default n select SMP select HAVE_MOVNTI Modified: trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/model_f4x/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_MODEL_F4X bool - default n select SMP select HAVE_MOVNTI Modified: trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/slot_2/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,5 +20,4 @@ config CPU_INTEL_SLOT_2 bool - default n Modified: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,5 +20,4 @@ config CPU_INTEL_SOCKET_PGA370 bool - default n select MMX Modified: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config CPU_INTEL_SOCKET_MFCPGA478 bool - default n Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA478/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config CPU_INTEL_SOCKET_MPGA478 bool - default n select CPU_INTEL_MODEL_69X select CPU_INTEL_MODEL_6DX Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA479M/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_INTEL_SOCKET_MPGA479M bool - default n select CPU_INTEL_MODEL_69X select CPU_INTEL_MODEL_6DX select MMX Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA603/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_INTEL_SOCKET_MPGA603 bool - default n select CPU_INTEL_MODEL_F0X select CPU_INTEL_MODEL_F1X select CPU_INTEL_MODEL_F2X Modified: trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/intel/socket_mPGA604/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config CPU_INTEL_SOCKET_MPGA604 bool - default n select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X Modified: trunk/coreboot-v2/src/cpu/via/model_c3/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c3/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/via/model_c3/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config CPU_VIA_C3 bool - default n Modified: trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config CPU_VIA_C7 bool - default n Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,7 +19,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 bool - default n select HAVE_HIGH_TABLES config AGP_APERTURE_SIZE Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/root_complex/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX bool - default n Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,7 +20,6 @@ config NORTHBRIDGE_AMD_AMDK8 bool select HAVE_HIGH_TABLES - default n config AGP_APERTURE_SIZE hex Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,4 +19,3 @@ config NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX bool - default n Modified: trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/gx1/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,5 +20,4 @@ config NORTHBRIDGE_AMD_GX1 bool - default n Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config NORTHBRIDGE_AMD_GX2 bool - default n Modified: trunk/coreboot-v2/src/northbridge/amd/lx/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/lx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/amd/lx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_AMD_LX bool - default n config HAVE_HIGH_TABLES bool Modified: trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/e7501/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_E7501 bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/e7520/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_E7520 bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/e7525/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_E7525 bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_I3100 bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i440bx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,6 +20,5 @@ config NORTHBRIDGE_INTEL_I440BX bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,6 +20,5 @@ config NORTHBRIDGE_INTEL_I82810 bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_I82830 bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i855gme/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_I855GME bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i855pm/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,5 +1,4 @@ config NORTHBRIDGE_INTEL_I855PM bool - default n select HAVE_HIGH_TABLES Modified: trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,4 +20,3 @@ config NORTHBRIDGE_INTEL_I945 bool select HAVE_HIGH_TABLES - default n Modified: trunk/coreboot-v2/src/northbridge/via/cn400/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn400/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/via/cn400/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_VIA_CN400 bool - default n config FALLBACK_SIZE int Modified: trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/via/cn700/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_VIA_CN700 bool - default n select HAVE_HIGH_TABLES config FALLBACK_SIZE Modified: trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_VIA_CX700 bool - default n # this is done by the northbridge's vgabios.c already config VGA_ROM_RUN Modified: trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/via/vt8601/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_VIA_VT8601 bool - default n select HAVE_HIGH_TABLES config FALLBACK_SIZE Modified: trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/via/vt8623/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_VIA_VT8623 bool - default n select HAVE_HIGH_TABLES config FALLBACK_SIZE Modified: trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/northbridge/via/vx800/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config NORTHBRIDGE_VIA_VX800 bool - default n config FALLBACK_SIZE int Modified: trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_AMD_AMD8111 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/amd8131/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8131/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/amd8131/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_AMD_AMD8131 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/amd8132/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_AMD_AMD8132 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/amd8151/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_AMD_AMD8151 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/cs5530/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,7 +20,6 @@ config SOUTHBRIDGE_AMD_CS5530 bool - default n menu "AMD Geode GX1 video support" depends on SOUTHBRIDGE_AMD_CS5530 Modified: trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/cs5535/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_AMD_CS5535 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_AMD_CS5536 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_AMD_RS690 bool - default n Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/sb600/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/amd/sb600/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_AMD_SB600 bool - default n Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm21000/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_BROADCOM_BCM21000 bool - default n Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5780/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_BROADCOM_BCM5780 bool - default n Modified: trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/broadcom/bcm5785/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/esb6300/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_ESB6300 bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_I3100 bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config SOUTHBRIDGE_INTEL_I82371EB bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82801ca/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_I82801CA bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82801dbm/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_I82801DBM bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82801er/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_I82801ER bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_INTEL_I82801GX bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -20,5 +20,4 @@ config SOUTHBRIDGE_INTEL_I82801XX bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/i82870/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_I82870 bool - default n Modified: trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/intel/pxhd/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_INTEL_PXHD bool - default n Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,6 +1,5 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool - default n config HAVE_HARD_RESET bool Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_NVIDIA_MCP55 bool - default n Modified: trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/ricoh/rl5c476/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_RICOH_RL5C476 bool - default n Modified: trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/sis/sis966/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_SIS_SIS966 bool - default n Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,4 +1,3 @@ config SOUTHBRIDGE_VIA_K8T890 bool - default n Modified: trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/via/vt8231/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_VIA_VT8231 bool - default n Modified: trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/via/vt8235/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,5 +19,4 @@ config SOUTHBRIDGE_VIA_VT8235 bool - default n Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -19,8 +19,8 @@ config SOUTHBRIDGE_VIA_VT8237R bool - default n config EPIA_VT8237R_INIT bool default n + depends on SOUTHBRIDGE_VIA_VT8237R Modified: trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/southbridge/winbond/w83c553/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SOUTHBRIDGE_WINBOND_W83C553 bool - default n Modified: trunk/coreboot-v2/src/superio/fintek/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/fintek/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/fintek/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SUPERIO_FINTEK_F71805F bool - default n Modified: trunk/coreboot-v2/src/superio/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/intel/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/intel/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SUPERIO_INTEL_I3100 bool - default n Modified: trunk/coreboot-v2/src/superio/ite/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/ite/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/ite/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,21 +1,14 @@ config SUPERIO_ITE_IT8661F bool - default n config SUPERIO_ITE_IT8671F bool - default n config SUPERIO_ITE_IT8673F bool - default n config SUPERIO_ITE_IT8705F bool - default n config SUPERIO_ITE_IT8712F bool - default n config SUPERIO_ITE_IT8716F bool - default n config SUPERIO_ITE_IT8718F bool - default n Modified: trunk/coreboot-v2/src/superio/nsc/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/nsc/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/nsc/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,27 +1,18 @@ config SUPERIO_NSC_PC8374 bool - default n config SUPERIO_NSC_PC87309 bool - default n config SUPERIO_NSC_PC87351 bool - default n config SUPERIO_NSC_PC87360 bool - default n config SUPERIO_NSC_PC87366 bool - default n config SUPERIO_NSC_PC87417 bool - default n config SUPERIO_NSC_PC87427 bool - default n config SUPERIO_NSC_PC97307 bool - default n config SUPERIO_NSC_PC97317 bool - default n Modified: trunk/coreboot-v2/src/superio/serverengines/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/serverengines/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SUPERIO_SERVERENGINES_PILOT bool - default n Modified: trunk/coreboot-v2/src/superio/smsc/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,18 +1,12 @@ config SUPERIO_SMSC_FDC37M60X bool - default n config SUPERIO_SMSC_LPC47B272 bool - default n config SUPERIO_SMSC_LPC47B397 bool - default n config SUPERIO_SMSC_LPC47M10X bool - default n config SUPERIO_SMSC_LPC47N217 bool - default n config SUPERIO_SMSC_SMSCSUPERIO bool - default n Modified: trunk/coreboot-v2/src/superio/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/via/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/via/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,3 +1,2 @@ config SUPERIO_VIA_VT1211 bool - default n Modified: trunk/coreboot-v2/src/superio/winbond/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/winbond/Kconfig 2009-10-09 15:22:35 UTC (rev 4752) +++ trunk/coreboot-v2/src/superio/winbond/Kconfig 2009-10-09 17:39:35 UTC (rev 4753) @@ -1,27 +1,18 @@ config SUPERIO_WINBOND_W83627DHG bool - default n config SUPERIO_WINBOND_W83627EHG bool - default n config SUPERIO_WINBOND_W83627HF bool - default n config SUPERIO_WINBOND_W83627THF bool - default n config SUPERIO_WINBOND_W83627THG bool - default n config SUPERIO_WINBOND_W83627UHG bool - default n config SUPERIO_WINBOND_W83697HF bool - default n config SUPERIO_WINBOND_W83977F bool - default n config SUPERIO_WINBOND_W83977TF bool - default n

1 0

[PATCH] CBFS decompress error
by Myles Watson 09 Oct '09

09 Oct '09

Move the ulzma prototype into cbfs.h Check the return value when decompressing. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> It's not 100% fixed, since the caller (cbfs_load_stage) if (cbfs_decompress(stage->compression, ((unsigned char *) stage) + sizeof(struct cbfs_stage), (void *) (u32) stage->load, stage->len)) return (void *) -1; returns -1 and then cbfs_and_run_core jumps to it. print_debug("Jumping to image.\r\n"); dst = cbfs_load_stage(filename); print_debug("Jumping to image.\r\n"); Why do we jump to a -1 instead of hanging? Thanks, Myles

5 9

[v2] r4752 - in trunk/coreboot-v2/src: include lib
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: myles Date: 2009-10-09 17:22:35 +0200 (Fri, 09 Oct 2009) New Revision: 4752 Modified: trunk/coreboot-v2/src/include/cbfs.h trunk/coreboot-v2/src/lib/cbfs.c Log: Move the ulzma prototype out of the function to make the code easier to read. Check the return value. Minor formatting and LAR -> CBFS. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/include/cbfs.h =================================================================== --- trunk/coreboot-v2/src/include/cbfs.h 2009-10-09 14:10:28 UTC (rev 4751) +++ trunk/coreboot-v2/src/include/cbfs.h 2009-10-09 15:22:35 UTC (rev 4752) @@ -52,7 +52,7 @@ #include <boot/coreboot_tables.h> /** These are standard values for the known compression alogrithms that coreboot knows about for stages and - payloads. Of course, other LAR users can use whatever + payloads. Of course, other CBFS users can use whatever values they want, as long as they understand them. */ #define CBFS_COMPRESS_NONE 0 Modified: trunk/coreboot-v2/src/lib/cbfs.c =================================================================== --- trunk/coreboot-v2/src/lib/cbfs.c 2009-10-09 14:10:28 UTC (rev 4751) +++ trunk/coreboot-v2/src/lib/cbfs.c 2009-10-09 15:22:35 UTC (rev 4752) @@ -29,6 +29,8 @@ #define ntohl(x) (x) #endif +unsigned long ulzma(unsigned char *src, unsigned char *dst); + int cbfs_decompress(int algo, void *src, void *dst, int len) { switch(algo) { @@ -36,15 +38,15 @@ memcpy(dst, src, len); return 0; - case CBFS_COMPRESS_LZMA: { - unsigned long ulzma(unsigned char *src, unsigned char *dst); - ulzma(src, dst); - } + case CBFS_COMPRESS_LZMA: + if (!ulzma(src, dst)) { + printk_err("CBFS: LZMA decompression failed!\n"); + return -1; + } return 0; default: - printk_info( "CBFS: Unknown compression type %d\n", - algo); + printk_info( "CBFS: Unknown compression type %d\n", algo); return -1; } }

1 0

[PATCH]kconfig for the remaining boards
by Patrick Georgi 09 Oct '09

09 Oct '09

Hi, attached patch contains the kconfig stuff for the remaining boards. All of them can be configured now, and except for the three Fam10 boards, all build, too. The next step will be to ensure that the configuration of a Kconfig build matches that of a newconfig build. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

3 2

[v2] r4751 - in trunk/coreboot-v2/src: drivers drivers/generic/debug mainboard/amd mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/norwich mainboard/amd/pistachio mainboard/amd/serengeti_cheetah_fam10 mainboard/digitallogic mainboard/digitallogic/adl855pc mainboard/digitallogic/msm586seg mainboard/digitallogic/msm800sev mainboard/supermicro mainboard/supermicro/h8dme mainboard/supermicro/h8dmr mainboard/supermicro/h8dmr_fam10 mainboard/supermicro/x6dai_g mainboard/supermicro/x6dhe_g mainb
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: oxygene Date: 2009-10-09 16:10:28 +0200 (Fri, 09 Oct 2009) New Revision: 4751 Added: trunk/coreboot-v2/src/drivers/generic/debug/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/db800/Kconfig trunk/coreboot-v2/src/mainboard/amd/db800/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/dbm690t/Kconfig trunk/coreboot-v2/src/mainboard/amd/dbm690t/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/norwich/Kconfig trunk/coreboot-v2/src/mainboard/amd/norwich/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/pistachio/Kconfig trunk/coreboot-v2/src/mainboard/amd/pistachio/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Makefile.inc trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Makefile.inc trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Makefile.inc trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc Modified: trunk/coreboot-v2/src/drivers/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/Kconfig trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig Log: Remaining boards are Kconfig'd now. Whether they work or not still depends on how close the configuration options are to what they should be. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/drivers/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) +++ trunk/coreboot-v2/src/drivers/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -1,2 +1,3 @@ subdirs-y += pci +subdirs-y += generic/debug subdirs-y += ati/ragexl Added: trunk/coreboot-v2/src/drivers/generic/debug/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/generic/debug/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/drivers/generic/debug/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1 @@ +obj-$(CONFIG_DRIVERS_GENERIC_DEBUG) += debug_dev.o Modified: trunk/coreboot-v2/src/mainboard/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) +++ trunk/coreboot-v2/src/mainboard/amd/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -2,8 +2,13 @@ prompt "Mainboard model" depends on VENDOR_AMD +source "src/mainboard/amd/db800/Kconfig" +source "src/mainboard/amd/dbm690t/Kconfig" +source "src/mainboard/amd/norwich/Kconfig" +source "src/mainboard/amd/pistachio/Kconfig" +source "src/mainboard/amd/rumba/Kconfig" source "src/mainboard/amd/serengeti_cheetah/Kconfig" -source "src/mainboard/amd/rumba/Kconfig" +source "src/mainboard/amd/serengeti_cheetah_fam10/Kconfig" endchoice Added: trunk/coreboot-v2/src/mainboard/amd/db800/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,48 @@ +config BOARD_AMD_DB800 + bool "DB800" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default amd/db800 + depends on BOARD_AMD_DB800 + +config MAINBOARD_PART_NUMBER + string + default "DB800" + depends on BOARD_AMD_DB800 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_AMD_DB800 + +config IRQ_SLOT_COUNT + int + default 6 + depends on BOARD_AMD_DB800 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_AMD_DB800 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_AMD_DB800 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_AMD_DB800 Added: trunk/coreboot-v2/src/mainboard/amd/db800/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,31 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,104 @@ +config BOARD_AMD_DBM690T + bool "DBM690T" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_S1G1 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_RS690 + select SOUTHBRIDGE_AMD_SB600 + select SUPERIO_ITE_IT8712F + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default amd/dbm690t + depends on BOARD_AMD_DBM690T + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_AMD_DBM690T + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_AMD_DBM690T + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_AMD_DBM690T + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_AMD_DBM690T + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_AMD_DBM690T + +config LB_CKS_LOC + int + default 123 + depends on BOARD_AMD_DBM690T + +config MAINBOARD_PART_NUMBER + string + default "DBM690T" + depends on BOARD_AMD_DBM690T + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_AMD_DBM690T + +config MAX_CPUS + int + default 2 + depends on BOARD_AMD_DBM690T + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_AMD_DBM690T + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_AMD_DBM690T + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_AMD_DBM690T + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_AMD_DBM690T + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_AMD_DBM690T + +config USE_INIT + bool + default n + depends on BOARD_AMD_DBM690T + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_AMD_DBM690T Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/amd/norwich/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,47 @@ +config BOARD_AMD_NORWICH + bool "Norwich" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default amd/norwich + depends on BOARD_AMD_NORWICH + +config MAINBOARD_PART_NUMBER + string + default "NORWICH" + depends on BOARD_AMD_NORWICH + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_AMD_NORWICH + +config IRQ_SLOT_COUNT + int + default 6 + depends on BOARD_AMD_NORWICH + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_AMD_NORWICH + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_AMD_NORWICH + +config RAMBASE + hex + default 0x4000 + depends on BOARD_AMD_NORWICH Added: trunk/coreboot-v2/src/mainboard/amd/norwich/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,31 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,103 @@ +config BOARD_AMD_PISTACHIO + bool "Pistachio" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_AM2 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_RS690 + select SOUTHBRIDGE_AMD_SB600 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default amd/pistachio + depends on BOARD_AMD_PISTACHIO + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_AMD_PISTACHIO + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_AMD_PISTACHIO + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_AMD_PISTACHIO + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_AMD_PISTACHIO + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_AMD_PISTACHIO + +config LB_CKS_LOC + int + default 123 + depends on BOARD_AMD_PISTACHIO + +config MAINBOARD_PART_NUMBER + string + default "PISTACHIO" + depends on BOARD_AMD_PISTACHIO + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_AMD_PISTACHIO + +config MAX_CPUS + int + default 2 + depends on BOARD_AMD_PISTACHIO + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_AMD_PISTACHIO + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_AMD_PISTACHIO + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_AMD_PISTACHIO + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_AMD_PISTACHIO + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_AMD_PISTACHIO + +config USE_INIT + bool + default n + depends on BOARD_AMD_PISTACHIO + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_AMD_PISTACHIO Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,116 @@ +config BOARD_AMD_SERENGETI_CHEETAH_FAM10 + bool "Serengeti Cheetah (Fam10)" + select ARCH_X86 + select CPU_AMD_FAM10 + select CPU_AMD_SOCKET_F_1207 + select NORTHBRIDGE_AMD_AMDFAM10 + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8132 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + select AMDMCT + +config MAINBOARD_DIR + string + default amd/serengeti_cheetah_fam10 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config MAINBOARD_PART_NUMBER + string + default "Serengeti-Cheetah-Fam10" + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +# 6 * MAX_PHYSICAL_CPUS +config MAX_CPUS + int + default 48 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config MAX_PHYSICAL_CPUS + int + default 8 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config USE_INIT + bool + default n + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 + Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,85 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +# ./ssdt.o is in northbridge/amd/amdk8/Config.lb +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt4.o +driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) +++ trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -1 +1,10 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_DIGITAL_LOGIC + +source "src/mainboard/digitallogic/adl855pc/Kconfig" +source "src/mainboard/digitallogic/msm586seg/Kconfig" +source "src/mainboard/digitallogic/msm800sev/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,24 @@ +config BOARD_DIGITALLOGIC_ADL855PC + bool "ADL855PC" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA479M + select NORTHBRIDGE_INTEL_I855PM + select SOUTHBRIDGE_INTEL_I82801DBM + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select UDELAY_TSC + +config MAINBOARD_DIR + string + default digitallogic/adl855pc + depends on BOARD_DIGITALLOGIC_ADL855PC + +config MAINBOARD_PART_NUMBER + string + default "ADL855PC" + depends on BOARD_DIGITALLOGIC_ADL855PC + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_DIGITALLOGIC_ADL855PC Added: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,3 @@ +ROMCCFLAGS := -mcpu=p3 -O +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,21 @@ +config BOARD_DIGITALLOGIC_MSM586SEG + bool "MSM586SEG" + select ARCH_X86 + select CPU_AMD_SC520 + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default digitallogic/msm586seg + depends on BOARD_DIGITALLOGIC_MSM586SEG + +config MAINBOARD_PART_NUMBER + string + default "TS5300" + depends on BOARD_DIGITALLOGIC_MSM586SEG + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_DIGITALLOGIC_MSM586SEG + Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,3 @@ +ROMCCFLAGS := -mcpu=i386 -O +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,48 @@ +config BOARD_DIGITALLOGIC_MSM800SEV + bool "MSM800SEV" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default digitallogic/msm800sev + depends on BOARD_DIGITALLOGIC_MSM800SEV + +config MAINBOARD_PART_NUMBER + string + default "MSM800SEV" + depends on BOARD_DIGITALLOGIC_MSM800SEV + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_DIGITALLOGIC_MSM800SEV + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_DIGITALLOGIC_MSM800SEV + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_DIGITALLOGIC_MSM800SEV + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_DIGITALLOGIC_MSM800SEV + +config RAMBASE + hex + default 0x4000 + depends on BOARD_DIGITALLOGIC_MSM800SEV Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,31 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/supermicro/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) +++ trunk/coreboot-v2/src/mainboard/supermicro/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -3,12 +3,13 @@ depends on VENDOR_SUPERMICRO source "src/mainboard/supermicro/h8dme/Kconfig" -#source "src/mainboard/supermicro/h8dmr/Kconfig" -#source "src/mainboard/supermicro/x6dai_g/Kconfig" -#source "src/mainboard/supermicro/x6dhe_g/Kconfig" -#source "src/mainboard/supermicro/x6dhe_g2/Kconfig" -#source "src/mainboard/supermicro/x6dhr_ig/Kconfig" -#source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" +source "src/mainboard/supermicro/h8dmr/Kconfig" +source "src/mainboard/supermicro/h8dmr_fam10/Kconfig" +source "src/mainboard/supermicro/x6dai_g/Kconfig" +source "src/mainboard/supermicro/x6dhe_g/Kconfig" +source "src/mainboard/supermicro/x6dhe_g2/Kconfig" +source "src/mainboard/supermicro/x6dhr_ig/Kconfig" +source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" endchoice Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -60,7 +60,7 @@ config MAINBOARD_PART_NUMBER string - default "ultra40" + default "H8DME" depends on BOARD_SUPERMICRO_H8DME config HW_MEM_HOLE_SIZEK Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,104 @@ +config BOARD_SUPERMICRO_H8DMR + bool "H8DMR" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + +config MAINBOARD_DIR + string + default supermicro/h8dmr + depends on BOARD_SUPERMICRO_H8DMR + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_SUPERMICRO_H8DMR + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_SUPERMICRO_H8DMR + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_SUPERMICRO_H8DMR + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUPERMICRO_H8DMR + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUPERMICRO_H8DMR + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_H8DMR + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_H8DMR + +config MAINBOARD_PART_NUMBER + string + default "H8DMR" + depends on BOARD_SUPERMICRO_H8DMR + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUPERMICRO_H8DMR + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_H8DMR + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DMR + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DMR + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_H8DMR + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_SUPERMICRO_H8DMR Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,78 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,110 @@ +config BOARD_SUPERMICRO_H8DMR_FAM10 + bool "H8DMR_FAM10 (Fam10)" + select ARCH_X86 + select CPU_AMD_FAM10 + select CPU_AMD_SOCKET_F_1207 + select NORTHBRIDGE_AMD_AMDFAM10 + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AMDMCT + +config MAINBOARD_DIR + string + default supermicro/h8dmr_fam10 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config MAINBOARD_PART_NUMBER + string + default "H8DMR_FAM10 FAM10" + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_SUPERMICRO_H8DMR_FAM10 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_0100009f.h" + depends on BOARD_SUPERMICRO_H8DMR_FAM10 Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr_fam10/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,78 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,53 @@ +config BOARD_SUPERMICRO_X6DAI_G + bool "X6DAI-G" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7525 + select SOUTHBRIDGE_INTEL_ESB6300 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x6dai_g + depends on BOARD_SUPERMICRO_X6DAI_G + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_X6DAI_G + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_X6DAI_G + +config MAINBOARD_PART_NUMBER + string + default "X6DAI_G" + depends on BOARD_SUPERMICRO_X6DAI_G + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_X6DAI_G + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x6780 + depends on BOARD_SUPERMICRO_X6DAI_G + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_X6DAI_G + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_X6DAI_G + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_SUPERMICRO_X6DAI_G Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS=-mcpu=p4 -O2 + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,59 @@ +config BOARD_SUPERMICRO_X6DHE_G + bool "X6DHE-G" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7520 + select SOUTHBRIDGE_INTEL_ESB6300 + select SOUTHBRIDGE_INTEL_PXHD + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x6dhe_g + depends on BOARD_SUPERMICRO_X6DHE_G + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_X6DHE_G + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_X6DHE_G + +config MAINBOARD_PART_NUMBER + string + default "X6DHE_G" + depends on BOARD_SUPERMICRO_X6DHE_G + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_X6DHE_G + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x6780 + depends on BOARD_SUPERMICRO_X6DHE_G + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_X6DHE_G + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_X6DHE_G + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_SUPERMICRO_X6DHE_G + +config DRIVERS_GENERIC_DEBUG + bool + default y + depends on BOARD_SUPERMICRO_X6DHE_G Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS=-mcpu=p4 -O2 + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,59 @@ +config BOARD_SUPERMICRO_X6DHE_G2 + bool "X6DAI-G" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7520 + select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_PXHD + select SUPERIO_NSC_PC87427 + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x6dhe_g2 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config MAINBOARD_PART_NUMBER + string + default "X6DHE_G2" + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x6780 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_SUPERMICRO_X6DHE_G2 + +config DRIVERS_GENERIC_DEBUG + bool + default y + depends on BOARD_SUPERMICRO_X6DHE_G2 Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS=-mcpu=p4 -O2 + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,54 @@ +config BOARD_SUPERMICRO_X6DHR_IG + bool "X6DHR-IG" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7520 + select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_PXHD + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x6dhr_ig + depends on BOARD_SUPERMICRO_X6DHR_IG + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_X6DHR_IG + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_X6DHR_IG + +config MAINBOARD_PART_NUMBER + string + default "X6DHR_IG" + depends on BOARD_SUPERMICRO_X6DHR_IG + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_X6DHR_IG + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x6780 + depends on BOARD_SUPERMICRO_X6DHR_IG + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_X6DHR_IG + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_X6DHR_IG + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_SUPERMICRO_X6DHR_IG Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS=-mcpu=p4 -O2 + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Kconfig 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,54 @@ +config BOARD_SUPERMICRO_X6DHR_IG2 + bool "X6DHR-IG" + select ARCH_X86 + select CPU_INTEL_SOCKET_MPGA604 + select NORTHBRIDGE_INTEL_E7520 + select SOUTHBRIDGE_INTEL_I82801ER + select SOUTHBRIDGE_INTEL_PXHD + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x6dhr_ig2 + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config MAINBOARD_PART_NUMBER + string + default "X6DHR_IG2" + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x15d9 + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x6780 + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config MAX_CPUS + int + default 4 + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config USE_INIT + bool + default n + depends on BOARD_SUPERMICRO_X6DHR_IG2 + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_SUPERMICRO_X6DHR_IG2 Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Makefile.inc 2009-10-09 14:10:28 UTC (rev 4751) @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ROMCCFLAGS=-mcpu=p4 -O2 + +include $(src)/mainboard/Makefile.romccboard.inc +

1 0

[PATCH]more kconfig
by Patrick Georgi 09 Oct '09

09 Oct '09

Hi, attached patch enables kconfig based builds for a couple more boards. As usual, this merely passes build and a validity check that all variables are defined that are defined by newconfig (but not necessarily the same value). The larger part of this (which is why I stopped porting more boards and want to get this out first) is that I moved the -O2 flag for romcc invocations into ROMCCFLAGS, as rca/rm4100 wants -O only. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

5 7

Re: [coreboot] [v2] r4743 ..
by Peter Stuge 09 Oct '09

09 Oct '09

svn(a)coreboot.org wrote: > +++ trunk/coreboot-v2/src/cpu/amd/model_lx/Kconfig 2009-10-08 14:31:56 UTC (rev 4743) > @@ -0,0 +1,4 @@ > +config CPU_AMD_LX > + bool > + default n > + It would be nice to have GEODE in this name. Also an extra blank line snuck in. > +++ trunk/coreboot-v2/src/cpu/amd/sc520/Kconfig 2009-10-08 14:31:56 UTC (rev 4743) > @@ -0,0 +1,4 @@ > +config CPU_AMD_SC520 > + bool > + default n > + Maybe ELAN here? > +config BOARD_IEI_PCISA_LX_800_R10 > + bool "PCISA lx-800 r10" These new board names seem to be mostly lowercase, which isn't really right. I'll fix the ones I know about. > +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc 2009-10-08 14:31:56 UTC (rev 4743) > @@ -0,0 +1,31 @@ > +driver-y += mainboard.o > + > +# Needed by irq_tables and mptable and acpi_tables. > +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o > + > +# This is part of the conversion to init-obj and away from included code. > + > +initobj-y += crt0.o > +# FIXME in $(top)/Makefile > +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc > +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc > +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc > +crt0-y += ../../../../src/arch/i386/lib/id.inc > +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc > +crt0-y += auto.inc > + > +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb > +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds > +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds > +ldscript-y += ../../../../src/arch/i386/lib/id.lds > +ldscript-y += ../../../../src/arch/i386/lib/failover.lds > + > +ifdef POST_EVALUATION > + > +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c > + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ > + perl -e 's/\.rodata/.rom.data/g' -pi $@ > + perl -e 's/\.text/.section .rom.text/g' -pi $@ > + > +endif > + This looks similar if not identical among very many boards. Can they be folded together? Sorry if I am nagging about this. //Peter

2 1

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coreboot October 2009