coreboot October 2009

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[v2] r4750 - in trunk/coreboot-v2/src: . cpu/amd cpu/amd/socket_939 cpu/amd/socket_AM2r2 drivers drivers/ati/ragexl mainboard/arima mainboard/arima/hdama mainboard/asus mainboard/asus/a8n_e mainboard/asus/a8v-e_se mainboard/broadcom mainboard/broadcom/blast mainboard/hp mainboard/hp/dl145_g3 mainboard/ibm mainboard/ibm/e325 mainboard/ibm/e326 mainboard/intel/jarrell mainboard/iwill mainboard/iwill/dk8_htx mainboard/iwill/dk8s2 mainboard/iwill/dk8x mainboard/olpc mainboard/olpc/btest mainboard/olp
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: oxygene Date: 2009-10-09 14:32:52 +0200 (Fri, 09 Oct 2009) New Revision: 4750 Added: trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Makefile.inc trunk/coreboot-v2/src/drivers/ati/ragexl/Makefile.inc trunk/coreboot-v2/src/mainboard/arima/hdama/Kconfig trunk/coreboot-v2/src/mainboard/arima/hdama/Makefile.inc trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig trunk/coreboot-v2/src/mainboard/asus/a8n_e/Makefile.inc trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Kconfig trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Makefile.inc trunk/coreboot-v2/src/mainboard/broadcom/blast/Kconfig trunk/coreboot-v2/src/mainboard/broadcom/blast/Makefile.inc trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Kconfig trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Makefile.inc trunk/coreboot-v2/src/mainboard/ibm/e325/Kconfig trunk/coreboot-v2/src/mainboard/ibm/e325/Makefile.inc trunk/coreboot-v2/src/mainboard/ibm/e326/Kconfig trunk/coreboot-v2/src/mainboard/ibm/e326/Makefile.inc trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Kconfig trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Makefile.inc trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Kconfig trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Makefile.inc trunk/coreboot-v2/src/mainboard/iwill/dk8x/Kconfig trunk/coreboot-v2/src/mainboard/iwill/dk8x/Makefile.inc trunk/coreboot-v2/src/mainboard/olpc/btest/Kconfig trunk/coreboot-v2/src/mainboard/olpc/btest/Makefile.inc trunk/coreboot-v2/src/mainboard/olpc/rev_a/Kconfig trunk/coreboot-v2/src/mainboard/olpc/rev_a/Makefile.inc Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/cpu/amd/Kconfig trunk/coreboot-v2/src/cpu/amd/Makefile.inc trunk/coreboot-v2/src/drivers/Makefile.inc trunk/coreboot-v2/src/mainboard/arima/Kconfig trunk/coreboot-v2/src/mainboard/asus/Kconfig trunk/coreboot-v2/src/mainboard/broadcom/Kconfig trunk/coreboot-v2/src/mainboard/hp/Kconfig trunk/coreboot-v2/src/mainboard/ibm/Kconfig trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig trunk/coreboot-v2/src/mainboard/iwill/Kconfig trunk/coreboot-v2/src/mainboard/olpc/Kconfig Log: More Kconfig-supported boards, and also kconfig support for amd/socket_AM2R2, amd/socket_939, drivers/ati/ragexl Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -146,6 +146,10 @@ bool default n +config ATI_RAGE_XL + bool + default n + source src/console/Kconfig config HAVE_ACPI_RESUME Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -3,10 +3,10 @@ default n source src/cpu/amd/socket_754/Kconfig -#source src/cpu/amd/socket_939/Kconfig +source src/cpu/amd/socket_939/Kconfig source src/cpu/amd/socket_940/Kconfig source src/cpu/amd/socket_AM2/Kconfig -#source src/cpu/amd/socket_AM2r2/Kconfig +source src/cpu/amd/socket_AM2r2/Kconfig source src/cpu/amd/socket_F/Kconfig source src/cpu/amd/socket_F_1207/Kconfig source src/cpu/amd/socket_S1G1/Kconfig Modified: trunk/coreboot-v2/src/cpu/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -1,7 +1,9 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F subdirs-$(CONFIG_CPU_AMD_SOCKET_754) += socket_754 +subdirs-$(CONFIG_CPU_AMD_SOCKET_939) += socket_939 subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 +subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_GX1) += model_gx1 subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 subdirs-$(CONFIG_CPU_AMD_LX) += model_lx Added: trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_939/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,9 @@ +config CPU_AMD_SOCKET_939 + bool + default n + select CPU_AMD_MODEL_FXX + +config CPU_SOCKET_TYPE + hex + default 0x0 + depends on CPU_AMD_SOCKET_939 Added: trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,14 @@ +obj-y += socket_939.o +subdirs-y += ../model_fxx +subdirs-y += ../dualcore +subdirs-y += ../mtrr +subdirs-y += ../microcode +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/pae Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,18 @@ +config CPU_AMD_SOCKET_AM2R2 + bool + default n + select CPU_AMD_MODEL_10XXX + select HT3_SUPPORT + select CAR_FAM10 + +config CPU_SOCKET_TYPE + hex + default 0x11 + depends on CPU_AMD_SOCKET_AM2R2 + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + depends on CPU_AMD_SOCKET_AM2R2 + Added: trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2r2/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,14 @@ +obj-y += socket_AM2r2.o +subdirs-y += ../model_10xxx +subdirs-y += ../quadcore +subdirs-y += ../mtrr +subdirs-y += ../microcode +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/sse +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/pae +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/mtrr Modified: trunk/coreboot-v2/src/drivers/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/Makefile.inc 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/drivers/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,2 @@ subdirs-y += pci +subdirs-y += ati/ragexl Added: trunk/coreboot-v2/src/drivers/ati/ragexl/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/drivers/ati/ragexl/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/drivers/ati/ragexl/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1 @@ +driver-$(CONFIG_ATI_RAGE_XL) += xlinit.o Modified: trunk/coreboot-v2/src/mainboard/arima/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/arima/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_ARIMA + +source "src/mainboard/arima/hdama/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/arima/hdama/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,108 @@ +config BOARD_ARIMA_HDAMA + bool "HDAMA" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_NSC_PC87360 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + +config MAINBOARD_DIR + string + default arima/hdama + depends on BOARD_ARIMA_HDAMA + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_ARIMA_HDAMA + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_ARIMA_HDAMA + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_ARIMA_HDAMA + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_ARIMA_HDAMA + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_ARIMA_HDAMA + +config LB_CKS_LOC + int + default 123 + depends on BOARD_ARIMA_HDAMA + +config MAINBOARD_PART_NUMBER + string + default "HDAMA" + depends on BOARD_ARIMA_HDAMA + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_ARIMA_HDAMA + +config MAX_CPUS + int + default 4 + depends on BOARD_ARIMA_HDAMA + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_ARIMA_HDAMA + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_ARIMA_HDAMA + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_ARIMA_HDAMA + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_ARIMA_HDAMA + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_ARIMA_HDAMA + +config USE_INIT + bool + default n + depends on BOARD_ARIMA_HDAMA + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_ARIMA_HDAMA + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_ARIMA_HDAMA Added: trunk/coreboot-v2/src/mainboard/arima/hdama/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable. +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/asus/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -22,6 +22,8 @@ prompt "Mainboard model" depends on VENDOR_ASUS +source "src/mainboard/asus/a8n_e/Kconfig" +source "src/mainboard/asus/a8v-e_se/Kconfig" source "src/mainboard/asus/p2b/Kconfig" source "src/mainboard/asus/p2b-d/Kconfig" source "src/mainboard/asus/p2b-f/Kconfig" Added: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,99 @@ +config BOARD_ASUS_A8N_E + bool "A8N-E" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_939 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_ITE_IT8712F + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + +config MAINBOARD_DIR + string + default asus/a8n_e + depends on BOARD_ASUS_A8N_E + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_ASUS_A8N_E + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on BOARD_ASUS_A8N_E + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_ASUS_A8N_E + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_ASUS_A8N_E + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_ASUS_A8N_E + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_ASUS_A8N_E + +config LB_CKS_LOC + int + default 123 + depends on BOARD_ASUS_A8N_E + +config MAINBOARD_PART_NUMBER + string + default "A8N-E" + depends on BOARD_ASUS_A8N_E + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_ASUS_A8N_E + +config MAX_CPUS + int + default 2 + depends on BOARD_ASUS_A8N_E + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_ASUS_A8N_E + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_ASUS_A8N_E + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_ASUS_A8N_E + +config USE_INIT + bool + default n + depends on BOARD_ASUS_A8N_E + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_ASUS_A8N_E + +config IRQ_SLOT_COUNT + int + default 13 + depends on BOARD_ASUS_A8N_E Added: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,76 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,104 @@ +config BOARD_ASUS_A8V_E_SE + bool "A8V-E SE" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_939 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SUPERIO_WINBOND_W83627EHG + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default asus/a8v-e_se + depends on BOARD_ASUS_A8V_E_SE + +config DCACHE_RAM_BASE + hex + default 0xcc000 + depends on BOARD_ASUS_A8V_E_SE + +config DCACHE_RAM_SIZE + hex + default 0x4000 + depends on BOARD_ASUS_A8V_E_SE + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + depends on BOARD_ASUS_A8V_E_SE + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_ASUS_A8V_E_SE + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_ASUS_A8V_E_SE + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_ASUS_A8V_E_SE + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_ASUS_A8V_E_SE + +config LB_CKS_LOC + int + default 123 + depends on BOARD_ASUS_A8V_E_SE + +config MAINBOARD_PART_NUMBER + string + default "A8V-E SE" + depends on BOARD_ASUS_A8V_E_SE + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_ASUS_A8V_E_SE + +config MAX_CPUS + int + default 2 + depends on BOARD_ASUS_A8V_E_SE + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_ASUS_A8V_E_SE + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_ASUS_A8V_E_SE + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_ASUS_A8V_E_SE + +config USE_INIT + bool + default n + depends on BOARD_ASUS_A8V_E_SE + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_ASUS_A8V_E_SE + +config IRQ_SLOT_COUNT + int + default 13 + depends on BOARD_ASUS_A8V_E_SE Added: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,41 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/broadcom/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/broadcom/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_BROADCOM + +source "src/mainboard/broadcom/blast/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/broadcom/blast/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,105 @@ +config BOARD_BROADCOM_BLAST + bool "Blast" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_BROADCOM_BCM5780 + select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_NSC_PC87417 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + +config MAINBOARD_DIR + string + default broadcom/blast + depends on BOARD_BROADCOM_BLAST + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_BROADCOM_BLAST + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on BOARD_BROADCOM_BLAST + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x0 + depends on BOARD_BROADCOM_BLAST + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_BROADCOM_BLAST + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_BROADCOM_BLAST + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_BROADCOM_BLAST + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_BROADCOM_BLAST + +config LB_CKS_LOC + int + default 123 + depends on BOARD_BROADCOM_BLAST + +config MAINBOARD_PART_NUMBER + string + default "BLAST" + depends on BOARD_BROADCOM_BLAST + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_BROADCOM_BLAST + +config MAX_CPUS + int + default 4 + depends on BOARD_BROADCOM_BLAST + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_BROADCOM_BLAST + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_BROADCOM_BLAST + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_BROADCOM_BLAST + +config USE_INIT + bool + default n + depends on BOARD_BROADCOM_BLAST + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_BROADCOM_BLAST + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_BROADCOM_BLAST Added: trunk/coreboot-v2/src/mainboard/broadcom/blast/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,35 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +driver-y += ../../../drivers/i2c/i2cmux2/i2cmux2.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/hp/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/hp/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_HP + +source "src/mainboard/hp/dl145_g3/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,105 @@ +config BOARD_HP_DL145_G3 + bool "DL145-G3" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_BROADCOM_BCM21000 + select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_NSC_PC87417 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + +config MAINBOARD_DIR + string + default hp/dl145_g3 + depends on BOARD_HP_DL145_G3 + +config DCACHE_RAM_BASE + hex + default 0xcc000 + depends on BOARD_HP_DL145_G3 + +config DCACHE_RAM_SIZE + hex + default 0x04000 + depends on BOARD_HP_DL145_G3 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_HP_DL145_G3 + +config APIC_ID_OFFSET + hex + default 0x10 + depends on BOARD_HP_DL145_G3 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_HP_DL145_G3 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on BOARD_HP_DL145_G3 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_HP_DL145_G3 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_HP_DL145_G3 + +config MAINBOARD_PART_NUMBER + string + default "DL145G3" + depends on BOARD_HP_DL145_G3 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_HP_DL145_G3 + +config MAX_CPUS + int + default 4 + depends on BOARD_HP_DL145_G3 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_HP_DL145_G3 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_HP_DL145_G3 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_HP_DL145_G3 + +config USE_INIT + bool + default n + depends on BOARD_HP_DL145_G3 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_HP_DL145_G3 + +config IRQ_SLOT_COUNT + int + default 15 + depends on BOARD_HP_DL145_G3 Added: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,33 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/ibm/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/ibm/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,9 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_IBM + +source "src/mainboard/ibm/e325/Kconfig" +source "src/mainboard/ibm/e326/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/ibm/e325/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,108 @@ +config BOARD_IBM_E325 + bool "e325" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_NSC_PC87366 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + +config MAINBOARD_DIR + string + default ibm/e325 + depends on BOARD_IBM_E325 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_IBM_E325 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + depends on BOARD_IBM_E325 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x0 + depends on BOARD_IBM_E325 + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_IBM_E325 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_IBM_E325 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_IBM_E325 + +config MAINBOARD_PART_NUMBER + string + default "E325" + depends on BOARD_IBM_E325 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_IBM_E325 + +config MAX_CPUS + int + default 1 + depends on BOARD_IBM_E325 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_IBM_E325 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_IBM_E325 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_IBM_E325 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_IBM_E325 + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_IBM_E325 + +config USE_INIT + bool + default n + depends on BOARD_IBM_E325 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_IBM_E325 + +config IRQ_SLOT_COUNT + int + default 12 + depends on BOARD_IBM_E325 Added: trunk/coreboot-v2/src/mainboard/ibm/e325/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/ibm/e326/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,108 @@ +config BOARD_IBM_E326 + bool "e326" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_NSC_PC87366 + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + +config MAINBOARD_DIR + string + default ibm/e326 + depends on BOARD_IBM_E326 + +config DCACHE_RAM_BASE + hex + default 0xcf000 + depends on BOARD_IBM_E326 + +config DCACHE_RAM_SIZE + hex + default 0x1000 + depends on BOARD_IBM_E326 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x0 + depends on BOARD_IBM_E326 + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_IBM_E326 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_IBM_E326 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_IBM_E326 + +config MAINBOARD_PART_NUMBER + string + default "E326" + depends on BOARD_IBM_E326 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_IBM_E326 + +config MAX_CPUS + int + default 2 + depends on BOARD_IBM_E326 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_IBM_E326 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_IBM_E326 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_IBM_E326 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_IBM_E326 + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_IBM_E326 + +config USE_INIT + bool + default n + depends on BOARD_IBM_E326 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_IBM_E326 + +config IRQ_SLOT_COUNT + int + default 12 + depends on BOARD_IBM_E326 Added: trunk/coreboot-v2/src/mainboard/ibm/e326/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -8,6 +8,7 @@ select SUPERIO_NSC_PC87427 select HAVE_PIRQ_TABLE select UDELAY_TSC + select ATI_RAGE_XL config MAINBOARD_DIR string @@ -38,3 +39,4 @@ int default 9 depends on BOARD_INTEL_JARRELL + Modified: trunk/coreboot-v2/src/mainboard/iwill/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/iwill/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,10 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_IWILL + +source "src/mainboard/iwill/dk8_htx/Kconfig" +source "src/mainboard/iwill/dk8s2/Kconfig" +source "src/mainboard/iwill/dk8x/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,109 @@ +config BOARD_IWILL_DK8_HTX + bool "DK8-HTX" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default iwill/dk8_htx + depends on BOARD_IWILL_DK8_HTX + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_IWILL_DK8_HTX + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_IWILL_DK8_HTX + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_IWILL_DK8_HTX + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_IWILL_DK8_HTX + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_IWILL_DK8_HTX + +config LB_CKS_LOC + int + default 123 + depends on BOARD_IWILL_DK8_HTX + +config MAINBOARD_PART_NUMBER + string + default "DK8-HTX" + depends on BOARD_IWILL_DK8_HTX + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_IWILL_DK8_HTX + +config MAX_CPUS + int + default 4 + depends on BOARD_IWILL_DK8_HTX + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_IWILL_DK8_HTX + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_IWILL_DK8_HTX + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_IWILL_DK8_HTX + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_IWILL_DK8_HTX + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_IWILL_DK8_HTX + +config USE_INIT + bool + default n + depends on BOARD_IWILL_DK8_HTX + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_IWILL_DK8_HTX + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_IWILL_DK8_HTX Added: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,90 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +# ./ssdt.o is in northbridge/amd/amdk8/Config.lb +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt4.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt5.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dx/dsdt_lb.dsl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/ssdt5.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci5.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex + mv pci5.hex ssdt5.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,109 @@ +config BOARD_IWILL_DK8S2 + bool "DK8S2" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + select ATI_RAGE_XL + +config MAINBOARD_DIR + string + default iwill/dk8s2 + depends on BOARD_IWILL_DK8S2 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_IWILL_DK8S2 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_IWILL_DK8S2 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_IWILL_DK8S2 + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_IWILL_DK8S2 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_IWILL_DK8S2 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_IWILL_DK8S2 + +config MAINBOARD_PART_NUMBER + string + default "DK8S2" + depends on BOARD_IWILL_DK8S2 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_IWILL_DK8S2 + +config MAX_CPUS + int + default 4 + depends on BOARD_IWILL_DK8S2 + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_IWILL_DK8S2 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_IWILL_DK8S2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_IWILL_DK8S2 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_IWILL_DK8S2 + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_IWILL_DK8S2 + +config USE_INIT + bool + default n + depends on BOARD_IWILL_DK8S2 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_IWILL_DK8S2 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_IWILL_DK8S2 Added: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,108 @@ +config BOARD_IWILL_DK8X + bool "DK8X" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_940 + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_AMD8111 + select SOUTHBRIDGE_AMD_AMD8131 + select SUPERIO_WINBOND_W83627THF + select HAVE_PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select AP_CODE_IN_CAR + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select WAIT_BEFORE_CPUS_INIT + +config MAINBOARD_DIR + string + default iwill/dk8x + depends on BOARD_IWILL_DK8X + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_IWILL_DK8X + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_IWILL_DK8X + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_IWILL_DK8X + +config APIC_ID_OFFSET + hex + default 0x8 + depends on BOARD_IWILL_DK8X + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_IWILL_DK8X + +config LB_CKS_LOC + int + default 123 + depends on BOARD_IWILL_DK8X + +config MAINBOARD_PART_NUMBER + string + default "DK8X" + depends on BOARD_IWILL_DK8X + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_IWILL_DK8X + +config MAX_CPUS + int + default 4 + depends on BOARD_IWILL_DK8X + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_IWILL_DK8X + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_IWILL_DK8X + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_IWILL_DK8X + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x6 + depends on BOARD_IWILL_DK8X + +config HT_CHAIN_UNITID_BASE + hex + default 0xa + depends on BOARD_IWILL_DK8X + +config USE_INIT + bool + default n + depends on BOARD_IWILL_DK8X + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_IWILL_DK8X + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_IWILL_DK8X Added: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/olpc/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) +++ trunk/coreboot-v2/src/mainboard/olpc/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -1 +1,9 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_OLPC + +source "src/mainboard/olpc/rev_a/Kconfig" +source "src/mainboard/olpc/btest/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/olpc/btest/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,34 @@ +config BOARD_OLPC_BTEST + bool "B-test" + select ARCH_X86 + select CPU_AMD_GX2 + select NORTHBRIDGE_AMD_GX2 + select SOUTHBRIDGE_AMD_CS5536 + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default olpc/btest + depends on BOARD_OLPC_BTEST + +config MAINBOARD_PART_NUMBER + string + default "BTEST" + depends on BOARD_OLPC_BTEST + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_OLPC_BTEST + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_OLPC_BTEST + +config USE_INIT + bool + default n + depends on BOARD_OLPC_BTEST Added: trunk/coreboot-v2/src/mainboard/olpc/btest/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,2 @@ +ROMCCFLAGS=-mcpu=p2 -O +include $(src)/mainboard/Makefile.romccboard.inc Added: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Kconfig 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,34 @@ +config BOARD_OLPC_REV_A + bool "Rev A" + select ARCH_X86 + select CPU_AMD_GX2 + select NORTHBRIDGE_AMD_GX2 + select SOUTHBRIDGE_AMD_CS5536 + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default olpc/rev_a + depends on BOARD_OLPC_REV_A + +config MAINBOARD_PART_NUMBER + string + default "REV A" + depends on BOARD_OLPC_REV_A + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_OLPC_REV_A + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_OLPC_REV_A + +config USE_INIT + bool + default n + depends on BOARD_OLPC_REV_A Added: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Makefile.inc 2009-10-09 12:32:52 UTC (rev 4750) @@ -0,0 +1,2 @@ +ROMCCFLAGS=-mcpu=p2 -O +include $(src)/mainboard/Makefile.romccboard.inc

1 0

[PATCH]another batch of kconfig boards
by Patrick Georgi 09 Oct '09

09 Oct '09

Hi, with this patch, the remaining board count is down to 15. It also implements the remaining AMD sockets and ati/ragexl driver support in kconfig. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

2 1

[PATCH] More kconfig fixes
by Uwe Hermann 09 Oct '09

09 Oct '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[v2] r4749 - in trunk/coreboot-v2/src: . arch/i386 cpu cpu/amd/socket_F_1207 mainboard/asus/m2v-mx_se mainboard/iei/juki-511p mainboard/televideo/tc7020 mainboard/via/epia-m700 southbridge/intel/i82371eb superio/fintek superio/intel superio/ite superio/nsc superio/serverengines superio/smsc superio/via superio/winbond
by svn＠coreboot.org 09 Oct '09

09 Oct '09

Author: uwe Date: 2009-10-09 13:47:21 +0200 (Fri, 09 Oct 2009) New Revision: 4749 Modified: trunk/coreboot-v2/src/Kconfig trunk/coreboot-v2/src/arch/i386/Kconfig trunk/coreboot-v2/src/cpu/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig trunk/coreboot-v2/src/superio/fintek/Kconfig trunk/coreboot-v2/src/superio/intel/Kconfig trunk/coreboot-v2/src/superio/ite/Kconfig trunk/coreboot-v2/src/superio/nsc/Kconfig trunk/coreboot-v2/src/superio/serverengines/Kconfig trunk/coreboot-v2/src/superio/smsc/Kconfig trunk/coreboot-v2/src/superio/via/Kconfig trunk/coreboot-v2/src/superio/winbond/Kconfig Log: More kconfig cleanups: - Use "default n" for all components that shall be "select"ed. - Use "0x0" instead of "0" for hex variables for clarity and to reduce the risk of people passing integer instead of hex values to such variables. - Add TODO comments for boards that have irq_tables.c but don' set CONFIG_HAVE_PIRQ_TABLE = 1. Someone with the hardware should test enabling. - ASUS M2V-MX SE doesn't have irq_tables.c so don't define IRQ_SLOT_COUNT in its Kconfig file. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -56,11 +56,11 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex - default 0 + default 0x0 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0 + default 0x0 config CPU_ADDR_BITS int @@ -68,7 +68,7 @@ config AGP_APERTURE_SIZE hex - default 0 + default 0x0 config XIP_ROM_BASE hex @@ -174,7 +174,7 @@ config HAVE_HARD_RESET bool - default 0 + default n config HAVE_INIT_TIMER bool Modified: trunk/coreboot-v2/src/arch/i386/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/i386/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/arch/i386/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -29,7 +29,7 @@ config PAYLOAD_SIZE hex - default 0 + default 0x0 config ROM_PAYLOAD_START hex Modified: trunk/coreboot-v2/src/cpu/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/cpu/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -19,7 +19,7 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE hex - default 0 + default 0x0 config MAX_PHYSICAL_CPUS int Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -41,5 +41,5 @@ config CDB hex - default 0 + default 0x0 depends on CPU_AMD_SOCKET_F_1207 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -115,8 +115,3 @@ default 0x20 depends on BOARD_ASUS_M2V_MX_SE -# FIXME? -config IRQ_SLOT_COUNT - int - default 11 - depends on BOARD_ASUS_M2V_MX_SE Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-10-09 11:47:21 UTC (rev 4749) @@ -69,10 +69,10 @@ ## ## Build code to export a programmable irq routing table ## +# FIXME: There's an irq_tables.c file, but CONFIG_HAVE_PIRQ_TABLE is 0. default CONFIG_HAVE_PIRQ_TABLE=0 default CONFIG_IRQ_SLOT_COUNT=2 default CONFIG_PIRQ_ROUTE=1 -#object irq_tables.o ## ## Build code to export a CMOS option table Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-10-09 11:47:21 UTC (rev 4749) @@ -70,8 +70,6 @@ default CONFIG_GX1_VIDEOMODE = 0 default CONFIG_SPLASH_GRAPHIC = 1 default CONFIG_VIDEO_MB = 2 -default CONFIG_HAVE_PIRQ_TABLE=0 -default CONFIG_PIRQ_ROUTE=1 default CONFIG_ROM_SIZE = 256 * 1024 default CONFIG_MAINBOARD_VENDOR = "TeleVideo" @@ -82,6 +80,7 @@ default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_PIRQ_ROUTE=1 default CONFIG_IRQ_SLOT_COUNT = 3 # Soldered NIC, internal USB, mini PCI slot default CONFIG_HAVE_OPTION_TABLE = 0 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-10-09 11:47:21 UTC (rev 4749) @@ -116,6 +116,7 @@ default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_HARD_RESET = 0 +# TODO: There is an irq_tables.c file, should it be used? default CONFIG_HAVE_PIRQ_TABLE = 0 default CONFIG_IRQ_SLOT_COUNT = 13 default CONFIG_HAVE_ACPI_TABLES = 1 Modified: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,3 +1,4 @@ config SOUTHBRIDGE_INTEL_I82371EB bool + default n Modified: trunk/coreboot-v2/src/superio/fintek/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/fintek/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/fintek/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,2 +1,3 @@ config SUPERIO_FINTEK_F71805F bool + default n Modified: trunk/coreboot-v2/src/superio/intel/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/intel/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/intel/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,2 +1,3 @@ config SUPERIO_INTEL_I3100 bool + default n Modified: trunk/coreboot-v2/src/superio/ite/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/ite/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/ite/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,14 +1,21 @@ config SUPERIO_ITE_IT8661F bool + default n config SUPERIO_ITE_IT8671F bool + default n config SUPERIO_ITE_IT8673F bool + default n config SUPERIO_ITE_IT8705F bool + default n config SUPERIO_ITE_IT8712F bool + default n config SUPERIO_ITE_IT8716F bool + default n config SUPERIO_ITE_IT8718F bool + default n Modified: trunk/coreboot-v2/src/superio/nsc/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/nsc/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/nsc/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,18 +1,27 @@ config SUPERIO_NSC_PC8374 bool + default n config SUPERIO_NSC_PC87309 bool + default n config SUPERIO_NSC_PC87351 bool + default n config SUPERIO_NSC_PC87360 bool + default n config SUPERIO_NSC_PC87366 bool + default n config SUPERIO_NSC_PC87417 bool + default n config SUPERIO_NSC_PC87427 bool + default n config SUPERIO_NSC_PC97307 bool + default n config SUPERIO_NSC_PC97317 bool + default n Modified: trunk/coreboot-v2/src/superio/serverengines/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/serverengines/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/serverengines/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,2 +1,3 @@ config SUPERIO_SERVERENGINES_PILOT bool + default n Modified: trunk/coreboot-v2/src/superio/smsc/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,12 +1,18 @@ config SUPERIO_SMSC_FDC37M60X bool + default n config SUPERIO_SMSC_LPC47B272 bool + default n config SUPERIO_SMSC_LPC47B397 bool + default n config SUPERIO_SMSC_LPC47M10X bool + default n config SUPERIO_SMSC_LPC47N217 bool + default n config SUPERIO_SMSC_SMSCSUPERIO bool + default n Modified: trunk/coreboot-v2/src/superio/via/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/via/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/via/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,2 +1,3 @@ config SUPERIO_VIA_VT1211 bool + default n Modified: trunk/coreboot-v2/src/superio/winbond/Kconfig =================================================================== --- trunk/coreboot-v2/src/superio/winbond/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) +++ trunk/coreboot-v2/src/superio/winbond/Kconfig 2009-10-09 11:47:21 UTC (rev 4749) @@ -1,18 +1,27 @@ config SUPERIO_WINBOND_W83627DHG bool + default n config SUPERIO_WINBOND_W83627EHG bool + default n config SUPERIO_WINBOND_W83627HF bool + default n config SUPERIO_WINBOND_W83627THF bool + default n config SUPERIO_WINBOND_W83627THG bool + default n config SUPERIO_WINBOND_W83627UHG bool + default n config SUPERIO_WINBOND_W83697HF bool + default n config SUPERIO_WINBOND_W83977F bool + default n config SUPERIO_WINBOND_W83977TF bool + default n

1 0

SerialICE QEMU LUA issues
by Joseph Smith 09 Oct '09

09 Oct '09

Well, It looks like I am having issues running qemu with serialice. It seems I am missing part of the LUA package but I can't figure out which one. I have the lua, lua-devel, and lua-static packages installed but it is still complaining. I am running Fedora Core 11, anyone know what package i need? [root@smitty5m qemu-0.11.0]# i386-softmmu/qemu -M serialice -serialice /dev/ttyS0 -hda /dev/zero -L ./bios SerialICE 1.4 ... ...initializing emulated target hardware... SerialICE: Waiting for handshake with target... target alife! SerialICE: LUA init... SerialICE LUA Failed to run script: serialice.lua:28: module 'bit' not found: no field package.preload['bit'] no file './bit.lua' no file '/usr/share/lua/5.1/bit.lua' no file '/usr/share/lua/5.1/bit/init.lua' no file '/usr/lib/lua/5.1/bit.lua' no file '/usr/lib/lua/5.1/bit/init.lua' no file './bit.so' no file '/usr/lib/lua/5.1/bit.so' no file '/usr/lib/lua/5.1/loadall.so' [root@smitty5m qemu-0.11.0]# Help? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 1

removal of svn:externals in v2's util/
by Patrick Georgi 09 Oct '09

09 Oct '09

Hi, after a quick poll on IRC on what to do with the svn:externals in util/, we pretty much agreed that removing them is the way to go. People who need those tools can still fetch them at the original location in the repository, and already checked out trees will continue to carry those directories. If you have any good reason why this shouldn't happen, or that another course of action (eg. moving the tools into the coreboot v2 repository, so everyone gets them), speak up. Time's up at 20:00 CEST Regards, Patrick

7 14

tyan s2881 with seabios and gpxe
by Hugh Greenberg 09 Oct '09

09 Oct '09

I am trying to put coreboot v2 on a tyan s2881 and I would like to use seabios and gpxe for the payload . I successfully created the coreboot.rom by following the s2881 build tutorial and seabios tutorial. I then tried to add gpxe to the coreboot rom and I received this output from cbfstool: $./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom add ../../../gpxe-0.9.6-tg3-5704.rom pci14e4,1648 99 Could not add the file to CBFS, it's probably too big. $ ./cbfstool ../../targets/tyan/s2881/s2881/coreboot.rom print ../../targets/tyan/s2881/s2881/coreboot.rom: 512 kB, bootblocksize 262144, romsize 524288, offset 0x0 Alignment: 64 bytes Name Offset Type Size normal/payload 0x0 payload 65592 normal/coreboot_ram 0x10080 stage 56173 fallback/payload 0x1dc40 payload 65592 fallback/coreboot_ram 0x2dcc0 stage 55651 0x3b680 null 18744 I taked to Ron about this and he suggested to try the Kconfig build system as that would create a smaller rom. That failed and I received this output: $make GEN build/build.h HOSTCC build_opt_tbl OPTION option_table.h In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:17: /local/coreboot/coreboot-v2/build/option_table.h:45:1: warning: "CMOS_VSTART_reserved_memory" redefined /local/coreboot/coreboot-v2/build/option_table.h:1:1: warning: this is the location of the previous definition /local/coreboot/coreboot-v2/build/option_table.h:46:1: warning: "CMOS_VLEN_reserved_memory" redefined /local/coreboot/coreboot-v2/build/option_table.h:2:1: warning: this is the location of the previous definition In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:19: /local/coreboot/coreboot-v2/src/pc80/serial.c:74: warning: no previous prototype for ‘uart_init’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:21: /local/coreboot/coreboot-v2/src/lib/ramtest.c:137: warning: no previous prototype for ‘ram_check’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:36: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:32:2: error: #error This file needs CONFIG_USE_PRINTK_IN_CAR In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:36: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c: In function ‘print_linkn_in’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:37: warning: implicit declaration of function ‘printk_debug’ /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c: In function ‘ht_read_freq_cap’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:138: warning: implicit declaration of function ‘printk_spew’ /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c: In function ‘ht_setup_chainx’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/incoherent_ht.c:571: warning: unused variable ‘i’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:39: /local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c: At top level: /local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:6: warning: no previous prototype for ‘init_timer’ /local/coreboot/coreboot-v2/src/cpu/amd/model_fxx/apic_timer.c:19: warning: no previous prototype for ‘udelay’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:40: /local/coreboot/coreboot-v2/src/lib/delay.c:2: warning: no previous prototype for ‘mdelay’ /local/coreboot/coreboot-v2/src/lib/delay.c:9: warning: no previous prototype for ‘delay’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:87: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:23: warning: redundant redeclaration of ‘hard_reset’ /local/coreboot/coreboot-v2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c:39: warning: previous definition of ‘hard_reset’ was here In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:87: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:576:2: warning: #warning "FIXME: Implement a better test for Opterons" /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:1083: warning: no previous prototype for ‘memory_end_k’ /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’: /local/coreboot/coreboot-v2/src/northbridge/amd/amdk8/raminit.c:2109: warning: implicit declaration of function ‘printk_err’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:90: /local/coreboot/coreboot-v2/src/lib/generic_sdram.c: At top level: /local/coreboot/coreboot-v2/src/lib/generic_sdram.c:15: warning: no previous prototype for ‘sdram_no_memory’ /local/coreboot/coreboot-v2/src/lib/generic_sdram.c:27: warning: no previous prototype for ‘sdram_initialize’ In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:92: /local/coreboot/coreboot-v2/src/cpu/amd/dualcore/dualcore.c: In function ‘do_k8_init_and_stop_secondaries’: /local/coreboot/coreboot-v2/src/cpu/amd/dualcore/dualcore.c:78: warning: unused variable ‘apicid’ In file included from /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:4, from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97: /local/coreboot/coreboot-v2/src/cpu/amd/car/disable_cache_as_ram.c:19:5: warning: "CONFIG_DCACHE_RAM_SIZE" is not defined In file included from /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:6, from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97: /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c: In function ‘clear_init_ram’: /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14: error: ‘CONFIG_DCACHE_RAM_SIZE’ undeclared (first use in this function) /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14: error: (Each undeclared identifier is reported only once /local/coreboot/coreboot-v2/src/cpu/amd/car/clear_init_ram.c:14: error: for each function it appears in.) In file included from /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:97: /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c: In function ‘post_cache_as_ram’: /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:79: error: ‘CONFIG_DCACHE_RAM_SIZE’ undeclared (first use in this function) /local/coreboot/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c:79: error: ‘CONFIG_DCACHE_RAM_BASE’ undeclared (first use in this function) /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c: At top level: /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:107: warning: no previous prototype for ‘failover_process’ /local/coreboot/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c:155: warning: no previous prototype for ‘cache_as_ram_main’ make: *** [/local/coreboot/coreboot-v2/build/mainboard/tyan/s2881/auto.inc] Error 1 Any ideas? Thanks. -- Hugh Greenberg Email: hng(a)lanl.gov

5 21

[PATCHes] more kconfig boards, amd/cs5535 changes
by Patrick Georgi 08 Oct '09

08 Oct '09

Hi, 20091008-4 is the usual "more kconfig" patch, but 20091008-3 is more complex: It makes southbridge/amd/cs5535 build with the new build system. It only worked in the old one, because chip.h is commented out in the Config.lb file (thanks Uwe for figuring that out). I simply added the normal boiler plate to actually have this stuff do something, even if it's just a printk (as southbridge_enable was already defined) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de>

3 4

[v2] r4748 - in trunk/coreboot-v2/src: mainboard/artecgroup mainboard/artecgroup/dbe61 mainboard/lippert mainboard/lippert/frontrunner mainboard/lippert/roadrunner-lx mainboard/lippert/spacerunner-lx southbridge/amd/cs5535
by svn＠coreboot.org 08 Oct '09

08 Oct '09

Author: oxygene Date: 2009-10-08 22:17:14 +0200 (Thu, 08 Oct 2009) New Revision: 4748 Added: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Kconfig trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Makefile.inc trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Kconfig trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Makefile.inc trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Kconfig trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Makefile.inc trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Kconfig trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig trunk/coreboot-v2/src/mainboard/lippert/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5535/chip.h trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c Log: Fix CS5535 build for kconfig, more kconfig boards (lippert, artec) Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig 2009-10-08 18:50:16 UTC (rev 4747) +++ trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) @@ -1 +1,8 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_ARTEC_GROUP + +source "src/mainboard/artecgroup/dbe61/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,47 @@ +config BOARD_ARTECGROUP_DBE61 + bool "dbe61" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default artecgroup/dbe61 + depends on BOARD_ARTECGROUP_DBE61 + +config MAINBOARD_PART_NUMBER + string + default "DBE61" + depends on BOARD_ARTECGROUP_DBE61 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ARTECGROUP_DBE61 + +config IRQ_SLOT_COUNT + int + default 3 + depends on BOARD_ARTECGROUP_DBE61 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_ARTECGROUP_DBE61 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_ARTECGROUP_DBE61 + +config RAMBASE + hex + default 0x4000 + depends on BOARD_ARTECGROUP_DBE61 Added: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Makefile.inc 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,31 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/mainboard/lippert/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/Kconfig 2009-10-08 18:50:16 UTC (rev 4747) +++ trunk/coreboot-v2/src/mainboard/lippert/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) @@ -1 +1,10 @@ -# +choice + prompt "Mainboard model" + depends on VENDOR_LIPPERT + +source "src/mainboard/lippert/frontrunner/Kconfig" +source "src/mainboard/lippert/roadrunner-lx/Kconfig" +source "src/mainboard/lippert/spacerunner-lx/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,34 @@ +config BOARD_LIPPERT_FRONTRUNNER + bool "Frontrunner" + select ARCH_X86 + select CPU_AMD_GX2 + select NORTHBRIDGE_AMD_GX2 + select SOUTHBRIDGE_AMD_CS5535 + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default lippert/frontrunner + depends on BOARD_LIPPERT_FRONTRUNNER + +config MAINBOARD_PART_NUMBER + string + default "Frontrunner" + depends on BOARD_LIPPERT_FRONTRUNNER + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_LIPPERT_FRONTRUNNER + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_LIPPERT_FRONTRUNNER + +config USE_INIT + bool + default n + depends on BOARD_LIPPERT_FRONTRUNNER Added: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Makefile.inc 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,2 @@ +ROMCCFLAGS=-mcpu=i386 -O +include $(src)/mainboard/Makefile.romccboard.inc Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,48 @@ +config BOARD_LIPPERT_ROADRUNNER_LX + bool "RoadRunner-LX" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_ITE_IT8712F + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default lippert/roadrunner-lx + depends on BOARD_LIPPERT_ROADRUNNER_LX + +config MAINBOARD_PART_NUMBER + string + default "ROADRUNNERLX" + depends on BOARD_LIPPERT_ROADRUNNER_LX + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_LIPPERT_ROADRUNNER_LX + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_LIPPERT_ROADRUNNER_LX + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_LIPPERT_ROADRUNNER_LX + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_LIPPERT_ROADRUNNER_LX + +config RAMBASE + hex + default 0x4000 + depends on BOARD_LIPPERT_ROADRUNNER_LX Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Makefile.inc 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,31 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Added: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Kconfig 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,48 @@ +config BOARD_LIPPERT_SPACERUNNER_LX + bool "SpaceRunner-LX" + select ARCH_X86 + select CPU_AMD_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_ITE_IT8712F + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR + +config MAINBOARD_DIR + string + default lippert/spacerunner-lx + depends on BOARD_LIPPERT_SPACERUNNER_LX + +config MAINBOARD_PART_NUMBER + string + default "SPACERUNNERLX" + depends on BOARD_LIPPERT_SPACERUNNER_LX + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_LIPPERT_SPACERUNNER_LX + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_LIPPERT_SPACERUNNER_LX + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_LIPPERT_SPACERUNNER_LX + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_LIPPERT_SPACERUNNER_LX + +config RAMBASE + hex + default 0x4000 + depends on BOARD_LIPPERT_SPACERUNNER_LX Added: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Makefile.inc 2009-10-08 20:17:14 UTC (rev 4748) @@ -0,0 +1,31 @@ +driver-y += mainboard.o + +# Needed by irq_tables and mptable and acpi_tables. +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +# FIXME in $(top)/Makefile +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/model_lx/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif + Modified: trunk/coreboot-v2/src/southbridge/amd/cs5535/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5535/chip.h 2009-10-08 18:50:16 UTC (rev 4747) +++ trunk/coreboot-v2/src/southbridge/amd/cs5535/chip.h 2009-10-08 20:17:14 UTC (rev 4748) @@ -1,9 +1,9 @@ -#ifndef _SOUTHBRIDGE_AMD_CS5536 -#define _SOUTHBRIDGE_AMD_CS5536 +#ifndef _SOUTHBRIDGE_AMD_CS5535 +#define _SOUTHBRIDGE_AMD_CS5535 -extern struct chip_operations southbridge_amd_cs5536_ops; +extern struct chip_operations southbridge_amd_cs5535_ops; -struct southbridge_amd_cs5536_config { +struct southbridge_amd_cs5535_config { int none; }; Modified: trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c 2009-10-08 18:50:16 UTC (rev 4747) +++ trunk/coreboot-v2/src/southbridge/amd/cs5535/cs5535.c 2009-10-08 20:17:14 UTC (rev 4748) @@ -108,3 +108,11 @@ .vendor = PCI_VENDOR_ID_NS, .device = PCI_DEVICE_ID_NS_CS5535 }; + +struct chip_operations southbridge_amd_cs5535_ops = { + CHIP_NAME("AMD Geode CS5535 Southbridge") + /* This is only called when this device is listed in the + * static device tree. + */ + .enable_dev = southbridge_enable, +};

1 0

[PATCH] Serengeti failover fix
by Myles Watson 08 Oct '09

08 Oct '09

Simplify targets/amd/serengeti_cheetah/Config.lb. There were too many variables being set incorrectly. Boot tested on SimNOW. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> It is also abuild-tested, but abuild doesn't use this Config file. That's why the broken build wasn't caught before this. Thanks, Myles

3 5

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2009

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2005

2004

2003

2002

coreboot October 2009