coreboot October 2009

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[v2] r4771 - in trunk/coreboot-v2/src: mainboard/tyan/s2891 mainboard/tyan/s2892 southbridge/nvidia/ck804
by svn＠coreboot.org 14 Oct '09

14 Oct '09

Author: myles Date: 2009-10-14 04:38:24 +0200 (Wed, 14 Oct 2009) New Revision: 4771 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Log: Use CAR ck804 code with the s2892. Reset the s2891 so the HT speed gets updated. Remove some PANTA comments. Add SATA init from non-CAR version. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-10-13 22:53:24 UTC (rev 4770) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-10-14 02:38:24 UTC (rev 4771) @@ -222,8 +222,8 @@ needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); - // soft_reset(); + printk_info("ht reset -\r\n"); + soft_reset(); } allow_all_aps_stop(bsp_apicid); Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-10-13 22:53:24 UTC (rev 4770) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-10-14 02:38:24 UTC (rev 4771) @@ -75,7 +75,7 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ -#include "southbridge/nvidia/ck804/ck804_early_setup.c" +#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" #include "cpu/amd/car/copy_and_run.c" Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2009-10-13 22:53:24 UTC (rev 4770) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2009-10-14 02:38:24 UTC (rev 4771) @@ -164,6 +164,18 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + /* Activate master port on primary SATA controller. */ + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 7, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, @@ -177,7 +189,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -// PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, @@ -251,8 +263,9 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, +/* This line doesn't exist in the non-CAR version. */ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), @@ -292,10 +305,10 @@ io_base[j] + ANACTRL_IO_BASE + 0xb4, io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); -//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, -// io_base[j] + ANACTRL_IO_BASE + 0xc4, -// io_base[j] + ANACTRL_IO_BASE + 0xc8, -// cpu_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, + io_base[j] + ANACTRL_IO_BASE + 0xc4, + io_base[j] + ANACTRL_IO_BASE + 0xc8, + cpu_ss_tbl, 64); } }

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[v2] r4770 - in trunk/coreboot-v2/src: mainboard/tyan/s2892 mainboard/tyan/s2895 southbridge/nvidia/ck804
by svn＠coreboot.org 14 Oct '09

14 Oct '09

Author: myles Date: 2009-10-14 00:53:24 +0200 (Wed, 14 Oct 2009) New Revision: 4770 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Log: White space change in preparation for a patch to unify handling of ck804. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-10-13 20:20:55 UTC (rev 4769) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-10-13 22:53:24 UTC (rev 4770) @@ -70,10 +70,10 @@ #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ #include "southbridge/nvidia/ck804/ck804_early_setup.c" @@ -154,12 +154,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif + #if CONFIG_USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); + #endif real_main(bist, cpu_init_detectedx); - } void real_main(unsigned long bist, unsigned long cpu_init_detectedx) Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-10-13 20:20:55 UTC (rev 4769) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-10-13 22:53:24 UTC (rev 4770) @@ -95,7 +95,6 @@ #include "cpu/amd/dualcore/dualcore.c" #define CK804_NUM 2 -#define CK804B_BUSN 0x80 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 @@ -279,8 +278,8 @@ needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\r\n"); - // soft_reset(); + printk_info("ht reset -\r\n"); + soft_reset(); } allow_all_aps_stop(bsp_apicid); @@ -290,24 +289,10 @@ fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); -#if 0 - dump_spd_registers(&cpu[0]); -#endif -#if 0 - dump_smbus_registers(); -#endif memreset_setup(); sdram_initialize(nodes, ctrl); -#if 0 - print_pci_devices(); -#endif - -#if 0 - dump_pci_devices(); -#endif - post_cache_as_ram(); } #endif Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2009-10-13 20:20:55 UTC (rev 4769) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2009-10-13 22:53:24 UTC (rev 4770) @@ -103,12 +103,11 @@ static void ck804_early_clear_port(void) { static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, #if CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, #endif - - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, #if CK804_NUM > 1 PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, #endif @@ -120,7 +119,6 @@ static void ck804_early_setup(void) { static const unsigned int ctrl_conf[] = { - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, @@ -328,9 +326,8 @@ static void soft_reset(void) { set_bios_reset(); -#if 1 + /* link reset */ outb(0x02, 0x0cf9); outb(0x06, 0x0cf9); -#endif } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2009-10-13 20:20:55 UTC (rev 4769) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2009-10-13 22:53:24 UTC (rev 4770) @@ -28,7 +28,6 @@ reg = register_values[i]; outl(reg, where); } - val = inl(control); val |= 1; outl(val, control); @@ -52,18 +51,6 @@ #define CK804_PCI_E_X 4 #endif -/* - * We will use the offset in setup_resource_map_x_offset and - * setup_resource_map_offset. - */ -#define CK804B_ANACTRL_IO_BASE 0x3000 -#define CK804B_SYSCTRL_IO_BASE 0x2000 - -#ifdef CK804B_BUSN -#undef CK804B_BUSN -#endif -#define CK804B_BUSN 0x0 - #ifndef CK804B_PCI_E_X #define CK804B_PCI_E_X 4 #endif @@ -94,26 +81,20 @@ unsigned *io_base) { static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, }; - static const unsigned int ctrl_devport_conf_b[] = { - PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - }; - int j; for (j = 0; j < ck804_num; j++) { - if (busn[j] == 0) { //sb chain - setup_resource_map_offset(ctrl_devport_conf, - ARRAY_SIZE(ctrl_devport_conf), - PCI_DEV(busn[j], 0, 0), io_base[j]); - continue; - } - setup_resource_map_offset(ctrl_devport_conf_b, - ARRAY_SIZE(ctrl_devport_conf_b), - PCI_DEV(busn[j], 0, 0), io_base[j]); + u32 dev; + if (busn[j] == 0) //sb chain + dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); + else + dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); + setup_resource_map_offset(ctrl_devport_conf, + ARRAY_SIZE(ctrl_devport_conf), dev, + io_base[j]); } } @@ -121,26 +102,20 @@ unsigned *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, 0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, 0x1, 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, }; - static const unsigned int ctrl_devport_conf_clear_b[] = { - PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, (CK804B_DEVN_BASE + 0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, - }; - int j; for (j = 0; j < ck804_num; j++) { - if (busn[j] == 0) { //sb chain - setup_resource_map_offset(ctrl_devport_conf_clear, - ARRAY_SIZE(ctrl_devport_conf_clear), - PCI_DEV(busn[j], 0, 0), io_base[j]); - continue; - } - setup_resource_map_offset(ctrl_devport_conf_clear_b, - ARRAY_SIZE(ctrl_devport_conf_clear_b), - PCI_DEV(busn[j], 0, 0), io_base[j]); + u32 dev; + if (busn[j] == 0) //sb chain + dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); + else + dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); + setup_resource_map_offset(ctrl_devport_conf_clear, + ARRAY_SIZE(ctrl_devport_conf_clear), dev, + io_base[j]); } } @@ -148,39 +123,33 @@ unsigned *io_base) { static const unsigned int ctrl_conf_master[] = { - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 2, 0xac), 0xffffff00, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xac), 0xffffff00, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, #ifdef CK804_MB_SETUP CK804_MB_SETUP #endif -#if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, -#endif -#if CK804_NUM == 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, -#endif + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, @@ -195,16 +164,16 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), @@ -218,11 +187,11 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif #if CK804_USE_ACI == 1 @@ -236,64 +205,64 @@ }; static const unsigned int ctrl_conf_slave[] = { - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, 1, 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE, 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff << 0) | (0x3ff << 10)), (0x21 << 0) | (0x22 << 10), -//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, +//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE + 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif }; @@ -302,13 +271,13 @@ if (busn[j] == 0) { setup_resource_map_x_offset(ctrl_conf_master, ARRAY_SIZE(ctrl_conf_master), - PCI_DEV(busn[0], 0, 0), io_base[0]); + PCI_DEV(busn[0], CK804_DEVN_BASE, 0), io_base[0]); continue; } setup_resource_map_x_offset(ctrl_conf_slave, ARRAY_SIZE(ctrl_conf_slave), - PCI_DEV(busn[j], 0, 0), io_base[j]); + PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); } for (j = 0; j < ck804_num; j++) {

1 0

[PATCH] fam10 Kconfig
by Myles Watson 14 Oct '09

14 Oct '09

The big_bootblock patch fixes building but breaks booting. It is only for seeing what needs to be fixed with fam10 boards. fam10.diff makes serengeti_cheetah_fam10 build with a broken bootblock, and updates lots of Kconfig variables. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 10

[v2] r4769 - trunk/coreboot-v2/src/mainboard/tyan/s2895
by svn＠coreboot.org 13 Oct '09

13 Oct '09

Author: myles Date: 2009-10-13 22:20:55 +0200 (Tue, 13 Oct 2009) New Revision: 4769 Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c Log: Revert some garbage that snuck into my trivial change, correct a spelling error. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-10-13 20:00:09 UTC (rev 4768) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-10-13 20:20:55 UTC (rev 4769) @@ -102,7 +102,7 @@ pirq_info++; slot_num++; if(sysconf.pci1234[2] & 0xf) { - //second pci beidge + //second pci bridge write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); pirq_info++; slot_num++; } @@ -163,12 +163,6 @@ pirq_info++; slot_num++; #endif - if(sysconf.pci1234[2] & 0xf) { - //second pci beidge - write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); - pirq_info++; slot_num++; - } - pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++)

1 0

[v2] r4768 - in trunk/coreboot-v2/src: devices mainboard/tyan/s2892 mainboard/tyan/s2895
by svn＠coreboot.org 13 Oct '09

13 Oct '09

Author: myles Date: 2009-10-13 22:00:09 +0200 (Tue, 13 Oct 2009) New Revision: 4768 Modified: trunk/coreboot-v2/src/devices/device.c trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c Log: Remove a couple more warnings. Trivial. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/devices/device.c =================================================================== --- trunk/coreboot-v2/src/devices/device.c 2009-10-13 19:21:44 UTC (rev 4767) +++ trunk/coreboot-v2/src/devices/device.c 2009-10-13 20:00:09 UTC (rev 4768) @@ -235,7 +235,7 @@ * the allocator. Also this allows handling of other types of bridges. * */ -void compute_resources(struct bus *bus, struct resource *bridge, +static void compute_resources(struct bus *bus, struct resource *bridge, unsigned long type_mask, unsigned long type) { struct device *dev; @@ -392,7 +392,7 @@ * @param type_mask This value gets anded with the resource type. * @param type This value must match the result of the and. */ -void allocate_resources(struct bus *bus, struct resource *bridge, +static void allocate_resources(struct bus *bus, struct resource *bridge, unsigned long type_mask, unsigned long type) { struct device *dev; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c 2009-10-13 19:21:44 UTC (rev 4767) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/mptable.c 2009-10-13 20:00:09 UTC (rev 4768) @@ -24,7 +24,7 @@ extern void get_bus_conf(void); -void *smp_write_config_table(void *v) +static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "TYAN "; Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-10-13 19:21:44 UTC (rev 4767) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-10-13 20:00:09 UTC (rev 4768) @@ -163,6 +163,12 @@ pirq_info++; slot_num++; #endif + if(sysconf.pci1234[2] & 0xf) { + //second pci beidge + write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); + pirq_info++; slot_num++; + } + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c 2009-10-13 19:21:44 UTC (rev 4767) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/mptable.c 2009-10-13 20:00:09 UTC (rev 4768) @@ -32,7 +32,7 @@ extern void get_bus_conf(void); -void *smp_write_config_table(void *v) +static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "TYAN ";

1 0

[PATCH] Support for MSI MS-6156
by Uwe Hermann 13 Oct '09

13 Oct '09

As everyone is committing new boards today, I don't want to be left behind. So here goes one more board for today (yet-another-440BX). Boot-tested to a Linux prompt successfully. Kconfig only, I didn't bother adding oldconfig files anymore. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 3

[v2] r4767 - in trunk/coreboot-v2: src/mainboard/msi src/mainboard/msi/ms6156 targets/msi targets/msi/ms6156
by svn＠coreboot.org 13 Oct '09

13 Oct '09

Author: uwe Date: 2009-10-13 21:21:44 +0200 (Tue, 13 Oct 2009) New Revision: 4767 Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/ trunk/coreboot-v2/src/mainboard/msi/ms6156/Config.lb trunk/coreboot-v2/src/mainboard/msi/ms6156/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms6156/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms6156/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6156/auto.c trunk/coreboot-v2/src/mainboard/msi/ms6156/chip.h trunk/coreboot-v2/src/mainboard/msi/ms6156/devicetree.cb trunk/coreboot-v2/src/mainboard/msi/ms6156/irq_tables.c trunk/coreboot-v2/src/mainboard/msi/ms6156/mainboard.c trunk/coreboot-v2/targets/msi/ms6156/ trunk/coreboot-v2/targets/msi/ms6156/Config.lb Modified: trunk/coreboot-v2/src/mainboard/msi/Kconfig Log: Add support for the MSI MS-6156 board. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/msi/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-10-13 17:56:11 UTC (rev 4766) +++ trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-10-13 19:21:44 UTC (rev 4767) @@ -24,6 +24,7 @@ source "src/mainboard/msi/ms6119/Kconfig" source "src/mainboard/msi/ms6147/Kconfig" +source "src/mainboard/msi/ms6156/Kconfig" source "src/mainboard/msi/ms6178/Kconfig" source "src/mainboard/msi/ms7135/Kconfig" source "src/mainboard/msi/ms7260/Kconfig" Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/Config.lb 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 128 * 1024 +include /config/nofailovercalculation.lb +default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 + +arch i386 end +driver mainboard.o +if CONFIG_HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" + action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if CONFIG_USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 off # GPIO 1 + end + device pnp 3f0.8 off # GPIO 2 + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a off # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + device pci 14.0 on end # Onboard audio (Ensoniq ES1371) + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/Kconfig 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,51 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_MSI_MS_6156 + bool "MS-6156" + select ARCH_X86 + select CPU_INTEL_SLOT_2 + select NORTHBRIDGE_INTEL_I440BX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_WINBOND_W83977TF + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + +config MAINBOARD_DIR + string + default msi/ms6156 + depends on BOARD_MSI_MS_6156 + +config MAINBOARD_PART_NUMBER + string + default "MS-6156" + depends on BOARD_MSI_MS_6156 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_MSI_MS_6156 + +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_MSI_MS_6156 + Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/Makefile.inc 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/Options.lb 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,97 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses COREBOOT_EXTRA_VERSION +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_CROSS_COMPILE +uses CC +uses HOSTCC +uses CONFIG_OBJCOPY +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_HAVE_FALLBACK_BOOT = 1 +default CONFIG_HAVE_MP_TABLE = 0 +default CONFIG_HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default CONFIG_HAVE_PIRQ_TABLE = 1 +default CONFIG_IRQ_SLOT_COUNT = 7 +default CONFIG_MAINBOARD_VENDOR = "MSI" +default CONFIG_MAINBOARD_PART_NUMBER = "MS-6156" +default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_STACK_SIZE = 8 * 1024 +default CONFIG_HEAP_SIZE = 16 * 1024 +default CONFIG_HAVE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 +default CONFIG_RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CONFIG_CROSS_COMPILE = "" +default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_TTYS0_BAUD = 115200 +default CONFIG_TTYS0_BASE = 0x3f8 +default CONFIG_TTYS0_LCS = 0x3 # 8n1 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/auto.c 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ + + enable_smbus(); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/chip.h 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/devicetree.cb (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/devicetree.cb 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,81 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 off # GPIO 1 + end + device pnp 3f0.8 off # GPIO 2 + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a off # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + device pci 14.0 on end # Onboard audio (Ensoniq ES1371) + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "1" + register "ide0_drive1_udma33_enable" = "1" + register "ide1_drive0_udma33_enable" = "1" + register "ide1_drive1_udma33_enable" = "1" + end + end +end Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/irq_tables.c 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router dev */ + 0x800, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb3, /* Checksum */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x0e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, + {0x00, (0x12 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0x0}, + {0x00, (0x00 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x07 << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/coreboot-v2/src/mainboard/msi/ms6156/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6156/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6156/mainboard.c 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("MSI MS-6156 Mainboard") +}; Added: trunk/coreboot-v2/targets/msi/ms6156/Config.lb =================================================================== --- trunk/coreboot-v2/targets/msi/ms6156/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/msi/ms6156/Config.lb 2009-10-13 19:21:44 UTC (rev 4767) @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target ms6156 +mainboard msi/ms6156 + +option CONFIG_ROM_SIZE = 256 * 1024 + +option CONFIG_MAINBOARD_VENDOR = "MSI" +option CONFIG_MAINBOARD_PART_NUMBER = "MS-6156" + +option CONFIG_IRQ_SLOT_COUNT = 7 + +option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option CONFIG_USE_FALLBACK_IMAGE = 0 + option COREBOOT_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option CONFIG_USE_FALLBACK_IMAGE = 1 + option COREBOOT_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"

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build service results for r4766
by coreboot information 13 Oct '09

13 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4766 to the coreboot repository. This caused the following changes: Change Log: Fix kontron/kt690 build. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Configuration of kontron:kt690 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4766 - in trunk/coreboot-v2: src/mainboard/kontron/kt690 targets/kontron/kt690
by svn＠coreboot.org 13 Oct '09

13 Oct '09

Author: myles Date: 2009-10-13 19:56:11 +0200 (Tue, 13 Oct 2009) New Revision: 4766 Modified: trunk/coreboot-v2/src/mainboard/kontron/kt690/Options.lb trunk/coreboot-v2/src/mainboard/kontron/kt690/acpi_tables.c trunk/coreboot-v2/targets/kontron/kt690/Config-abuild.lb Log: Fix kontron/kt690 build. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/kontron/kt690/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/kt690/Options.lb 2009-10-13 16:56:58 UTC (rev 4765) +++ trunk/coreboot-v2/src/mainboard/kontron/kt690/Options.lb 2009-10-13 17:56:11 UTC (rev 4766) @@ -21,7 +21,6 @@ ## uses CONFIG_HAVE_MP_TABLE -uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME @@ -42,9 +41,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE @@ -301,10 +298,4 @@ default CONFIG_GFXUMA=1 default CONFIG_HAVE_MAINBOARD_RESOURCES=1 -### End Options.lb -# -# CBFS -# -# -default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/src/mainboard/kontron/kt690/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/kt690/acpi_tables.c 2009-10-13 16:56:58 UTC (rev 4765) +++ trunk/coreboot-v2/src/mainboard/kontron/kt690/acpi_tables.c 2009-10-13 17:56:11 UTC (rev 4766) @@ -123,7 +123,7 @@ } -unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) { +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); return (unsigned long) (acpigen_get_current()); Modified: trunk/coreboot-v2/targets/kontron/kt690/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/kt690/Config-abuild.lb 2009-10-13 16:56:58 UTC (rev 4765) +++ trunk/coreboot-v2/targets/kontron/kt690/Config-abuild.lb 2009-10-13 17:56:11 UTC (rev 4766) @@ -28,4 +28,4 @@ end buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" -pci_rom ../../../misc/KT690/pci1002,791f.rom vendor_id=0x1002 device_id=0x791f +#pci_rom ../../../misc/KT690/pci1002,791f.rom vendor_id=0x1002 device_id=0x791f

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build service results for r4764
by coreboot information 13 Oct '09

13 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4764 to the coreboot repository. This caused the following changes: Change Log: This patch adds (initial) support for the Kontron KT690 mainboard. It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU. Issues with this port: - hangs early during "Starting Windows" with Windows 7, after loading all the drivers - sound is untested and probably not working - powernow seems to be not working Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Configuration of kontron:kt690 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4764&device=kt690&vendor=k… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot October 2009