coreboot October 2009

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[PATCH] Fix VIA C3 and C7 CPUs in kconfig
by Uwe Hermann 16 Oct '09

16 Oct '09

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4785 - in trunk/coreboot-v2/src/cpu/via: model_c3 model_c7
by svn＠coreboot.org 16 Oct '09

16 Oct '09

Author: uwe Date: 2009-10-16 12:06:18 +0200 (Fri, 16 Oct 2009) New Revision: 4785 Modified: trunk/coreboot-v2/src/cpu/via/model_c3/Makefile.inc trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc Log: Similar to r4626, change obj-y to driver-y for VIA C3 and C7. Otherwise the following happens at runtime (tested on VIA pc2500e, C7): Initializing CPU #0 CPU: vendor Centaur device 6a9 CPU: family 06, model 0a, stepping 09 Unknown cpu We also change C3 as it is pretty clear that the same problem occurs there. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/cpu/via/model_c3/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c3/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) +++ trunk/coreboot-v2/src/cpu/via/model_c3/Makefile.inc 2009-10-16 10:06:18 UTC (rev 4785) @@ -8,4 +8,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../../intel/microcode -obj-y += model_c3_init.o +driver-y += model_c3_init.o Modified: trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) +++ trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc 2009-10-16 10:06:18 UTC (rev 4785) @@ -8,4 +8,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../../intel/microcode -obj-y += model_c7_init.o +driver-y += model_c7_init.o

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[v2] r4784 - in trunk/coreboot-v2/src/cpu/amd: socket_754 socket_939 socket_940 socket_AM2 socket_F socket_F_1207
by svn＠coreboot.org 16 Oct '09

16 Oct '09

Author: uwe Date: 2009-10-16 12:03:50 +0200 (Fri, 16 Oct 2009) New Revision: 4784 Modified: trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Makefile.inc Log: Drop duplicate CPU subdirs-y entries for "../../x86/mtrr". Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc 2009-10-16 07:44:04 UTC (rev 4783) +++ trunk/coreboot-v2/src/cpu/amd/socket_754/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) @@ -4,7 +4,6 @@ subdirs-y += ../mtrr subdirs-y += ../microcode subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/fpu subdirs-y += ../../x86/mmx subdirs-y += ../../x86/sse Modified: trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc 2009-10-16 07:44:04 UTC (rev 4783) +++ trunk/coreboot-v2/src/cpu/amd/socket_939/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) @@ -4,7 +4,6 @@ subdirs-y += ../mtrr subdirs-y += ../microcode subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/fpu subdirs-y += ../../x86/mmx subdirs-y += ../../x86/sse Modified: trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc 2009-10-16 07:44:04 UTC (rev 4783) +++ trunk/coreboot-v2/src/cpu/amd/socket_940/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) @@ -4,7 +4,6 @@ subdirs-y += ../mtrr subdirs-y += ../microcode subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/fpu subdirs-y += ../../x86/mmx subdirs-y += ../../x86/sse Modified: trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc 2009-10-16 07:44:04 UTC (rev 4783) +++ trunk/coreboot-v2/src/cpu/amd/socket_AM2/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) @@ -4,7 +4,6 @@ subdirs-y += ../mtrr subdirs-y += ../microcode subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/fpu subdirs-y += ../../x86/mmx subdirs-y += ../../x86/sse Modified: trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc 2009-10-16 07:44:04 UTC (rev 4783) +++ trunk/coreboot-v2/src/cpu/amd/socket_F/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) @@ -4,7 +4,6 @@ subdirs-y += ../mtrr subdirs-y += ../microcode subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/fpu subdirs-y += ../../x86/mmx subdirs-y += ../../x86/sse Modified: trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Makefile.inc 2009-10-16 07:44:04 UTC (rev 4783) +++ trunk/coreboot-v2/src/cpu/amd/socket_F_1207/Makefile.inc 2009-10-16 10:03:50 UTC (rev 4784) @@ -4,7 +4,6 @@ subdirs-y += ../mtrr subdirs-y += ../microcode subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/fpu subdirs-y += ../../x86/mmx subdirs-y += ../../x86/sse

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[PATCH]: vga bios was added into image by cbfstool, not by "cat" any more.
by Bao, Zheng 16 Oct '09

16 Oct '09

Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise the VGA ROM can not run. After make, run > ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom to make the final image with vga bios. The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I can not make test on. ## Index: src/southbridge/amd/rs690/chip.h ## =================================================================== ## --- src/southbridge/amd/rs690/chip.h (revision 4782) ## +++ src/southbridge/amd/rs690/chip.h (working copy) ## @@ -23,7 +23,6 @@ ## /* Member variables are defined in Config.lb. */ ## struct southbridge_amd_rs690_config ## { ## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */ ## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ ## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ ## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ ## Don't apply the above patch about rs690/chip.h before every board has fixed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/southbridge/amd/rs690/rs690_gfx.c =================================================================== --- src/southbridge/amd/rs690/rs690_gfx.c (revision 4782) +++ src/southbridge/amd/rs690/rs690_gfx.c (working copy) @@ -77,13 +77,9 @@ (struct southbridge_amd_rs690_config *)dev->chip_info; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n", - deviceid, vendorid, cfg->vga_rom_address); + printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + deviceid, vendorid); -#if 0 /* I think these should be done in Config.lb. Please check it. */ - dev->on_mainboard = 1; - dev->rom_address = cfg->vga_rom_address; /* 0xfff00000; */ -#endif pci_dev_init(dev); /* clk ind */ Index: src/mainboard/amd/dbm690t/Options.lb =================================================================== --- src/mainboard/amd/dbm690t/Options.lb (revision 4782) +++ src/mainboard/amd/dbm690t/Options.lb (working copy) @@ -73,6 +73,7 @@ uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses CONFIG_VGA_ROM_RUN uses CONFIG_HW_MEM_HOLE_SIZEK uses CONFIG_HT_CHAIN_UNITID_BASE uses CONFIG_HT_CHAIN_END_UNITID_BASE @@ -103,8 +104,6 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#256K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## @@ -160,6 +159,7 @@ #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset Index: src/mainboard/amd/dbm690t/Config.lb =================================================================== --- src/mainboard/amd/dbm690t/Config.lb (revision 4782) +++ src/mainboard/amd/dbm690t/Config.lb (working copy) @@ -136,7 +136,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -170,7 +169,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Index: src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- src/mainboard/amd/dbm690t/devicetree.cb (revision 4782) +++ src/mainboard/amd/dbm690t/devicetree.cb (working copy) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -33,7 +32,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Index: src/mainboard/amd/pistachio/Options.lb =================================================================== --- src/mainboard/amd/pistachio/Options.lb (revision 4782) +++ src/mainboard/amd/pistachio/Options.lb (working copy) @@ -73,6 +73,7 @@ uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses CONFIG_VGA_ROM_RUN uses CONFIG_HW_MEM_HOLE_SIZEK uses CONFIG_HT_CHAIN_UNITID_BASE uses CONFIG_HT_CHAIN_END_UNITID_BASE @@ -158,6 +159,7 @@ #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset Index: src/mainboard/amd/pistachio/Config.lb =================================================================== --- src/mainboard/amd/pistachio/Config.lb (revision 4782) +++ src/mainboard/amd/pistachio/Config.lb (working copy) @@ -136,7 +136,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -171,7 +170,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Index: src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- src/mainboard/amd/pistachio/devicetree.cb (revision 4782) +++ src/mainboard/amd/pistachio/devicetree.cb (working copy) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -34,7 +33,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Index: targets/amd/dbm690t/Config.lb =================================================================== --- targets/amd/dbm690t/Config.lb (revision 4782) +++ targets/amd/dbm690t/Config.lb (working copy) @@ -4,7 +4,7 @@ mainboard amd/dbm690t romimage "normal" - option CONFIG_ROM_SIZE = 1024*1024 - 55808 + option CONFIG_ROM_SIZE = 1024*1024 option CONFIG_USE_FALLBACK_IMAGE=0 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 Index: targets/amd/pistachio/Config.lb =================================================================== --- targets/amd/pistachio/Config.lb (revision 4782) +++ targets/amd/pistachio/Config.lb (working copy) @@ -4,14 +4,14 @@ mainboard amd/pistachio romimage "normal" - option CONFIG_ROM_SIZE = 1024*1024 - 55808 + option CONFIG_ROM_SIZE = 1024*1024 option CONFIG_USE_FALLBACK_IMAGE=0 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end -romimage "fallback" +romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000

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[v2] r4783 - in trunk/coreboot-v2: src/mainboard/amd/dbm690t src/mainboard/amd/pistachio src/southbridge/amd/rs690 targets/amd/dbm690t targets/amd/pistachio
by svn＠coreboot.org 16 Oct '09

16 Oct '09

Author: zbao Date: 2009-10-16 09:44:04 +0200 (Fri, 16 Oct 2009) New Revision: 4783 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c trunk/coreboot-v2/targets/amd/dbm690t/Config.lb trunk/coreboot-v2/targets/amd/pistachio/Config.lb Log: Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise the VGA ROM can not run. After make, run > ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom to make the final image with vga bios. The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I cant make test on. ## Index: src/southbridge/amd/rs690/chip.h ## =================================================================== ## --- src/southbridge/amd/rs690/chip.h (revision 4782) ## +++ src/southbridge/amd/rs690/chip.h (working copy) ## @@ -23,7 +23,6 @@ ## /* Member variables are defined in Config.lb. */ ## struct southbridge_amd_rs690_config ## { ## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */ ## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ ## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ ## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ ## Don't apply above patch about rs690/chip.h before every board has been fixed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-10-16 07:44:04 UTC (rev 4783) @@ -136,7 +136,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -170,7 +169,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-10-16 07:44:04 UTC (rev 4783) @@ -73,6 +73,7 @@ uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses CONFIG_VGA_ROM_RUN uses CONFIG_HW_MEM_HOLE_SIZEK uses CONFIG_HT_CHAIN_UNITID_BASE uses CONFIG_HT_CHAIN_END_UNITID_BASE @@ -103,8 +104,6 @@ ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#256K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## @@ -160,6 +159,7 @@ #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb 2009-10-16 07:44:04 UTC (rev 4783) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -33,7 +32,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-10-16 07:44:04 UTC (rev 4783) @@ -136,7 +136,6 @@ #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -171,7 +170,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-10-16 07:44:04 UTC (rev 4783) @@ -73,6 +73,7 @@ uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses CONFIG_VGA_ROM_RUN uses CONFIG_HW_MEM_HOLE_SIZEK uses CONFIG_HT_CHAIN_UNITID_BASE uses CONFIG_HT_CHAIN_END_UNITID_BASE @@ -158,6 +159,7 @@ #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 +default CONFIG_VGA_ROM_RUN=1 # BTDC: Only one HT device on Herring. #HT Unit ID offset Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb 2009-10-16 07:44:04 UTC (rev 4783) @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -34,7 +33,6 @@ device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_gfx.c 2009-10-16 07:44:04 UTC (rev 4783) @@ -77,13 +77,9 @@ (struct southbridge_amd_rs690_config *)dev->chip_info; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n", - deviceid, vendorid, cfg->vga_rom_address); + printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + deviceid, vendorid); -#if 0 /* I think these should be done in Config.lb. Please check it. */ - dev->on_mainboard = 1; - dev->rom_address = cfg->vga_rom_address; /* 0xfff00000; */ -#endif pci_dev_init(dev); /* clk ind */ Modified: trunk/coreboot-v2/targets/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/dbm690t/Config.lb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/targets/amd/dbm690t/Config.lb 2009-10-16 07:44:04 UTC (rev 4783) @@ -4,14 +4,14 @@ mainboard amd/dbm690t romimage "normal" - option CONFIG_ROM_SIZE = 1024*1024 - 55808 + option CONFIG_ROM_SIZE = 1024*1024 option CONFIG_USE_FALLBACK_IMAGE=0 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end -romimage "fallback" +romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 Modified: trunk/coreboot-v2/targets/amd/pistachio/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/pistachio/Config.lb 2009-10-16 01:08:07 UTC (rev 4782) +++ trunk/coreboot-v2/targets/amd/pistachio/Config.lb 2009-10-16 07:44:04 UTC (rev 4783) @@ -4,14 +4,14 @@ mainboard amd/pistachio romimage "normal" - option CONFIG_ROM_SIZE = 1024*1024 - 55808 + option CONFIG_ROM_SIZE = 1024*1024 option CONFIG_USE_FALLBACK_IMAGE=0 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000 payload ../payload.elf end -romimage "fallback" +romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 option CONFIG_ROM_IMAGE_SIZE=0x20000 option CONFIG_XIP_ROM_SIZE=0x20000

1 0

[v2] r4782 - in trunk/coreboot-v2/util/vgabios: . x86emu/include x86emu/include/x86emu x86emu/src/x86emu x86emu/src/x86emu/x86emu
by svn＠coreboot.org 16 Oct '09

16 Oct '09

Author: stepan Date: 2009-10-16 03:08:07 +0200 (Fri, 16 Oct 2009) New Revision: 4782 Modified: trunk/coreboot-v2/util/vgabios/helper_mem.c trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu.h trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/fpu_regs.h trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/regs.h trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/debug.c trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/decode.c trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/fpu.c trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/makefile trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/ops.c trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/x86emu/debug.h Log: this is probably in vain because this tool should use the same x86emu as coreboot in order to produce comparable results. But, this patch drops the CONFIG_ from CONFIG_DEBUG because that was added by accident when we automatically renamed coreboot variables to be consistent. "vgabios" is an independent userspace utility, and it does not use newconfig nor Kconfig, so it should not be converted. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/util/vgabios/helper_mem.c =================================================================== --- trunk/coreboot-v2/util/vgabios/helper_mem.c 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/helper_mem.c 2009-10-16 01:08:07 UTC (rev 4782) @@ -24,7 +24,7 @@ }; #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG void dprint(unsigned long start, unsigned long size) { int i, j; @@ -44,7 +44,7 @@ } printf("\n"); } -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ #if 0 #ifndef _PC Modified: trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/fpu_regs.h =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/fpu_regs.h 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/fpu_regs.h 2009-10-16 01:08:07 UTC (rev 4782) @@ -102,7 +102,7 @@ #endif /* X86_FPU_SUPPORT */ -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define DECODE_PRINTINSTR32(t,mod,rh,rl) \ DECODE_PRINTF(t[(mod<<3)+(rh)]); # define DECODE_PRINTINSTR256(t,mod,rh,rl) \ Modified: trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/regs.h =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/regs.h 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu/regs.h 2009-10-16 01:08:07 UTC (rev 4782) @@ -275,7 +275,7 @@ u32 mode; volatile int intr; /* mask of pending interrupts */ int debug; -#ifdef CONFIG_DEBUG +#ifdef DEBUG int check; u16 saved_ip; u16 saved_cs; Modified: trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu.h =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu.h 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/include/x86emu.h 2009-10-16 01:08:07 UTC (rev 4782) @@ -155,7 +155,7 @@ void X86EMU_exec(void); void X86EMU_halt_sys(void); -#ifdef CONFIG_DEBUG +#ifdef DEBUG #define HALT_SYS() \ printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ X86EMU_halt_sys() Modified: trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/debug.c =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/debug.c 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/debug.c 2009-10-16 01:08:07 UTC (rev 4782) @@ -42,7 +42,7 @@ /*----------------------------- Implementation ----------------------------*/ -#ifdef CONFIG_DEBUG +#ifdef DEBUG static void print_encoded_bytes (u16 s, u16 o); static void print_decoded_instruction (void); @@ -90,7 +90,7 @@ * flag associated with the "execution", and we are using a copy * of the register struct. All the major opcodes, once fully * decoded, have the following two steps: TRACE_REGS(r,m); - * SINGLE_STEP(r,m); which disappear if CONFIG_DEBUG is not defined to + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to * the preprocessor. The TRACE_REGS macro expands to: * * if (debug&DEBUG_DISASSEMBLE) @@ -354,7 +354,7 @@ } } -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ void x86emu_dump_regs (void) { Modified: trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/decode.c =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/decode.c 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/decode.c 2009-10-16 01:08:07 UTC (rev 4782) @@ -283,7 +283,7 @@ case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: return M.x86.R_SS; default: -#ifdef CONFIG_DEBUG +#ifdef DEBUG printk("error: should not happen: multiple overrides.\n"); #endif HALT_SYS(); @@ -303,7 +303,7 @@ u8 fetch_data_byte( uint offset) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -322,7 +322,7 @@ u16 fetch_data_word( uint offset) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -341,7 +341,7 @@ u32 fetch_data_long( uint offset) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -362,7 +362,7 @@ uint segment, uint offset) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -383,7 +383,7 @@ uint segment, uint offset) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -404,7 +404,7 @@ uint segment, uint offset) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -426,7 +426,7 @@ uint offset, u8 val) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -448,7 +448,7 @@ uint offset, u16 val) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -470,7 +470,7 @@ uint offset, u32 val) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access((u16)get_data_segment(), offset); #endif @@ -493,7 +493,7 @@ uint offset, u8 val) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -516,7 +516,7 @@ uint offset, u16 val) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif @@ -539,7 +539,7 @@ uint offset, u32 val) { -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (CHECK_DATA_ACCESS()) x86emu_check_data_access(segment, offset); #endif Modified: trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/fpu.c =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/fpu.c 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/fpu.c 2009-10-16 01:08:07 UTC (rev 4782) @@ -50,7 +50,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG static char *x86emu_fpu_op_d9_tab[] = { "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", @@ -89,7 +89,7 @@ "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xd9 */ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) @@ -100,7 +100,7 @@ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); } else { @@ -294,7 +294,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG char *x86emu_fpu_op_da_tab[] = { "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", @@ -316,7 +316,7 @@ "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xda */ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) @@ -384,7 +384,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG char *x86emu_fpu_op_db_tab[] = { "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", @@ -397,7 +397,7 @@ "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xdb */ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) @@ -407,7 +407,7 @@ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (mod != 3) { DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); } else if (rh == 4) { /* === 11 10 0 nnn */ @@ -428,7 +428,7 @@ } else { DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); } -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ switch (mod) { case 0: destoffset = decode_rm00_address(rl); @@ -504,7 +504,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG char *x86emu_fpu_op_dc_tab[] = { "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", "FCOMP\tQWORD PTR ", @@ -524,7 +524,7 @@ "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xdc */ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) @@ -618,7 +618,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG static char *x86emu_fpu_op_dd_tab[] = { "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", @@ -634,7 +634,7 @@ "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xdd */ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) @@ -718,7 +718,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG static char *x86emu_fpu_op_de_tab[] = { @@ -741,7 +741,7 @@ "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xde */ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) @@ -837,7 +837,7 @@ END_OF_INSTR_NO_TRACE(); } -#ifdef CONFIG_DEBUG +#ifdef DEBUG static char *x86emu_fpu_op_df_tab[] = { /* mod == 00 */ @@ -860,7 +860,7 @@ "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," }; -#endif /* CONFIG_DEBUG */ +#endif /* DEBUG */ /* opcode=0xdf */ void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) Modified: trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/makefile =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/makefile 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/makefile 2009-10-16 01:08:07 UTC (rev 4782) @@ -32,7 +32,7 @@ # ############################################################################# -.IMPORT .IGNORE: CONFIG_DEBUG +.IMPORT .IGNORE: DEBUG #---------------------------------------------------------------------------- # Define the lists of object files @@ -40,7 +40,7 @@ OBJECTS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O CFLAGS += -DSCITECH -.IF $(CONFIG_DEBUG) +.IF $(DEBUG) CFLAGS += -DDEBUG .ENDIF LIBCLEAN = *.dll *.lib *.a Modified: trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/ops.c =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/ops.c 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/ops.c 2009-10-16 01:08:07 UTC (rev 4782) @@ -76,7 +76,7 @@ /* constant arrays to do several instructions in just one function */ -#ifdef CONFIG_DEBUG +#ifdef DEBUG static char *x86emu_GenOpName[8] = { "ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"}; #endif @@ -157,7 +157,7 @@ sar_long, }; -#ifdef CONFIG_DEBUG +#ifdef DEBUG static char *opF6_names[8] = { "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" }; @@ -1278,7 +1278,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1356,7 +1356,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1472,7 +1472,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -1548,7 +1548,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3080,7 +3080,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3155,7 +3155,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3632,7 +3632,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3703,7 +3703,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3805,7 +3805,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -3878,7 +3878,7 @@ */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4863,7 +4863,7 @@ /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings @@ -4927,7 +4927,7 @@ /* Yet another special case instruction. */ START_OF_INSTR(); FETCH_DECODE_MODRM(mod, rh, rl); -#ifdef CONFIG_DEBUG +#ifdef DEBUG if (DEBUG_DECODE()) { /* XXX DECODE_PRINTF may be changed to something more general, so that it is important to leave the strings Modified: trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/x86emu/debug.h =================================================================== --- trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/x86emu/debug.h 2009-10-15 22:40:41 UTC (rev 4781) +++ trunk/coreboot-v2/util/vgabios/x86emu/src/x86emu/x86emu/debug.h 2009-10-16 01:08:07 UTC (rev 4782) @@ -48,7 +48,7 @@ #define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ #define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) @@ -60,7 +60,7 @@ # define CHECK_DATA_ACCESS() #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) @@ -99,7 +99,7 @@ # define DEBUG_DECODE_NOPRINT() 0 #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ x86emu_decode_printf(x) @@ -129,7 +129,7 @@ # define SAVE_IP_CS(x,y) #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG #define TRACE_REGS() \ if (DEBUG_DISASSEMBLE()) { \ x86emu_just_disassemble(); \ @@ -140,7 +140,7 @@ # define TRACE_REGS() #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() @@ -150,7 +150,7 @@ TRACE_REGS(); \ SINGLE_STEP() -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define START_OF_INSTR() # define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); @@ -160,7 +160,7 @@ # define END_OF_INSTR_NO_TRACE() #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG # define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ x86emu_dump_regs(); \ @@ -176,7 +176,7 @@ # define RETURN_TRACE(n,u,v) #endif -#ifdef CONFIG_DEBUG +#ifdef DEBUG #define DB(x) x #else #define DB(x)

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Re: [coreboot] [v2] r4780 - trunk/coreboot-v2/src
by Myles Watson 16 Oct '09

16 Oct '09

> Modified: > trunk/coreboot-v2/src/Kconfig > Log: > Start documenting a few kconfig variables and user-visible options. > > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> I don't think this is trivial. > Modified: trunk/coreboot-v2/src/Kconfig > =================================================================== > --- trunk/coreboot-v2/src/Kconfig 2009-10-15 14:23:33 UTC (rev 4779) > +++ trunk/coreboot-v2/src/Kconfig 2009-10-15 17:49:07 UTC (rev 4780) > @@ -239,12 +243,27 @@ > > config HAVE_ACPI_TABLES > bool > + help > + This variable specifies whether a given board has ACPI table > support. > + It is usually set in mainboard/*/Kconfig. > + Whether or not the ACPI tables are actually generated by coreboot > + is configurable by the user via GENERATE_ACPI_TABLES. I think comments, not help text is the correct place to put comments about CONFIG variables that will never show up in a menu. Maybe some of it should just go into documentation/. Thanks, Myles

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[v2] r4781 - trunk/coreboot-v2/src/drivers/generic/debug
by svn＠coreboot.org 15 Oct '09

15 Oct '09

Author: stepan Date: 2009-10-16 00:40:41 +0200 (Fri, 16 Oct 2009) New Revision: 4781 Modified: trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c Log: undo another accidential rename of X -> CONFIG_X (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c =================================================================== --- trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c 2009-10-15 17:49:07 UTC (rev 4780) +++ trunk/coreboot-v2/src/drivers/generic/debug/debug_dev.c 2009-10-15 22:40:41 UTC (rev 4781) @@ -238,7 +238,7 @@ switch(dev->path.pnp.device) { case 0: parent = dev->bus->dev; - printk_debug("CONFIG_DEBUG: %s", dev_path(parent)); + printk_debug("DEBUG: %s", dev_path(parent)); if(parent->chip_ops && parent->chip_ops->name) { printk_debug(": %s\n", parent->chip_ops->name); } else {

1 0

[v2] r4780 - trunk/coreboot-v2/src
by svn＠coreboot.org 15 Oct '09

15 Oct '09

Author: uwe Date: 2009-10-15 19:49:07 +0200 (Thu, 15 Oct 2009) New Revision: 4780 Modified: trunk/coreboot-v2/src/Kconfig Log: Start documenting a few kconfig variables and user-visible options. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/Kconfig =================================================================== --- trunk/coreboot-v2/src/Kconfig 2009-10-15 14:23:33 UTC (rev 4779) +++ trunk/coreboot-v2/src/Kconfig 2009-10-15 17:49:07 UTC (rev 4780) @@ -195,6 +195,10 @@ config HAVE_OPTION_TABLE bool default y + help + This variable specifies whether a given board has a cmos.layout + file containing NVRAM/CMOS bit definitions. + It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig. config PIRQ_ROUTE bool @@ -239,12 +243,27 @@ config HAVE_ACPI_TABLES bool + help + This variable specifies whether a given board has ACPI table support. + It is usually set in mainboard/*/Kconfig. + Whether or not the ACPI tables are actually generated by coreboot + is configurable by the user via GENERATE_ACPI_TABLES. config HAVE_MP_TABLE bool + help + This variable specifies whether a given board has MP table support. + It is usually set in mainboard/*/Kconfig. + Whether or not the MP table is actually generated by coreboot + is configurable by the user via GENERATE_MP_TABLE. config HAVE_PIRQ_TABLE bool + help + This variable specifies whether a given board has PIRQ table support. + It is usually set in mainboard/*/Kconfig. + Whether or not the PIRQ table is actually generated by coreboot + is configurable by the user via GENERATE_PIRQ_TABLE. config HAVE_HIGH_TABLES bool @@ -268,17 +287,30 @@ depends on HAVE_ACPI_TABLES bool "Generate ACPI tables" default y + help + Generate ACPI tables for this board. + If unsure, say Y. + config GENERATE_MP_TABLE depends on HAVE_MP_TABLE bool "Generate an MP table" default y + help + Generate an MP table (conforming to the Intel MultiProcessor + specification 1.4) for this board. + If unsure, say Y. + config GENERATE_PIRQ_TABLE depends on HAVE_PIRQ_TABLE bool "Generate a PIRQ table" default y + help + Generate a PIRQ table for this board. + If unsure, say Y. + endmenu menu "Payload"

1 0

Re: [coreboot] [v2] r4776 - trunk/coreboot-v2/src/arch/i386/lib
by Stefan Reinauer 15 Oct '09

15 Oct '09

svn(a)coreboot.org wrote: > Author: hailfinger > Date: 2009-10-15 01:51:05 +0200 (Thu, 15 Oct 2009) > New Revision: 4776 > > Modified: > trunk/coreboot-v2/src/arch/i386/lib/cbfs_and_run.c > Log: > cbfs_and_run_core() did not check the return code of cbfs_load_stage() > and jumped to (void*)-1 on error. > Die properly instead. > I didn't use die() because that caused a linker error. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Acked-by: Myles Watson <mylesgw(a)gmail.com> > > > Modified: trunk/coreboot-v2/src/arch/i386/lib/cbfs_and_run.c > =================================================================== > --- trunk/coreboot-v2/src/arch/i386/lib/cbfs_and_run.c 2009-10-14 20:49:49 UTC (rev 4775) > +++ trunk/coreboot-v2/src/arch/i386/lib/cbfs_and_run.c 2009-10-14 23:51:05 UTC (rev 4776) > @@ -11,6 +11,11 @@ > u8 *dst; > print_debug("Jumping to image.\r\n"); > dst = cbfs_load_stage(filename); > + if (dst == (void *) -1) { > + /* We should use die() here. */ > + print_emerg("Loading stage failed!\n"); > + for (;;); > + } > Can we do for (;;) asm("hlt"); instead? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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coreboot October 2009