coreboot October 2009

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[PATCH] Drop cpu/x86/fpu/{Config.lb,Makefile.inc}
by Peter Stuge 17 Oct '09

17 Oct '09

2 2

[v2] r4799 - in trunk/coreboot-v2/src/cpu: amd/model_10xxx amd/model_fxx amd/model_gx1 amd/model_gx2 amd/model_lx intel/ep80579 intel/model_1067x intel/model_69x intel/model_6dx intel/model_6ex intel/model_6fx intel/model_6xx intel/model_f0x intel/model_f1x intel/model_f2x intel/model_f3x intel/model_f4x via/model_c3 via/model_c7 x86/fpu
by svn＠coreboot.org 17 Oct '09

17 Oct '09

Author: stuge Date: 2009-10-17 03:12:42 +0200 (Sat, 17 Oct 2009) New Revision: 4799 Removed: trunk/coreboot-v2/src/cpu/x86/fpu/Config.lb trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb trunk/coreboot-v2/src/cpu/amd/model_gx1/Config.lb trunk/coreboot-v2/src/cpu/amd/model_gx2/Config.lb trunk/coreboot-v2/src/cpu/amd/model_lx/Config.lb trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb trunk/coreboot-v2/src/cpu/intel/model_69x/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6dx/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb trunk/coreboot-v2/src/cpu/intel/model_6xx/Config.lb trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb trunk/coreboot-v2/src/cpu/via/model_c3/Config.lb trunk/coreboot-v2/src/cpu/via/model_c7/Config.lb Log: Drop src/cpu/x86/fpu/{Config.lb,Makefile.inc} since they are also empty Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -25,7 +25,6 @@ default CONFIG_HAVE_MOVNTI=1 default CONFIG_CPU_ADDR_BITS=48 dir /cpu/x86/tsc -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/pae Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -6,7 +6,6 @@ default CONFIG_HAVE_MOVNTI=1 default CONFIG_CPU_ADDR_BITS=40 dir /cpu/x86/tsc -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/pae Modified: trunk/coreboot-v2/src/cpu/amd/model_gx1/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx1/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/amd/model_gx1/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -1,5 +1,4 @@ dir /cpu/x86/tsc -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -1,5 +1,4 @@ dir /cpu/x86/tsc -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_lx/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -1,5 +1,4 @@ dir /cpu/x86/tsc -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -21,7 +21,6 @@ object ep80579.o dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_1067x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -3,7 +3,6 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_69x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_69x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_69x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -1,6 +1,5 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_6dx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6dx/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_6dx/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -1,6 +1,5 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -3,7 +3,6 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -3,7 +3,6 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_6xx/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_6xx/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -1,6 +1,5 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_f0x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -2,7 +2,6 @@ default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_f1x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -2,7 +2,6 @@ default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_f2x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -2,7 +2,6 @@ default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_f3x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -2,7 +2,6 @@ default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/intel/model_f4x/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -2,7 +2,6 @@ default CONFIG_HAVE_MOVNTI=1 dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/via/model_c3/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c3/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/via/model_c3/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -21,7 +21,6 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/cpu/via/model_c7/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/via/model_c7/Config.lb 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/via/model_c7/Config.lb 2009-10-17 01:12:42 UTC (rev 4799) @@ -21,7 +21,6 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Deleted: trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc 2009-10-16 22:39:55 UTC (rev 4798) +++ trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc 2009-10-17 01:12:42 UTC (rev 4799) @@ -1 +0,0 @@ -#

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build service results for r4796
by coreboot information 17 Oct '09

17 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4796 to the coreboot repository. This caused the following changes: Change Log: This is a snapshot as the availability of the systems for this project is now uncertain, and I can't invest the remaining time needed to get it done. Status is that memory is still not quite configured correctly. It is close but here are DRAM Row Boundary registers. Here is coreboot 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 This is close. But: 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 is the real hardware. So we are somehow missing those last slots. I think it's because the SPD connections and the chip connections differ, some dumping of RAM registers differ. But it's very close. This is under serialice. Once we get to this point we get stuck here: Copying coreboot to RAM. Copying coreboot to RAM. Copying coreboot to RAM. Forever. Here is the total config for 0:0.0 from coreboot: PCI: 00:00.00 00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c 80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00 90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0 d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00 f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00 And from factory: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00 I want to commit this because even if I get no further, someone else might. Note that for serialice you need the following temporary patch as well: Index: src/superio/nsc/pc8374/pc8374_early_init.c =================================================================== --- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791) +++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy) @@ -29,7 +29,8 @@ static void pc8374_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); +/* don't disable for now, it kills serialice */ + pnp_set_enable(dev, 1); Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of amd:db800 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4796&device=db800&vendor=a… Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4796&device=msm800sev&vend… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

2 1

build service results for r4798
by coreboot information 17 Oct '09

17 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4798 to the coreboot repository. This caused the following changes: Change Log: Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of amd:db800 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4798&device=db800&vendor=a… Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4798&device=msm800sev&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r4797
by coreboot information 17 Oct '09

17 Oct '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4797 to the coreboot repository. This caused the following changes: Change Log: Drop duplicate version of the documentation/cbfs.txt file as discussed. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:db800 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4797&device=db800&vendor=a… Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4797&device=msm800sev&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4798 - trunk/coreboot-v2/src/console
by svn＠coreboot.org 17 Oct '09

17 Oct '09

Author: uwe Date: 2009-10-17 00:39:55 +0200 (Sat, 17 Oct 2009) New Revision: 4798 Modified: trunk/coreboot-v2/src/console/Kconfig Log: Make COM port selection and BAUD rate a "choice" for better usability. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-10-16 22:07:20 UTC (rev 4797) +++ trunk/coreboot-v2/src/console/Kconfig 2009-10-16 22:39:55 UTC (rev 4798) @@ -2,22 +2,83 @@ # TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete. config CONSOLE_SERIAL8250 - bool "Enable serial port console output" + bool "Serial port console output" default y help Send coreboot debug output to a serial port console. -# TODO: COM1, COM2 etc. +choice + prompt "COM port" + default CONSOLE_SERIAL_COM1 + depends on CONSOLE_SERIAL8250 + +config CONSOLE_SERIAL_COM1 + bool "COM1/ttyS0" + help + Serial console on COM1/ttyS0. +config CONSOLE_SERIAL_COM2 + bool "COM2/ttyS1" + help + Serial console on COM2/ttyS1. +config CONSOLE_SERIAL_COM3 + bool "COM3/ttyS2" + help + Serial console on COM3/ttyS2. +config CONSOLE_SERIAL_COM4 + bool "COM4/ttyS3" + help + Serial console on COM4/ttyS3. + +endchoice + config TTYS0_BASE - hex "I/O base for the serial port" + hex depends on CONSOLE_SERIAL8250 - default 0x3f8 + default 0x3f8 if CONSOLE_SERIAL_COM1 + default 0x2f8 if CONSOLE_SERIAL_COM2 + default 0x3e8 if CONSOLE_SERIAL_COM3 + default 0x2e8 if CONSOLE_SERIAL_COM4 + help + Map the COM port names to the respective I/O port. -config TTYS0_BAUD - int "Serial port BAUD rate" +choice + prompt "BAUD rate" + default CONSOLE_SERIAL_115200 depends on CONSOLE_SERIAL8250 - default 115200 +config CONSOLE_SERIAL_115200 + bool "115200" + help + Set serial port BAUD rate to 115200. +config CONSOLE_SERIAL_57600 + bool "57600" + help + Set serial port BAUD rate to 57600. +config CONSOLE_SERIAL_38400 + bool "38400" + help + Set serial port BAUD rate to 38400. +config CONSOLE_SERIAL_19200 + bool "19200" + help + Set serial port BAUD rate to 19200. +config CONSOLE_SERIAL_9600 + bool "9600" + help + Set serial port BAUD rate to 9600. + +endchoice + +config TTYS0_BAUD + int + default 115200 if CONSOLE_SERIAL_115200 + default 57600 if CONSOLE_SERIAL_57600 + default 38400 if CONSOLE_SERIAL_38400 + default 19200 if CONSOLE_SERIAL_19200 + default 9600 if CONSOLE_SERIAL_9600 + help + Map the BAUD rates to an integer. + # TODO: Allow user-friendly selection of settings other than 8n1. config TTYS0_LCS int @@ -25,7 +86,7 @@ depends on CONSOLE_SERIAL8250 config SERIAL_POST - bool "Enable POST output on the serial port console" + bool "Show POST codes on the serial port console" depends on CONSOLE_SERIAL8250 default n help

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[PATCH] Drop duplicate CBFS docs
by Uwe Hermann 17 Oct '09

17 Oct '09

We currently have - documentation/cbfs.txt - util/cbfstool/README (almost exact copy of the above) - http://www.coreboot.org/CBFS (wikified copy of the above). Attached patch drops the two text files in favor for the wiki page, which is a lot easier to keep up-to-date. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4797 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 17 Oct '09

17 Oct '09

Author: uwe Date: 2009-10-17 00:07:20 +0200 (Sat, 17 Oct 2009) New Revision: 4797 Removed: trunk/coreboot-v2/util/cbfstool/README Log: Drop duplicate version of the documentation/cbfs.txt file as discussed. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/coreboot-v2/util/cbfstool/README =================================================================== --- trunk/coreboot-v2/util/cbfstool/README 2009-10-16 22:07:15 UTC (rev 4796) +++ trunk/coreboot-v2/util/cbfstool/README 2009-10-16 22:07:20 UTC (rev 4797) @@ -1,337 +0,0 @@ -Coreboot CBFS Specification -Jordan Crouse <jordan(a)cosmicpenguin.net> - -= Introduction = - -This document describes the coreboot CBFS specification (from here referred -to as CBFS). CBFS is a scheme for managing independent chunks of data in -a system ROM. Though not a true filesystem, the style and concepts are -similar. - -= Architecture = - -The CBFS architecture looks like the following: - -/---------------\ <-- Start of ROM -| /-----------\ | --| -| | Header | | | -| |-----------| | | -| | Name | | |-- Component -| |-----------| | | -| |Data | | | -| |.. | | | -| \-----------/ | --| -| | -| /-----------\ | -| | Header | | -| |-----------| | -| | Name | | -| |-----------| | -| |Data | | -| |.. | | -| \-----------/ | -| | -| ... | -| /-----------\ | -| | | | -| | Bootblock | | -| | --------- | | -| | Reset | | <- 0xFFFFFFF0 -| \-----------/ | -\---------------/ - - -The CBFS architecture consists of a binary associated with a physical -ROM disk referred hereafter as the ROM. A number of independent of -components, each with a header prepended on to data are located within -the ROM. The components are nominally arranged sequentially, though they -are aligned along a pre-defined boundary. - -The bootblock occupies the last 20k of the ROM. Within -the bootblock is a master header containing information about the ROM -including the size, alignment of the components, and the offset of the -start of the first CBFS component within the ROM. - -= Master Header = - -The master header contains essential information about the ROM that is -used by both the CBFS implementation within coreboot at runtime as well -as host based utilities to create and manage the ROM. The master header -will be located somewhere within the bootblock (high end of the ROM). A -pointer to the location of the header will be located at offset --4 from the end of the ROM. This translates to address 0xFFFFFFFC on a -normal x86 system. The pointer will be to physical memory somewhere -between - 0xFFFF0000 and 0xFFFFFFF0. This makes it easier for coreboot -to locate the header at run time. Build time utilities will -need to read the pointer and do the appropriate math to locate the header. - -The following is the structure of the master header: - -struct cbfs_header { - unsigned int magic; - unsigned int version; - unsigned int romsize; - unsigned int bootblocksize; - unsigned int align; - unsigned int offset; - unsigned int pad[2]; -}; - -The meaning of each member is as follows: - -'magic' is a 32 bit number that identifies the ROM as a CBFS type. The magic -number is 0x4F524243, which is 'ORBC' in ASCII. - -'version' is a 32 bit number that identifies the version of CBFS. The current -version is 0x31313131 ('1111' in ASCII) which is endian-independent. - -'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from -0xFFFFFFFF to locate the beginning of the ROM in memory. - -'bootblocksize' is the boot block size in bytes. There is no limitation on -the boot block size as in v3. - -'align' is the number of bytes that each component is aligned to within the -ROM. This is used to make sure that each component is aligned correctly with -regards to the erase block sizes on the ROM - allowing one to replace a -component at runtime without disturbing the others. - -'offset' is the offset of the the first CBFS component (from the start of -the ROM). This is to allow for arbitrary space to be left at the beginning -of the ROM for things like embedded controller firmware. - -'pad' rounds the header to 32 bytes and reserves a little room for later use. - -= Bootblock = -The bootblock is a mandatory component in the ROM. It is located in the -last bootblocksize bytes of ROM space, and contains, among other things, -the location of the master header and the entry point for the loader -firmware. The bootblock does not have a component header attached to it. - - -= Components = - -CBFS components are placed in the ROM starting at 'offset' specified in -the master header and ending at the bootblock. Thus the total size available -for components in the ROM is (ROM size - bootblocksize - 'offset'). Each CBFS -component is to be aligned according to the 'align' value in the header. -Thus, if a component of size 1052 is located at offset 0 with an 'align' value -of 1024, the next component will be located at offset 2048. - -Each CBFS component will be indexed with a unique ASCII string name of -unlimited size. - -Each CBFS component starts with a header: - -struct cbfs_file { - char magic[8]; - unsigned int len; - unsigned int type; - unsigned int checksum; - unsigned int offset; -}; - -'magic' is a magic value used to identify the header. During runtime, -coreboot will scan the ROM looking for this value. The default magic is -the string 'LARCHIVE'. - -'len' is the length of the data, not including the size of the header and -the size of the name. - -'type' is a 32 bit number indicating the type of data that is attached. -The data type is used in a number of ways, as detailed in the section -below. - -'checksum' is a 32bit checksum of the entire component, including the -header and name. - -'offset' is the start of the component data, based off the start of the header. -The difference between the size of the header and offset is the size of the -component name. - -Immediately following the header will be the name of the component, which will -null terminated and 16 byte aligned. The following picture shows the -structure of the header: - -/--------\ <- start -| Header | -|--------| <- sizeof(struct cbfs_file) -| Name | -|--------| <- 'offset' -| Data | -| ... | -\--------/ <- start + 'offset' + 'len' - -== Searching Alogrithm == - -To locate a specific component in the ROM, one starts at the 'offset' -specified in the CBFS master header. For this example, the offset will -be 0. - -From that offset, the code should search for the magic string on the -component, jumping 'align' bytes each time. So, assuming that 'align' is -16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc. -If the offset ever exceeds the allowable range for CBFS components, then no -component was found. - -Upon recognizing a component, the software then has to search for the -specific name of the component. This is accomplished by comparing the -desired name with the string on the component located at -offset + sizeof(struct cbfs_file). If the string matches, then the component -has been located, otherwise the software should add 'offset' + 'len' to -the offset and resume the search for the magic value. - -== Data Types == - -The 'type' member of struct cbfs_file is used to identify the content -of the component data, and is used by coreboot and other -run-time entities to make decisions about how to handle the data. - -There are three component types that are essential to coreboot, and so -are defined here. - -=== Stages === - -Stages are code loaded by coreboot during the boot process. They are -essential to a successful boot. Stages are comprised of a single blob -of binary data that is to be loaded into a particular location in memory -and executed. The uncompressed header contains information about how -large the data is, and where it should be placed, and what additional memory -needs to be cleared. - -Stages are assigned a component value of 0x10. When coreboot sees this -component type, it knows that it should pass the data to a sub-function -that will process the stage. - -The following is the format of a stage component: - -/--------\ -| Header | -|--------| -| Binary | -| .. | -\--------/ - -The header is defined as: - -struct cbfs_stage { - unsigned int compression; - unsigned long long entry; - unsigned long long load; - unsigned int len; - unsigned int memlen; -}; - -'compression' is an integer defining how the data is compressed. There -are three compression types defined by this version of the standard: -none (0x0), lzma (0x1), and nrv2b (0x02), though additional types may be -added assuming that coreboot understands how to handle the scheme. - -'entry' is a 64 bit value indicating the location where the program -counter should jump following the loading of the stage. This should be -an absolute physical memory address. - -'load' is a 64 bit value indicating where the subsequent data should be -loaded. This should be an absolute physical memory address. - -'len' is the length of the compressed data in the component. - -'memlen' is the amount of memory that will be used by the component when -it is loaded. - -The component data will start immediately following the header. - -When coreboot loads a stage, it will first zero the memory from 'load' to -'memlen'. It will then decompress the component data according to the -specified scheme and place it in memory starting at 'load'. Following that, -it will jump execution to the address specified by 'entry'. -Some components are designed to execute directly from the ROM - coreboot -knows which components must do that and will act accordingly. - -=== Payloads === - -Payloads are loaded by coreboot following the boot process. - -Stages are assigned a component value of 0x20. When coreboot sees this -component type, it knows that it should pass the data to a sub-function -that will process the payload. Furthermore, other run time -applications such as 'bayou' may easily index all available payloads -on the system by searching for the payload type. - - -The following is the format of a stage component: - -/-----------\ -| Header | -| Segment 1 | -| Segment 2 | -| ... | -|-----------| -| Binary | -| .. | -\-----------/ - -The header is as follows: - -struct cbfs_payload { - struct cbfs_payload_segment segments; -} - -The header contains a number of segments corresponding to the segments -that need to be loaded for the payload. - -The following is the structure of each segment header: - -struct cbfs_payload_segment { - unsigned int type; - unsigned int compression; - unsigned int offset; - unsigned long long load_addr; - unsigned int len; - unsigned int mem_len; -}; - -'type' is the type of segment, one of the following: - -PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code -PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data -PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment - should be zeroed -PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for - the payload -PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point - for the payload - -'compression' is the compression scheme for the segment. Each segment can -be independently compressed. There are three compression types defined by -this version of the standard: none (0x0), lzma (0x1), and nrv2b (0x02), -though additional types may be added assuming that coreboot understands -how to handle the scheme. - -'offset' is the address of the data within the component, starting from -the component header. - -'load_addr' is a 64 bit value indicating where the segment should be placed -in memory. - -'len' is a 32 bit value indicating the size of the segment within the -component. - -'mem_len' is the size of the data when it is placed into memory. - -The data will located immediately following the last segment. - -=== Option ROMS === - -The third specified component type will be Option ROMs. Option ROMS will -have component type '0x30'. They will have no additional header, the -uncompressed binary data will be located in the data portion of the -component. - -=== NULL === - -There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is -the "don't care" component type. This can be used when the component -type is not necessary (such as when the name of the component is unique. -i.e. option_table). It is recommended that all components be assigned a -unique type, but NULL can be used when the type does not matter.

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[v2] r4796 - trunk/coreboot-v2/src/mainboard/dell/s1850
by svn＠coreboot.org 17 Oct '09

17 Oct '09

Author: rminnich Date: 2009-10-17 00:07:15 +0200 (Sat, 17 Oct 2009) New Revision: 4796 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c trunk/coreboot-v2/src/mainboard/dell/s1850/debug.c Log: This is a snapshot as the availability of the systems for this project is now uncertain, and I can't invest the remaining time needed to get it done. Status is that memory is still not quite configured correctly. It is close but here are DRAM Row Boundary registers. Here is coreboot 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 This is close. But: 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 is the real hardware. So we are somehow missing those last slots. I think it's because the SPD connections and the chip connections differ, some dumping of RAM registers differ. But it's very close. This is under serialice. Once we get to this point we get stuck here: Copying coreboot to RAM. Copying coreboot to RAM. Copying coreboot to RAM. Forever. Here is the total config for 0:0.0 from coreboot: PCI: 00:00.00 00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00 70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c 80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00 90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0 d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00 f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00 And from factory: 00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09) 00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00 50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10 60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00 70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c 80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00 90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07 a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00 c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0 d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00 e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00 f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00 I want to commit this because even if I get no further, someone else might. Note that for serialice you need the following temporary patch as well: Index: src/superio/nsc/pc8374/pc8374_early_init.c =================================================================== --- src/superio/nsc/pc8374/pc8374_early_init.c (revision 4791) +++ src/superio/nsc/pc8374/pc8374_early_init.c (working copy) @@ -29,7 +29,8 @@ static void pc8374_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); +/* don't disable for now, it kills serialice */ + pnp_set_enable(dev, 1); Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig 2009-10-16 20:15:06 UTC (rev 4795) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Kconfig 2009-10-16 22:07:15 UTC (rev 4796) @@ -35,6 +35,12 @@ default 0x016c depends on BOARD_DELL_S1850 +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1028 + depends on BOARD_DELL_S1850 + + config MAX_CPUS int default 2 Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-16 20:15:06 UTC (rev 4795) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/auto.c 2009-10-16 22:07:15 UTC (rev 4796) @@ -61,6 +61,9 @@ return smbus_read_byte(device, address); } +/* this is very highly mainboard dependent, related to wiring */ +/* from factory BIOS via lspci */ +#define DIMM_MAP_LOGICAL 0x2841 #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" @@ -184,6 +187,8 @@ .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + /* the wiring on this part is really messed up */ + /* this is my best guess so far */ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, } @@ -331,24 +336,28 @@ #if 1 enable_smbus(); #endif -#if 1 +#if 0 // dump_spd_registers(&cpu[0]); int i; for(i = 0; i < 1; i++) { dump_spd_registers(); } #endif +#if 1 + show_dram_slots(); +#endif disable_watchdogs(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); // memreset_setup(); + sdram_initialize(ARRAY_SIZE(mch), mch); -#if 1 +#if 0 dump_pci_devices(); #endif #if 1 dump_pci_device(PCI_DEV(0, 0x00, 0)); - dump_bar14(PCI_DEV(0, 0x00, 0)); +// dump_bar14(PCI_DEV(0, 0x00, 0)); #endif #if 1 // temporarily disabled Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/debug.c =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/debug.c 2009-10-16 20:15:06 UTC (rev 4795) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/debug.c 2009-10-16 22:07:15 UTC (rev 4796) @@ -205,69 +205,6 @@ } } -#if 0 -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\r\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\r\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\r\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\r\n"); - } - } -} -#endif - void dump_spd_registers(void) { unsigned device; @@ -301,6 +238,30 @@ } } +void show_dram_slots(void) +{ + unsigned device; + device = SMBUS_MEM_DEVICE_START; + while(device <= SMBUS_MEM_DEVICE_END) { + int status = 0; + int i; + print_debug("\r\n"); + print_debug("dimm "); + print_debug_hex8(device); + + status = smbus_read_byte(device, 0); + if (status < 0) { + print_debug("bad device: "); + } else { + print_debug("present: "); + } + print_debug_hex8(status); + print_debug("\r\n"); + device += SMBUS_MEM_DEVICE_INC; + print_debug("\n"); + } +} + void dump_ipmi_registers(void) { unsigned device;

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[v2] r4795 - trunk/coreboot-v2/src/console
by svn＠coreboot.org 16 Oct '09

16 Oct '09

Author: myles Date: 2009-10-16 22:15:06 +0200 (Fri, 16 Oct 2009) New Revision: 4795 Modified: trunk/coreboot-v2/src/console/console.c Log: Revert deletion that snuck in to 4794. Sorry. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/console/console.c =================================================================== --- trunk/coreboot-v2/src/console/console.c 2009-10-16 19:29:45 UTC (rev 4794) +++ trunk/coreboot-v2/src/console/console.c 2009-10-16 20:15:06 UTC (rev 4795) @@ -81,3 +81,11 @@ outb(value, 0x80); #endif } + +/* Report a fatal error */ +void __attribute__((noreturn)) die(const char *msg) +{ + printk_emerg("%s", msg); + post_code(0xff); + while (1); /* Halt */ +}

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coreboot October 2009