coreboot September 2008

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r230 - in buildrom-devel: bin config/platforms packages/coreboot-v2 packages/filo/conf packages/kernel packages/roms
by svn＠coreboot.org 22 Sep '08

22 Sep '08

Author: jcrouse Date: 2008-09-22 23:06:10 +0200 (Mon, 22 Sep 2008) New Revision: 230 Added: buildrom-devel/bin/show-instructions.sh buildrom-devel/config/platforms/dbm690t.conf buildrom-devel/packages/coreboot-v2/dbm690t.mk buildrom-devel/packages/filo/conf/dbm690t-Config buildrom-devel/packages/kernel/dbm690t.mk buildrom-devel/packages/roms/amd_r690.mk buildrom-devel/packages/roms/amd_r690_instructions Log: Add AMD dbm690t mainboard to buildrom. The dbm690t uses an embedded VBIOS which buildrom can attach to the ROM image. (The previous commit missed all the added files, my bad - Jordan) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Ward Vandewege <ward(a)gnu.org> Added: buildrom-devel/bin/show-instructions.sh =================================================================== --- buildrom-devel/bin/show-instructions.sh (rev 0) +++ buildrom-devel/bin/show-instructions.sh 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,7 @@ +#!/bin/sh + +tmp=`tempfile` +cat $1 | sed -e "s:%DESTFILE%:$2:" > $tmp +`dirname $0`/../scripts/kconfig/lxdialog/lxdialog --textbox $tmp 20 75 +rm -rf $tmp + Property changes on: buildrom-devel/bin/show-instructions.sh ___________________________________________________________________ Added: svn:executable + * Added: buildrom-devel/config/platforms/dbm690t.conf =================================================================== --- buildrom-devel/config/platforms/dbm690t.conf (rev 0) +++ buildrom-devel/config/platforms/dbm690t.conf 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,64 @@ +# Support for the AMD Herring Platform + +#### Platform configuration + +CC=gcc +STRIP=strip +AS=as + +ifeq ($(CONFIG_TARGET_64BIT),y) +TARGET_ARCH=x86_64 +CFLAGS_platform = +else +TARGET_ARCH=i686 +CFLAGS_platform = +endif + +# Targets + +KERNEL_MK=$(PACKAGE_DIR)/kernel/dbm690t.mk +CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/dbm690t.mk + +# kernel configuration (for LAB) + +ifeq ($(CONFIG_TARGET_64BIT),y) +KERNEL_VERSION=2.6.22.2 +KERNEL_MK=$(PACKAGE_DIR)/kernel/dbm690t-x86_64.mk +KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-dbm690t-x86_64 +BUSYBOX_CONFIG=defconfig-dbm690t-x86_64 +UCLIBC_VER=0.9.29 +UCLIBC_CONFIG=defconfig-x86_64 +else +KERNEL_VERSION=2.6.20.2 +KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-dbm690t +UCLIBC_VER=0.9.29 +endif + +#UCLIBC_ARCH=$(TARGET_ARCH) + +# Etherboot configuration +ETHERBOOT_ARCH=i386 + +# coreboot configuration + +COREBOOT_VENDOR=amd +CBV2_CONFIG=Config.lb +CBV2_PAYLOAD_FILE_EXT=elf + +CBV3_TAG=HEAD + +COREBOOT_BOARD=dbm690t +CBV2_TDIR=dbm690t +CBV2_TAG=3590 + +# FILO configuration + +FILO_CONFIG=dbm690t-Config + +# VIDEO BIOS configuration + +ifndef $(CONFIG_AMD_R690_VBIOS) +AMD_R690_VBIOS_LOCATION := $(BASE_DIR)/sources/amd_rs690_vbios.bin +else +AMD_R690_VBIOS_LOCATION = $(subst ",,$(CONFIG_AMD_R690_VBIOS)) +endif Added: buildrom-devel/packages/coreboot-v2/dbm690t.mk =================================================================== --- buildrom-devel/packages/coreboot-v2/dbm690t.mk (rev 0) +++ buildrom-devel/packages/coreboot-v2/dbm690t.mk 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,22 @@ +# This is the AMD DBM690T coreboot target + +CBV2_PATCHES= + +# Make sure we have the tools we need to accomplish this +HAVE_IASL:=$(call find-tool,iasl) + +ifeq ($(HAVE_IASL),n) +$(error To build coreboot, you need to install the 'iasl' tool) +endif + +ifeq ($(CONFIG_PLATFORM_DBM690T),y) +ifeq ($(CONFIG_SIMNOW),y) +CBV2_PATCHES += $(PACKAGE_DIR)/coreboot-v2/patches/simnow.patch +endif +endif + +include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc + +coreboot: generic-coreboot +coreboot-clean: generic-coreboot-clean +coreboot-distclean: generic-coreboot-distclean Added: buildrom-devel/packages/filo/conf/dbm690t-Config =================================================================== --- buildrom-devel/packages/filo/conf/dbm690t-Config (rev 0) +++ buildrom-devel/packages/filo/conf/dbm690t-Config 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,102 @@ +# !!! NOTE !!! +# Do NOT add spaces or comments at the end of option lines. +# It confuses some versions of make. + +# Use grub instead of autoboot? +USE_GRUB = 1 + +# Grub menu.lst path +# SATA +# MENULST_FILE = "hda1:/boot/filo/menu.lst" +# PATA +MENULST_FILE = "hde1:/boot/filo/menu.lst" + +# time before default menu.lst is chosen. Set to 0 to ignore +MENULST_TIMEOUT = 3 + +# Image filename for automatic boot and optional command line parameter +#AUTOBOOT_FILE = "hde1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200" +#AUTOBOOT_FILE = "mem@0xfff80000" +#AUTOBOOT_FILE = "hde1@0" +#AUTOBOOT_FILE = "uda1:/vmlinuz.elf" + +# Time in second before booting AUTOBOOT_FILE +AUTOBOOT_DELAY = 2 + +# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus +IDE_DISK = 1 + +# Add a short delay when polling status registers +# (required on some broken SATA controllers) +# NOTE: Slows down access significantly, so disable +# whenever possible. +#IDE_DISK_POLL_DELAY = 1 + +# Use PCMCIA compact flash on Via Epia MII10000 and MII6000E +# This device is referred to as hde. +#PCMCIA_CF = 1 + +# Driver for USB Storage +# USB_DISK = 1 + +# VGA text console +VGA_CONSOLE = 1 +PC_KEYBOARD = 1 + +# Serial console +SERIAL_CONSOLE = 1 +SERIAL_IOBASE = 0x3f8 +# if SERIAL_SPEED is commented out, the speed will not be changed. +#SERIAL_SPEED = 115200 + +# Filesystems +FSYS_EXT2FS = 1 +FSYS_FAT = 1 +#FSYS_JFS = 1 +#FSYS_MINIX = 1 +FSYS_REISERFS = 1 +#FSYS_XFS = 1 +FSYS_ISO9660 = 1 + +# Support for boot disk image in bootable CD-ROM (El Torito) +ELTORITO = 1 + +# PCI support +SUPPORT_PCI = 1 + +# Enable this to scan PCI busses above bus 0 +# AMD64 based boards do need this. +PCI_BRUTE_SCAN = 1 + +# Sound support (needs SUPPORT_PCI) +#SUPPORT_SOUND = 1 + +# Sound drivers +#VIA_SOUND = 1 + +# Debugging +DEBUG_ALL = 1 +#DEBUG_ELFBOOT = 1 +#DEBUG_ELFNOTE = 1 +#DEBUG_LINUXBIOS = 1 +#DEBUG_MALLOC = 1 +#DEBUG_MULTIBOOT = 1 +#DEBUG_SEGMENT = 1 +#DEBUG_SYS_INFO = 1 +#DEBUG_TIMER = 1 +#DEBUG_BLOCKDEV = 1 +#DEBUG_PCI = 1 +#DEBUG_VIA_SOUND = 1 +#DEBUG_LINUXLOAD = 1 +#DEBUG_IDE = 1 +#DEBUG_USB = 1 +#DEBUG_ELTORITO = 1 + +# i386 options + +# Loader for standard Linux kernel image, a.k.a. /vmlinuz +LINUX_LOADER = 1 + +# Boot FILO from Multiboot loader (eg. GRUB) +#MULTIBOOT_IMAGE = 1 + Added: buildrom-devel/packages/kernel/dbm690t.mk =================================================================== --- buildrom-devel/packages/kernel/dbm690t.mk (rev 0) +++ buildrom-devel/packages/kernel/dbm690t.mk 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,16 @@ +# Build file for the AMD DBM690T LAB kernel + +KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/ +KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2 + +# Kernel config is set in the platform configuration + +$(SOURCE_DIR)/$(KERNEL_SOURCE): + @ mkdir -p $(SOURCE_DIR) + @ wget $(WGET_Q) -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE) + +include $(PACKAGE_DIR)/kernel/kernel.inc + +kernel: generic-kernel +kernel-clean: generic-kernel-clean +kernel-distclean: generic-kernel-distclean Added: buildrom-devel/packages/roms/amd_r690.mk =================================================================== --- buildrom-devel/packages/roms/amd_r690.mk (rev 0) +++ buildrom-devel/packages/roms/amd_r690.mk 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_AMD_R690_USE_VBIOS),y) +OPTIONROM_TARGETS += $(AMD_R690_VBIOS_LOCATION) +CBV2_PREPEND := $(AMD_R690_VBIOS_LOCATION) +endif + +$(AMD_R690_VBIOS_LOCATION): + @ $(BIN_DIR)/show-instructions.sh \ + $(PACKAGE_DIR)/roms/amd_r690_instructions \ + $(AMD_R690_VBIOS_LOCATION) + @ echo "Unable to find $(AMD_R690_VBIOS_LOCATION)" + @ exit 1 Added: buildrom-devel/packages/roms/amd_r690_instructions =================================================================== --- buildrom-devel/packages/roms/amd_r690_instructions (rev 0) +++ buildrom-devel/packages/roms/amd_r690_instructions 2008-09-22 21:06:10 UTC (rev 230) @@ -0,0 +1,10 @@ +Please follow these instructions for downloading the video BIOS +for your R690 platform: + + * Download the latest video BIOS from: + http://url.goes.here/ + * Copy the file to: + %DESTFILE% + You may need to create the directory first. + +After copying the file, start the build again by typing 'make'.

1 0

r229 - in buildrom-devel: config/platforms packages/grub2 packages/roms
by svn＠coreboot.org 22 Sep '08

22 Sep '08

Author: jcrouse Date: 2008-09-22 22:56:04 +0200 (Mon, 22 Sep 2008) New Revision: 229 Modified: buildrom-devel/config/platforms/Config.in buildrom-devel/config/platforms/platforms.conf buildrom-devel/packages/grub2/grub2.mk buildrom-devel/packages/roms/roms.mk Log: Add AMD dbm690t mainboard to buildrom. The dbm690t uses an embedded VBIOS which buildrom can attach to the ROM image. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/Config.in =================================================================== --- buildrom-devel/config/platforms/Config.in 2008-09-18 16:30:48 UTC (rev 228) +++ buildrom-devel/config/platforms/Config.in 2008-09-22 20:56:04 UTC (rev 229) @@ -164,6 +164,12 @@ depends on COREBOOT_V2 select PLATFORM select PLATFORM_SUPPORT_64BIT + +config PLATFORM_DBM690T + bool "AMD dbM690T" + depends on VENDOR_AMD + select PLATFORM + select PLATFORM_SUPPORT_64BIT endchoice choice @@ -208,4 +214,35 @@ Say 'y' here to patch the build to work on an emulated platform in the AMD SimNow (TM) simulator +config AMD_R690_HEADLESS + bool "Build the R690 platform as headless (without VGA)" + depends on ADVANCED && PLATFORM_DBM690T + default n + help + Say 'y' here to build without the VGA BIOS for the + R690 chipset. This will result in no video graphics + for the platform. This is not likely what you want, + so you should say 'n' here unless you are absolutely + sure. + +config AMD_R690_USE_VBIOS + bool + depends on !AMD_R690_HEADLESS + default y + +config AMD_R690_CUSTOM_VBIOS + bool "Specify a custom location for the R690 video BIOS" + depends on AMD_R690_USE_VBIOS + help + Say 'y' here to specify a custom location for the R690 + video BIOS file. Otherwise, it will be looked for in a + default location. + +config AMD_R690_VBIOS + string "Location of the RS690 Video BIOS file" + depends on AMD_R690_CUSTOM_VBIOS + default "" + help + Specify the full pathname for your RS690 video BIOS file + endmenu Modified: buildrom-devel/config/platforms/platforms.conf =================================================================== --- buildrom-devel/config/platforms/platforms.conf 2008-09-18 16:30:48 UTC (rev 228) +++ buildrom-devel/config/platforms/platforms.conf 2008-09-22 20:56:04 UTC (rev 229) @@ -27,6 +27,7 @@ PLATFORM-$(CONFIG_PLATFORM_CHEETAH_FAM10) = serengeti_cheetah.conf PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf PLATFORM-$(CONFIG_PLATFORM_QEMU-X86) = qemu.conf +PLATFORM-$(CONFIG_PLATFORM_DBM690T) = dbm690t.conf include $(CONFIG_DIR)/platforms/$(PLATFORM-y) @@ -35,3 +36,5 @@ # For those platforms that have option roms, add the following line #DEPENDS-$(MYPLATFORM) += roms + +DEPENDS-$(CONFIG_PLATFORM_DBM690T) += roms Modified: buildrom-devel/packages/grub2/grub2.mk =================================================================== --- buildrom-devel/packages/grub2/grub2.mk 2008-09-18 16:30:48 UTC (rev 228) +++ buildrom-devel/packages/grub2/grub2.mk 2008-09-22 20:56:04 UTC (rev 229) @@ -22,11 +22,13 @@ serial terminal lar terminfo memdisk ata ls \ configfile boot hexdump linux multiboot ext2 +ifeq ($(CONFIG_PAYLOAD_GRUB2),y) HAVE_RUBY:=$(call find-tool,ruby) ifeq ($(HAVE_RUBY),n) $(error To build GRUB2, you need to install 'ruby') endif +endif $(SOURCE_DIR)/$(GRUB2_TAR): @ mkdir -p $(SOURCE_DIR) Modified: buildrom-devel/packages/roms/roms.mk =================================================================== --- buildrom-devel/packages/roms/roms.mk 2008-09-18 16:30:48 UTC (rev 228) +++ buildrom-devel/packages/roms/roms.mk 2008-09-22 20:56:04 UTC (rev 229) @@ -1,12 +1,13 @@ # Each platform that needs an option ROM or other binary blob is specified # here -OPTIONROM_TARGETS?= +OPTIONROM_TARGETS ?= -OPTIONROM-y = +OPTIONROMS-y = +OPTIONROMS-$(CONFIG_PLATFORM_DBM690T) += $(PACKAGE_DIR)/roms/amd_r690.mk ifneq ($(OPTIONROMS-y),) -include $(OPTIONROM-y) +include $(OPTIONROMS-y) endif $(ROM_DIR): @@ -15,8 +16,5 @@ roms: $(ROM_DIR) $(OPTIONROM_TARGETS) roms-clean: -ifneq ($(OPTIONROM_TARGETS),) - @ rm -rf $(OPTIONROM_TARGETS) -endif -roms-distclean: roms-clean +roms-distclean:

1 0

dbm690t buildrom patch
by Marc Jones 22 Sep '08

22 Sep '08

Patch attached. Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Add AMD dbm690t mainboard to buildrom. The dbm690t uses an embedded VBIOS which buildrom can attach to the ROM image. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Index: buildrom-devel/config/platforms/Config.in =================================================================== --- buildrom-devel.orig/config/platforms/Config.in 2008-08-11 10:04:01.000000000 -0600 +++ buildrom-devel/config/platforms/Config.in 2008-09-22 10:23:09.000000000 -0600 @@ -164,6 +164,12 @@ depends on COREBOOT_V2 select PLATFORM select PLATFORM_SUPPORT_64BIT + +config PLATFORM_DBM690T + bool "AMD dbM690T" + depends on VENDOR_AMD + select PLATFORM + select PLATFORM_SUPPORT_64BIT endchoice choice @@ -208,4 +214,35 @@ Say 'y' here to patch the build to work on an emulated platform in the AMD SimNow (TM) simulator +config AMD_R690_HEADLESS + bool "Build the R690 platform as headless (without VGA)" + depends on ADVANCED && PLATFORM_DBM690T + default n + help + Say 'y' here to build without the VGA BIOS for the + R690 chipset. This will result in no video graphics + for the platform. This is not likely what you want, + so you should say 'n' here unless you are absolutely + sure. + +config AMD_R690_USE_VBIOS + bool + depends on !AMD_R690_HEADLESS + default y + +config AMD_R690_CUSTOM_VBIOS + bool "Specify a custom location for the R690 video BIOS" + depends on AMD_R690_USE_VBIOS + help + Say 'y' here to specify a custom location for the R690 + video BIOS file. Otherwise, it will be looked for in a + default location. + +config AMD_R690_VBIOS + string "Location of the RS690 Video BIOS file" + depends on AMD_R690_CUSTOM_VBIOS + default "" + help + Specify the full pathname for your RS690 video BIOS file + endmenu Index: buildrom-devel/config/platforms/dbm690t.conf =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/config/platforms/dbm690t.conf 2008-09-21 15:51:11.000000000 -0600 @@ -0,0 +1,64 @@ +# Support for the AMD Herring Platform + +#### Platform configuration + +CC=gcc +STRIP=strip +AS=as + +ifeq ($(CONFIG_TARGET_64BIT),y) +TARGET_ARCH=x86_64 +CFLAGS_platform = +else +TARGET_ARCH=i686 +CFLAGS_platform = +endif + +# Targets + +KERNEL_MK=$(PACKAGE_DIR)/kernel/dbm690t.mk +CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/dbm690t.mk + +# kernel configuration (for LAB) + +ifeq ($(CONFIG_TARGET_64BIT),y) +KERNEL_VERSION=2.6.22.2 +KERNEL_MK=$(PACKAGE_DIR)/kernel/dbm690t-x86_64.mk +KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-dbm690t-x86_64 +BUSYBOX_CONFIG=defconfig-dbm690t-x86_64 +UCLIBC_VER=0.9.29 +UCLIBC_CONFIG=defconfig-x86_64 +else +KERNEL_VERSION=2.6.20.2 +KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-dbm690t +UCLIBC_VER=0.9.29 +endif + +#UCLIBC_ARCH=$(TARGET_ARCH) + +# Etherboot configuration +ETHERBOOT_ARCH=i386 + +# coreboot configuration + +COREBOOT_VENDOR=amd +CBV2_CONFIG=Config.lb +CBV2_PAYLOAD_FILE_EXT=elf + +CBV3_TAG=HEAD + +COREBOOT_BOARD=dbm690t +CBV2_TDIR=dbm690t +CBV2_TAG=3092 + +# FILO configuration + +FILO_CONFIG=dbm690t-Config + +# VIDEO BIOS configuration + +ifeq ($(CONFIG_AMD_R690_VBIOS),"") +AMD_R690_VBIOS_LOCATION := $(BASE_DIR)/sources/amd_rs690_vbios.bin +else +AMD_R690_VBIOS_LOCATION = $(subst ",,$(CONFIG_AMD_R690_VBIOS)) +endif Index: buildrom-devel/config/platforms/platforms.conf =================================================================== --- buildrom-devel.orig/config/platforms/platforms.conf 2008-09-11 12:41:29.000000000 -0600 +++ buildrom-devel/config/platforms/platforms.conf 2008-09-21 19:58:48.000000000 -0600 @@ -27,6 +27,7 @@ PLATFORM-$(CONFIG_PLATFORM_CHEETAH_FAM10) = serengeti_cheetah.conf PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf PLATFORM-$(CONFIG_PLATFORM_QEMU-X86) = qemu.conf +PLATFORM-$(CONFIG_PLATFORM_DBM690T) = dbm690t.conf include $(CONFIG_DIR)/platforms/$(PLATFORM-y) @@ -35,3 +36,5 @@ # For those platforms that have option roms, add the following line #DEPENDS-$(MYPLATFORM) += roms + +DEPENDS-$(CONFIG_PLATFORM_DBM690T) += roms Index: buildrom-devel/packages/coreboot-v2/dbm690t.mk =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/packages/coreboot-v2/dbm690t.mk 2008-09-21 15:51:11.000000000 -0600 @@ -0,0 +1,22 @@ +# This is the AMD DBM690T coreboot target + +CBV2_PATCHES= + +# Make sure we have the tools we need to accomplish this +HAVE_IASL:=$(call find-tool,iasl) + +ifeq ($(HAVE_IASL),n) +$(error To build coreboot, you need to install the 'iasl' tool) +endif + +ifeq ($(CONFIG_PLATFORM_DBM690T),y) +ifeq ($(CONFIG_SIMNOW),y) +CBV2_PATCHES += $(PACKAGE_DIR)/coreboot-v2/patches/simnow.patch +endif +endif + +include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc + +coreboot: generic-coreboot +coreboot-clean: generic-coreboot-clean +coreboot-distclean: generic-coreboot-distclean Index: buildrom-devel/packages/filo/conf/dbm690t-Config =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/packages/filo/conf/dbm690t-Config 2008-09-21 15:51:11.000000000 -0600 @@ -0,0 +1,102 @@ +# !!! NOTE !!! +# Do NOT add spaces or comments at the end of option lines. +# It confuses some versions of make. + +# Use grub instead of autoboot? +USE_GRUB = 1 + +# Grub menu.lst path +# SATA +# MENULST_FILE = "hda1:/boot/filo/menu.lst" +# PATA +MENULST_FILE = "hde1:/boot/filo/menu.lst" + +# time before default menu.lst is chosen. Set to 0 to ignore +MENULST_TIMEOUT = 3 + +# Image filename for automatic boot and optional command line parameter +#AUTOBOOT_FILE = "hde1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200" +#AUTOBOOT_FILE = "mem@0xfff80000" +#AUTOBOOT_FILE = "hde1@0" +#AUTOBOOT_FILE = "uda1:/vmlinuz.elf" + +# Time in second before booting AUTOBOOT_FILE +AUTOBOOT_DELAY = 2 + +# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus +IDE_DISK = 1 + +# Add a short delay when polling status registers +# (required on some broken SATA controllers) +# NOTE: Slows down access significantly, so disable +# whenever possible. +#IDE_DISK_POLL_DELAY = 1 + +# Use PCMCIA compact flash on Via Epia MII10000 and MII6000E +# This device is referred to as hde. +#PCMCIA_CF = 1 + +# Driver for USB Storage +# USB_DISK = 1 + +# VGA text console +VGA_CONSOLE = 1 +PC_KEYBOARD = 1 + +# Serial console +SERIAL_CONSOLE = 1 +SERIAL_IOBASE = 0x3f8 +# if SERIAL_SPEED is commented out, the speed will not be changed. +#SERIAL_SPEED = 115200 + +# Filesystems +FSYS_EXT2FS = 1 +FSYS_FAT = 1 +#FSYS_JFS = 1 +#FSYS_MINIX = 1 +FSYS_REISERFS = 1 +#FSYS_XFS = 1 +FSYS_ISO9660 = 1 + +# Support for boot disk image in bootable CD-ROM (El Torito) +ELTORITO = 1 + +# PCI support +SUPPORT_PCI = 1 + +# Enable this to scan PCI busses above bus 0 +# AMD64 based boards do need this. +PCI_BRUTE_SCAN = 1 + +# Sound support (needs SUPPORT_PCI) +#SUPPORT_SOUND = 1 + +# Sound drivers +#VIA_SOUND = 1 + +# Debugging +DEBUG_ALL = 1 +#DEBUG_ELFBOOT = 1 +#DEBUG_ELFNOTE = 1 +#DEBUG_LINUXBIOS = 1 +#DEBUG_MALLOC = 1 +#DEBUG_MULTIBOOT = 1 +#DEBUG_SEGMENT = 1 +#DEBUG_SYS_INFO = 1 +#DEBUG_TIMER = 1 +#DEBUG_BLOCKDEV = 1 +#DEBUG_PCI = 1 +#DEBUG_VIA_SOUND = 1 +#DEBUG_LINUXLOAD = 1 +#DEBUG_IDE = 1 +#DEBUG_USB = 1 +#DEBUG_ELTORITO = 1 + +# i386 options + +# Loader for standard Linux kernel image, a.k.a. /vmlinuz +LINUX_LOADER = 1 + +# Boot FILO from Multiboot loader (eg. GRUB) +#MULTIBOOT_IMAGE = 1 + Index: buildrom-devel/packages/grub2/grub2.mk =================================================================== --- buildrom-devel.orig/packages/grub2/grub2.mk 2008-06-23 16:37:29.000000000 -0600 +++ buildrom-devel/packages/grub2/grub2.mk 2008-09-21 15:51:11.000000000 -0600 @@ -22,11 +22,13 @@ serial terminal lar terminfo memdisk ata ls \ configfile boot hexdump linux multiboot ext2 +ifeq ($(CONFIG_PAYLOAD_GRUB2),y) HAVE_RUBY:=$(call find-tool,ruby) ifeq ($(HAVE_RUBY),n) $(error To build GRUB2, you need to install 'ruby') endif +endif $(SOURCE_DIR)/$(GRUB2_TAR): @ mkdir -p $(SOURCE_DIR) Index: buildrom-devel/packages/kernel/dbm690t.mk =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/packages/kernel/dbm690t.mk 2008-09-21 15:51:11.000000000 -0600 @@ -0,0 +1,16 @@ +# Build file for the AMD DBM690T LAB kernel + +KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/ +KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2 + +# Kernel config is set in the platform configuration + +$(SOURCE_DIR)/$(KERNEL_SOURCE): + @ mkdir -p $(SOURCE_DIR) + @ wget $(WGET_Q) -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE) + +include $(PACKAGE_DIR)/kernel/kernel.inc + +kernel: generic-kernel +kernel-clean: generic-kernel-clean +kernel-distclean: generic-kernel-distclean Index: buildrom-devel/packages/roms/amd_r690.mk =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/packages/roms/amd_r690.mk 2008-09-22 10:21:09.000000000 -0600 @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_AMD_R690_USE_VBIOS),y) +OPTIONROM_TARGETS += $(AMD_R690_VBIOS_LOCATION) +CBV2_PREPEND := $(AMD_R690_VBIOS_LOCATION) +endif + +$(AMD_R690_VBIOS_LOCATION): + @ $(BIN_DIR)/show-instructions.sh \ + $(PACKAGE_DIR)/roms/amd_r690_instructions \ + $(AMD_R690_VBIOS_LOCATION) + @ echo "Unable to find $(AMD_R690_VBIOS_LOCATION)" + @ exit 1 Index: buildrom-devel/packages/roms/amd_r690_instructions =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/packages/roms/amd_r690_instructions 2008-09-21 15:51:11.000000000 -0600 @@ -0,0 +1,10 @@ +Please follow these instructions for downloading the video BIOS +for your R690 platform: + + * Download the latest video BIOS from: + http://url.goes.here/ + * Copy the file to: + %DESTFILE% + You may need to create the directory first. + +After copying the file, start the build again by typing 'make'. Index: buildrom-devel/packages/roms/roms.mk =================================================================== --- buildrom-devel.orig/packages/roms/roms.mk 2008-08-11 10:04:00.000000000 -0600 +++ buildrom-devel/packages/roms/roms.mk 2008-09-21 15:51:11.000000000 -0600 @@ -1,12 +1,13 @@ # Each platform that needs an option ROM or other binary blob is specified # here -OPTIONROM_TARGETS?= +OPTIONROM_TARGETS ?= -OPTIONROM-y = +OPTIONROMS-y = +OPTIONROMS-$(CONFIG_PLATFORM_DBM690T) += $(PACKAGE_DIR)/roms/amd_r690.mk ifneq ($(OPTIONROMS-y),) -include $(OPTIONROM-y) +include $(OPTIONROMS-y) endif $(ROM_DIR): @@ -15,8 +16,5 @@ roms: $(ROM_DIR) $(OPTIONROM_TARGETS) roms-clean: -ifneq ($(OPTIONROM_TARGETS),) - @ rm -rf $(OPTIONROM_TARGETS) -endif -roms-distclean: roms-clean +roms-distclean: Index: buildrom-devel/bin/show-instructions.sh =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ buildrom-devel/bin/show-instructions.sh 2008-09-22 10:21:09.000000000 -0600 @@ -0,0 +1,7 @@ +#!/bin/sh + +tmp=`tempfile` +cat $1 | sed -e "s:%DESTFILE%:$2:" > $tmp +`dirname $0`/../scripts/kconfig/lxdialog/lxdialog --textbox $tmp 20 75 +rm -rf $tmp +

3 2

coreboot on MS-6380E and/or Intel PM965
by Tomas Kyselica 22 Sep '08

22 Sep '08

Hi *, I would like to ask if it is planned to support MS-6380E motherboard (my old desktop) or Intel PM965 chipset (in my MSI GX700 notebook). Regards Thomas

2 1

r3590 build service
by coreboot information 22 Sep '08

22 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3590 to the coreboot source repository and caused the following changes: Change Log: Patch for AMD DBM690T board. Signed-off-by: Michael Xie <Michael.Xie(a)amd.com> Reviewed-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3590&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3590&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3590&device=epia-cn&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

3 2

r3589 build service
by coreboot information 22 Sep '08

22 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3589 to the coreboot source repository and caused the following changes: Change Log: Patch for AMD SB600 chipset. Most of the functions in SB600 are enabled except power management. Signed-off-by: Michael Xie <Michael.Xie(a)amd.com> Reviewed-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3589&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3589&device=epia-cn&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3588 build service
by coreboot information 22 Sep '08

22 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3588 to the coreboot source repository and caused the following changes: Change Log: Patch for AMD RS690 chipset. All the PCIe slots are enabled in this patch except power management. Signed-off-by: Michael Xie <Michael.Xie(a)amd.com> Reviewed-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3588&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3588&device=epia-cn&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

rs690, sb600, dbm690t patches
by Marc Jones 22 Sep '08

22 Sep '08

Michael had a slight problem sending the patches. There are only three patches to review, rs690.patch, sb600.patch, and dbm690t.patch. Please ignore the osrc-patches(a)elbe.amd.com' emails. Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

2 1

openexpo-stand
by Mich Wyser 22 Sep '08

22 Sep '08

Hi There We share with you a Stand on the OpenExpo together, because we do not need all the place. I want to know, how much space you need ... We will have one Laptop & Prospects on the Stand. Cheers Mich -- Mich Wyser Softwareschneiderei Auweg 6, CH-5102 Rupperswil Phone: +41 32 511 25 54 SIP: callto:41325112554@voipgateway.org (free) skype:softwareschneiderei?call (free) PGP: http://mich.softwareschneiderei.ch/pubkey.txt

2 1

r3590 - in trunk/coreboot-v2: src/mainboard/amd src/mainboard/amd/dbm690t targets/amd targets/amd/dbm690t
by svn＠coreboot.org 22 Sep '08

22 Sep '08

Author: stepan Date: 2008-09-22 15:16:18 +0200 (Mon, 22 Sep 2008) New Revision: 3590 Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c trunk/coreboot-v2/targets/amd/dbm690t/ trunk/coreboot-v2/targets/amd/dbm690t/Config.lb trunk/coreboot-v2/targets/amd/dbm690t/VERSION Log: Patch for AMD DBM690T board. Signed-off-by: Michael Xie <Michael.Xie(a)amd.com> Reviewed-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,302 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + + +## +## Compute the location and size of where this firmware image +## (coreboot plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The coreboot bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of coreboot will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up coreboot, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/si/3114 + +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE + object get_bus_conf.o + object irq_tables.o +end + +#object reset.o + +if USE_DCACHE_RAM + + if CONFIG_USE_INIT + + makerule ./cache_as_ram_auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" + end + + else + + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end + + end + +end +## +## Build our 16 bit and 32 bit coreboot entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (This is where coreboot is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +if USE_DCACHE_RAM + ## + ## Setup Cache-As-Ram + ## + mainboardinit cpu/amd/car/cache_as_ram.inc +end + +### +### This is the early phase of coreboot startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds + else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc + end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + + if CONFIG_USE_INIT + initobject cache_as_ram_auto.o + else + mainboardinit ./cache_as_ram_auto.inc + end + +end + +## +## Include the secondary Configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + +#The variables belong to mainboard are defined here. +#Define system_memory_size, the total memory on mainboard. + +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_S1G1 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + chip drivers/pci/onboard + device pci 5.0 on end # Internal Graphics 0x791F + register "rom_address" = "0xfff00000" + end + end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x1914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "vga_rom_address" = "0xfff00000" + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,301 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses HAVE_ACPI_TABLES +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +uses USE_OPTION_TABLE +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses COREBOOT_EXTRA_VERSION +uses _RAMBASE +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_GDB_STUB +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses HW_MEM_HOLE_SIZEK +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +uses SB_HT_CHAIN_ON_BUS0 + +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_INIT + +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +uses CONFIG_USE_PRINTK_IN_CAR + +uses CONFIG_VIDEO_MB +uses CONFIG_GFXUMA + +### +### Build options +### + +## +## ROM_SIZE is the size of boot ROM that this board will use. +## +default ROM_SIZE=524288 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +#default FALLBACK_SIZE=131072 +#256K +default FALLBACK_SIZE=0x40000 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from coreboot +## +default HAVE_HARD_RESET=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +## +## Move the default coreboot cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=2 + +default CONFIG_MAX_PHYSICAL_CPUS=1 +default CONFIG_LOGICAL_CPUS=1 + +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + +#1G memory hole +default HW_MEM_HOLE_SIZEK=0x100000 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +# BTDC: Only one HT device on Herring. +#HT Unit ID offset +#default HT_CHAIN_UNITID_BASE=0x6 +default HT_CHAIN_UNITID_BASE=0x0 + + +#real SB Unit ID +default HT_CHAIN_END_UNITID_BASE=0x1 + +#make the SB HT chain on bus 0 +default SB_HT_CHAIN_ON_BUS0=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x8000 +default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_INIT=0 + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="dbm690t" +default MAINBOARD_VENDOR="amd" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050 + + +### +### coreboot layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +## +## coreboot C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + + +default CONFIG_USE_PRINTK_IN_CAR=1 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the coreboot loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +default CONFIG_VIDEO_MB=1 +default CONFIG_GFXUMA=1 + +### End Options.lb +end Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +#define RAMINIT_SYSINFO 1 +#define K8_SET_FIDVID 1 +#define QRANK_DIMM_SUPPORT 1 +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define RC0 (6<<8) +#define RC1 (7<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +#define ICS951462_ADDRESS 0x69 +#define SMBUS_HUB 0x71 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#define post_code(x) outb(x, 0x80) + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#include "southbridge/amd/rs690/rs690_early_setup.c" +#include "southbridge/amd/sb600/sb600_early_setup.c" + +/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +/* called in raminit_f.c */ +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/*called in raminit_f.c */ +static inline int spd_read_byte(u32 device, u32 address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" +#include "resourcemap.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + +#include "cpu/amd/model_fxx/fidvid.c" + +#if USE_FALLBACK_IMAGE == 1 + +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + /* Is this a cpu only reset? Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal()) { /* RTC already inited */ + goto normal_image; + } else { + goto fallback_image; + } + } + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } else { + goto fallback_image; + } +normal_image: + post_code(0x23); + __asm__ volatile ("jmp __normal_image": /* outputs */ + :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); + +fallback_image: + post_code(0x25); +} +#endif /* USE_FALLBACK_IMAGE == 1 */ + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; + int needs_reset = 0; + u32 bsp_apicid = 0; + msr_t msr; + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + enable_rs690_dev8(); + sb600_lpc_init(); + + /* it8712f_enable_serial does not use its 1st parameter. */ + it8712f_enable_serial(0, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + printk_debug("bsp_apicid=0x%x\n", bsp_apicid); + + setup_dbm690t_resource_map(); + + setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched */ + wait_all_core0_started(); + start_other_cores(); +#endif + wait_all_aps_started(bsp_apicid); + + ht_setup_chains_x(sysinfo); + + /* run _early_setup before soft-reset. */ + rs690_early_setup(); + sb600_early_setup(); + + msr=rdmsr(0xc0010042); + printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + // show final fid and vid + msr=rdmsr(0xc0010042); + printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + printk_debug("needs_reset=0x%x\n", needs_reset); + + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now; */ + printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", + sysinfo->nodes, sysinfo->ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + rs690_before_pci_init(); + sb600_before_pci_init(); + + post_cache_as_ram(); +} Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/chip.h 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_amd_dbm690t_ops; + +struct mainboard_amd_dbm690t_config +{ + unsigned long uma_size; /* How many UMA should be used in memory for TOP. */ +}; + Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cmos.layout 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/fadt.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> + + + +/** + * Create the Fixed ACPI Description Tables (FADT) for this board. + The FADT defines various fixed hardware ACPI information vital to an ACPI-compatible + OS, such as the base address for the following hardware registers blocks: + PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, + PM2_CNT_BLK, PM_TMR_BLK, GPE0_BLK and GPE1_BLK. + The FADT also has a pointer to the DSDT that contains the Differentiated Definition Block, + which in turn provides variable information to an ACPI-compatible OS concerning the base + system design. + + Not all blocks are necessary usualy only PM1a, PMTMR and GPE0 are used. + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header=&(fadt->header); + + printk_debug("pm_base: 0x%04x\n", pm_base); + + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + + /* Prepare the header */ + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id,OEM_ID,6); + memcpy(header->oem_table_id,"LXBACPI ",8); + memcpy(header->asl_compiler_id,ASLC,4); + header->asl_compiler_revision=0; + + + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt= (u32)dsdt; + + /* + 0: unspecified + 1: desktop + 2: mobile + 3: workstation + 4: enterprise server + */ + fadt->preferred_pm_profile=0x01; + + /* + System vector the SCI interrupt is wired to in 8259 mode. + On systems that do not contain the 8259, this field contains the Global + System interrupt number of the SCI interrupt. OSPM is required to treat + the ACPI SCI interrupt as a sharable, level, active low interrupt. + SB600 BDG 4.1 + */ + fadt->sci_int=4; + + /* + System port address of the SMI Command Port. During ACPI OS initialization, + OSPM can determine that the ACPI hardware registers are owned by SMI (by way + of the SCI_EN bit), in which case the ACPI OS issues the ACPI_ENABLE command + to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the + ACPI hardware registers. OSPM issues commands to the SMI_CMD port + synchronously from the boot processor. + This filed is reserved and must be zero on system that does not support + System Management mode. + */ + fadt->smi_cmd = 0; + + /*Those two fields are reserved and must be zero on systems that do not + support Legacy Mode.*/ + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + +} Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_rs690[8]; +u8 bus_sb600[2]; +unsigned long apicid_sb600; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +unsigned long pci1234x[] = { + 0x0000ff0, +}; + +/* +* HT Chain device num, actually it is unit id base of every ht device in chain, +* assume every chain only have 4 ht device at most +*/ +unsigned long hcdnx[] = { + 0x20202020, +}; + +unsigned long bus_type[256]; + +unsigned long sbdn_rs690; +unsigned long sbdn_sb600; + +extern void get_sblk_pci1234(void); + +static unsigned long get_bus_conf_done = 0; + +void get_bus_conf(void) +{ + unsigned long apicid_base; + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + get_bus_conf_done = 1; + + sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); + sbdn_rs690 = sysconf.sbdn; + sbdn_sb600 = 0; + + for (i = 0; i < 2; i++) { + bus_sb600[i] = 0; + } + for (i = 0; i < 8; i++) { + bus_rs690[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb600[0] = bus_rs690[0]; + + bus_type[bus_rs690[0]] = 1; + + /* sb600 */ + dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4)); + if (dev) { + bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb600[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rs690 */ + for (i = 1; i < 8; i++) { + dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0)); + if (dev) { + bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rs690[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rs690[i]] = 1; /* PCI bus. */ + } + } + } + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(1); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_sb600 = apicid_base + 0; +} Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/irq_tables.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern void get_bus_conf(void); + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_rs690[8]; +extern u8 bus_sb600[2]; +extern unsigned long sbdn_sb600; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb600[0]; + pirq->rtr_devfn = ((sbdn_sb600 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mainboard.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include "chip.h" + +/******************************************************** +* dbm690t uses a BCM5789 as on-board NIC. +* It has a pin named LOW_POWER to enable it into LOW POWER state. +* In order to run NIC, we should let it out of Low power state. This pin +* is controlled by sb600 GPM3. +* RRG4.2.3 GPM as GPIO +* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers: +* I/O C50, C51, C52, PM I/O94, 95, 96. +* RRG4.2.3.1 GPM pins as Input +* RRG4.2.3.2 GPM pins as Output +********************************************************/ +static void enable_onboard_nic() +{ + u8 byte; + + printk_info("enable_onboard_nic.\n"); + + outb(0x13, 0xC50); + + byte = inb(0xC51); + byte &= 0x3F; + byte |= 0x40; + outb(byte, 0xC51); + + byte = inb(0xC52); + byte &= ~0x8; + outb(byte, 0xC52); + + byte = inb(0xC51); + byte &= 0x3F; + byte |= 0x80; /* 7:6=10 */ + outb(byte, 0xC51); + + byte = inb(0xC52); + byte &= ~0x8; + outb(byte, 0xC52); +} + +/************************************************* +* enable the dedicated function in dbm690t board. +* This function called early than rs690_enable. +*************************************************/ +void dbm690t_enable(device_t dev) +{ + struct mainboard_amd_dbm690t_config *mainboard = + (struct mainboard_amd_dbm690t_config *)dev->chip_info; + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk_info("dbm690t_enable, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk_info("dbm690t_enable, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", msr2.lo, msr2.hi); + + switch (msr.lo) { + case 0x10000000: /* 256M system memory */ + uma_memory_size = 0x2000000; /* 32M recommended UMA */ + break; + + case 0x18000000: /* 384M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + break; + } + + uma_memory_start = msr.lo - uma_memory_size;/* TOP_MEM1 */ + printk_info("dbm690t_enable: uma size 0x%08x, memory start 0x%08x\n", uma_memory_size, uma_memory_start); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + uma_memory_start = 0x38000000; /* 1GB system memory supposed */ +#endif + + printk_info("dbm690t_enable. dev=0x%x\n", dev); + + enable_onboard_nic(); +} + +/* +* CONFIG_CHIP_NAME defined in Option.lb. +*/ +struct chip_operations mainboard_amd_dbm690t_ops = { +#if CONFIG_CHIP_NAME == 1 + CHIP_NAME("AMD Dbm690t Mainboard") +#endif + .enable_dev = dbm690t_enable, +}; Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/mptable.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern u8 bus_isa; +extern u8 bus_rs690[8]; +extern u8 bus_sb600[2]; + +extern unsigned long apicid_sb600; + +extern unsigned long bus_type[256]; +extern unsigned long sbdn_rs690; +extern unsigned long sbdn_sb600; + +extern void get_bus_conf(void); + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "ATI "; + static const char productid[12] = "DBM690T "; + struct mp_config_table *mc; + int i, j; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + + /* Bus: Bus ID Type */ + /* define bus and isa numbers */ + for (j = 0; j < bus_isa; j++) { + smp_write_bus(mc, j, (char *)"PCI "); + } + smp_write_bus(mc, bus_isa, (char *)"ISA "); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + u32 dword; + u8 byte; + + dev = + dev_find_slot(bus_sb600[0], + PCI_DEVFN(sbdn_sb600 + 0x14, 0)); + if (dev) { + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb600, 0x11, dword); + + /* Initialize interrupt mapping */ + /* aza */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= 0; /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + + /* SATA */ + dword = pci_read_config32(dev, 0xac); + dword &= ~(7 << 26); + dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ + /* dword |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xac, dword); + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + } + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, + 0x0, apicid_sb600, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x1, apicid_sb600, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0, apicid_sb600, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x3, apicid_sb600, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x4, apicid_sb600, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x6, apicid_sb600, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x7, apicid_sb600, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0xd, apicid_sb600, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0xe, apicid_sb600, 0xe); + + /* usb */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0, 19 << 2 | 0, apicid_sb600, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0, 19 << 2 | 1, apicid_sb600, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0, 19 << 2 | 2, apicid_sb600, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0, 19 << 2 | 3, apicid_sb600, 0x13); + + /* sata */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0, 18 << 2 | 0, apicid_sb600, 22); + + /* HD Audio: b0:d20:f1:reg63 should be 0. */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + 0, 20 << 2 | 0, apicid_sb600, 16); + + /* on board NIC & Slot PCIE. */ + i = 2; + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19); + + /* PCI slots */ + i += 6; + j = 5; + /* PCI_SLOT 0. */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23); + + /* PCI_SLOT 1. */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20); + + /* PCI_SLOT 2. */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_ExtINT, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, + 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, + bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = + smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_dbm690t_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + }; + + int max; + max = sizeof(register_values) / sizeof(register_values[0]); + setup_resource_map(register_values, max); +} Added: trunk/coreboot-v2/targets/amd/dbm690t/Config.lb =================================================================== --- trunk/coreboot-v2/targets/amd/dbm690t/Config.lb (rev 0) +++ trunk/coreboot-v2/targets/amd/dbm690t/Config.lb 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1,21 @@ +# This will make a target directory of ./dbm690t + +target dbm690t +mainboard amd/dbm690t + +romimage "normal" + option ROM_SIZE = 1024*1024 - 55808 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x20000 + payload ../payload.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x20000 + payload ../payload.elf +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" Added: trunk/coreboot-v2/targets/amd/dbm690t/VERSION =================================================================== --- trunk/coreboot-v2/targets/amd/dbm690t/VERSION (rev 0) +++ trunk/coreboot-v2/targets/amd/dbm690t/VERSION 2008-09-22 13:16:18 UTC (rev 3590) @@ -0,0 +1 @@ +_dbm690t

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coreboot September 2008